CN222337928U - Memory card timing test device - Google Patents

Abstract

The utility model discloses a memory card timing test device, comprising: a host computer; a test socket, a signal output interface is provided on the test socket, the signal output interface is connected to the signal pin of the memory card to be tested; a signal acquisition module, the signal acquisition module is electrically connected to the signal output interface; the signal acquisition module comprises an analog-to-digital converter and an SPI controller provided on the analog-to-digital converter, the SPI controller is used to configure the analog-to-digital converter, and the analog-to-digital converter and the SPI controller are both electrically connected to the host computer. The utility model detects the type of the current memory card to be tested by the host computer, and through the SPI controller in the signal acquisition module, the analog-to-digital converter can configure different signal acquisition modes according to different types of memory cards to be tested, completes the timing test of the memory card to be tested at the fastest speed, realizes the automatic test of different types of memory cards to be tested, saves manpower and time costs, and improves the test efficiency.

Description

Testing device for memory card time sequence

Technical Field

The present utility model relates to the field of chip timing testing technologies, and in particular, to a testing apparatus for a memory card timing.

Background

With the enrichment of various multimedia entertainment contents, consumers have increasingly high requirements on the storage capacity of electronic products used, so that memory cards are widely applied to various electronic devices. A memory card is a small-sized removable memory device that stores data through flash memory technology, is diverse in kind, and is generally connected to the device using a specific interface.

In order to ensure the stable and reliable operation of the memory card, manufacturers generally test the sampling time sequence of the memory card during production. The existing time sequence testing method mainly realizes testing (such as equipment of a signal source, a logic analyzer and the like) through related instruments, is complex in operation, cannot test different types of memory cards, cannot automatically record data after analysis processing, and causes great waste to manpower.

Disclosure of utility model

The utility model mainly aims to provide a testing device for a time sequence of a memory card, which aims to solve the problem that the time sequence test cannot be carried out on different types of memory cards.

To achieve the above object, the present utility model provides a test device for testing a memory card timing sequence for testing a secure digital memory card (Secure Digital Memory Card, SD card) and an Embedded multimedia card (Embedded Multi MEDIA CARD, EMMC card), the test device comprising:

An upper computer;

The test seat is provided with a signal output interface which is connected with a signal pin of the memory card to be tested;

The signal acquisition module is electrically connected with the signal output interface;

The signal acquisition module comprises an analog-to-digital converter and an SPI controller arranged on the analog-to-digital converter, the SPI controller is used for configuring the analog-to-digital converter, and the analog-to-digital converter and the SPI controller are electrically connected with the upper computer.

In some embodiments, the memory card timing test apparatus further includes an editable logic gate array module (Filed Programmable GATE ARRAY, FPGA) electrically connecting the host computer and the signal acquisition module.

In some embodiments, the analog-to-digital converter is electrically connected to the programmable logic gate array module through an FMC interface (FPGA Mezzanine Card), and the SPI controller is connected to the programmable logic gate array module through an SPI interface.

In some embodiments, the test device for memory card timing further includes a clock synchronization module electrically connected to the signal acquisition module, the editable logic gate array module, and the test socket, for controlling clock synchronization of the signal acquisition module, the editable logic gate array module, and the memory card under test.

In some embodiments, the clock synchronization module includes a phase locked loop circuit.

In some embodiments, the test device further comprises a signal conversion module, and the signal acquisition module is electrically connected with the test seat through the signal conversion module.

In some embodiments, the signal conversion module includes an operational amplifier unit and a differential driving chip, the operational amplifier unit is electrically connected with the test socket, the differential driving chip is electrically connected with the operational amplifier unit, and the signal acquisition module is electrically connected with the differential driving chip.

In some embodiments, the test apparatus further comprises a first-in first-out memory (First Input First Output, FIFO) through which the programmable logic gate array module is electrically connected to the upper computer.

In some embodiments, the test device further comprises a flash memory module electrically connected to the editable logic gate array module, the flash memory module having operating firmware stored therein.

In some embodiments, the test device further comprises a power module electrically connected to the signal acquisition module and the test socket.

According to the utility model, the type of the current memory card to be tested is detected by the upper computer, and the analog-to-digital converter can be configured with different signal acquisition modes according to different types of memory cards to be tested by the SPI controller in the signal acquisition module, so that the time sequence test of the memory cards to be tested can be completed at the highest speed, the automatic test of different types of memory cards to be tested is realized, the labor and time cost are saved, and the test efficiency is improved.

Drawings

FIG. 1 is a schematic diagram of a testing apparatus for testing a memory card timing sequence according to an embodiment of the present utility model;

FIG. 2 is a schematic diagram of another embodiment of a memory card timing testing apparatus according to the present utility model;

FIG. 3 is a schematic diagram of a testing apparatus for testing a memory card timing sequence according to another embodiment of the present utility model;

FIG. 4 is a schematic diagram of a testing apparatus for testing the timing of a memory card according to another embodiment of the present utility model;

FIG. 5 is a schematic diagram of a testing apparatus for testing the timing of a memory card according to another embodiment of the utility model.

Reference numerals:

10. The system comprises an upper computer, a signal conversion module, an analog-to-digital converter, a SPI controller, a 30, a test seat, a 40, an editable logic gate array module, a 50, a clock synchronization module, a 60, a signal conversion module, a 61, an operational amplifier unit, a 62, a differential driving chip, a 70, a first-in first-out memory, a 80 and a flash memory module.

Detailed Description

The following description of the embodiments of the present utility model will be made more clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be noted that all directional indicators (such as up, down, left, right, front, and rear are used in the embodiments of the present utility model) are merely for explaining the relative positional relationship, movement conditions, and the like between the components in a certain specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicators are changed accordingly.

It will also be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present utility model.

The utility model proposes a testing device of the memory card time sequence, is used for testing the safe digital memory card and embedded multimedia card, refer to figure 1, this testing device includes:

An upper computer 10;

The test seat 30 is provided with a signal output interface, and the signal output interface is connected with a signal pin of the memory card to be tested;

The signal acquisition module 20 is electrically connected with the signal output interface;

The signal acquisition module 20 comprises an analog-to-digital converter 21 and an SPI controller 22 arranged on the analog-to-digital converter 21, wherein the SPI controller 22 is used for configuring the analog-to-digital converter 21, and the analog-to-digital converter 21 and the SPI controller 22 are electrically connected with the upper computer 10.

When the test is started, the upper computer 10 issues a test command to the signal acquisition module 20, and after the SPI controller 22 in the signal acquisition module 20 identifies the type of the memory card to be tested, the working mode of the analog-to-digital converter 21 is configured, that is, the number of suitable signal acquisition channels is set, wherein the signal acquisition channels are the connection channels of the signal output interface and the signal pins of the memory card to be tested. For example, if the secure digital memory card, that is, the SD card is tested, the signal output interface of the test socket 30 is only connected to 4 data transmission pins of the SD card and is connected to CLK and CMD pins of the SD card, wherein the CLK pin is used for outputting clock signals for synchronizing data transmission and driving operation of the device, and the CMD pin is used for interaction between the memory card and the signal acquisition module 20, and if the embedded multimedia card, that is, the EMMC card is tested, the signal output interface of the test socket 30 can be connected to all data transmission pins of the EMMC card and CLK and CMD pins for faster data acquisition.

Then, the signal acquisition module 20 starts the signal acquisition function according to the test command of the upper computer 10, receives the signal output from the test socket 30, converts the signal into a digital signal, and transmits the converted signal to the upper computer 10 for further analysis, and the upper computer 10 rapidly analyzes and compares the standard time sequence threshold (usually the SD card/EMMC card reference value range of each manufacturer) to finally display the time sequence result. Preferably, after the test is completed, the test result may be stored in a predetermined memory module, and the analog timing pattern of each channel and the corresponding recommended measures are displayed on a display module connected to the host computer 10.

The upper computer 10 may be a computer device or an embedded system, and is used for controlling and monitoring the testing process, and analyzing and displaying the collected testing result. The upper computer 10 can interact with staff, the staff inputs parameters, test mode and other relevant configuration information of the memory card to be tested through an operation interface of the upper computer 10, or a test program can be stored in the upper computer 10 in advance, so that the upper computer 10 automatically completes the test of the memory card to be tested, and the test result is analyzed.

The test seat 30 is used for connecting a memory card to be tested, and a signal output interface is arranged on the test seat 30 and used for outputting various signals of the memory card to be tested. Wherein the signal output interface is typically an SDIO interface (Secure Digital Input and Output, secure digital input output interface). Preferably, the test socket 30 can be connected with a plurality of memory cards to be tested, and is provided with a plurality of signal output interfaces corresponding to the memory cards to be tested one by one, so that the time sequence of the memory cards to be tested can be tested simultaneously, and the test efficiency is improved.

According to the utility model, the type of the current memory card to be tested is detected by the upper computer 10, and the analog-to-digital converter 21 can be configured with different signal acquisition modes according to different types of memory cards to be tested by the SPI controller 22 in the signal acquisition module 20, so that the time sequence test of the memory cards to be tested can be completed at the highest speed, the automatic test of different types of memory cards to be tested is realized, the labor and time cost are saved, and the test efficiency is improved.

As shown in fig. 2, in some embodiments, the test apparatus for memory card timing further includes an editable logic gate array module 40, where the editable logic gate array module 40 is electrically connected to the host computer 10 and the signal acquisition module 20. Because the memory cards to be tested of different brands or models have differences, and the time sequence threshold of the memory card to be tested needs to be adjusted according to application scenes, the test parameters may also be different, and the editable logic gate array module 40 (hereinafter referred to as FPGA module) not only can program the memory card to be tested according to specific requirements, but also can be programmed and reconfigured for multiple times, so that staff can perform quick iteration and modification according to the requirements without redesigning hardware.

After the FPGA module is arranged, the FPGA module can be connected with the upper computer 10 in a handshake way before testing to judge whether normal testing can be performed. The FPGA module is used for sending a handshake signal to the upper computer 10 after loading a starting program, if the upper computer 10 receives the handshake signal and then is connected with the FPGA module, the FPGA module enters an idle waiting mode, if the upper computer 10 is not connected with the FPGA module, the FPGA module continues to send the handshake signal, three continuous connection failures occur, the test is stopped, an alarm signal is sent, information such as error reasons, error codes and the like is reported, and workers are reminded of processing. It can be appreciated that the upper computer 10 can also be connected to the FPGA module by manual confirmation by a worker.

As shown in fig. 2, in some embodiments, analog-to-digital converter 21 is electrically connected to editable logic gate array module 40 via an FMC interface, and SPI controller 22 is connected to editable logic gate array module 40 via an SPI interface.

The FMC interface is an interface for connecting the FPGA module, supports high-speed serial connection, is suitable for application scenes requiring high bandwidth and low delay, and is generally provided with a plurality of connection pins, and can support a plurality of different types of peripherals or modules, so that the FMC interface has strong expandability, and can directly add new modules without large-scale modification of the whole system when the functions are required to be expanded. The SPI interface generally supports high-speed transmission, has a higher data transmission rate, and supports full duplex communication, allowing data to be transmitted and received simultaneously, thereby achieving higher communication efficiency, and the SPI controller 22 is connected with the FPGA module through the SPI interface, so that the FPGA module can control the signal acquisition module 20 more quickly and conveniently.

As shown in fig. 3, in some embodiments, the test apparatus for memory card timing further includes a clock synchronization module 50, where the clock synchronization module 50 is electrically connected to the signal acquisition module 20, the programmable logic gate array module 40, and the test socket 30, and is used to control the signal acquisition module 20, the programmable logic gate array module 40, and the memory card under test to be clock-synchronized.

The clock synchronization module 50 is connected with the signal acquisition module 20, the editable logic gate array module and the test seat 30 to receive clock signals from the memory to be tested, and adjusts the clock signals of the signal acquisition module 20 and the editable logic gate array module according to the clock signals, so that the clock signals are synchronized with the clock signals of the memory to be tested, and test errors caused by clock deviation or jitter are reduced, so that accuracy and stability of test time sequence signals are ensured. Further, by setting the clock synchronization module 50, the clock frequency can be dynamically adjusted in the communication process, and the clock frequency is controlled to be in the minimum range, so as to save electric energy and realize the data flow control function.

In some embodiments, clock synchronization module 50 includes a phase-locked loop circuit. The phase-locked loop circuit is mainly used for generating a stable and accurate output signal, and the phase and frequency of the output signal are kept synchronous with the input reference clock, so that after receiving the clock signal of the memory card to be tested, the clock of the signal acquisition module 20 and the clock of the memory card to be tested can be kept consistent continuously.

As shown in fig. 4, in some embodiments, the test apparatus further includes a signal conversion module 60, and the signal acquisition module 20 is electrically connected to the test socket 30 through the signal conversion module 60. Since the signal output by the memory card to be tested is weak and is not easily read by the signal acquisition module 20, the signal conversion module 60 is used to optimize the signal and convert it into a stable and easily readable form. During testing, the signal conversion module 60 receives the signal output by the memory card to be tested, then the signal conversion module 60 converts the signal, the signal acquisition module 20 receives and processes the converted signal, and finally the converted signal is transmitted to the upper computer 10. Further, because the types and signals of the memory card to be tested are different, the number of the signal pins is also different, and a plurality of signal conversion modules 60 can be arranged to correspondingly connect a plurality of signal pins, so that the signals output by each signal pin are converted, and the upper computer 10 can conveniently read and analyze the signals.

As shown in fig. 4, in some embodiments, the signal conversion module 60 includes an operational amplifier unit 61 and a differential driving chip 62, the operational amplifier unit 61 is electrically connected with the test socket 30, the differential driving chip 62 is electrically connected with the operational amplifier unit 61, and the signal acquisition module 20 is electrically connected with the differential driving chip 62.

The operational amplifier unit 61 is used for amplifying the signal output by the memory card to be tested and converting the signal into a single-ended signal, so that the signal can be conveniently read later. The differential driving chip 62 can receive the single-ended signal from the operational amplifier unit 61 and convert the single-ended signal into a differential signal, the differential signal has better performance in terms of anti-interference and transmission distance, and the stability and anti-interference capability of the signal can be improved by converting the single-ended signal into the differential signal. The differential signals are transmitted to the signal acquisition module 20, the analog-to-digital converter 21 in the signal acquisition module 20 converts the differential signals into digital signals, namely, the conversion of the signals is realized, the converted signals are transmitted to the FPGA module for processing, and finally, the signals are transmitted to the upper computer 10, so that the upper computer 10 can read and analyze the signals conveniently.

As shown in FIG. 5, in some embodiments, the test apparatus further comprises a first-in first-out memory 70, and the programmable logic gate array module is electrically connected to the host computer 10 through the first-in first-out memory 70. The FIFO is used to alleviate the difference in data processing speed between the programmable logic gate array module and the host computer 10, and because the host computer 10 is responsible for more complex analysis and storage operations, the processing speed is often slower than that of the programmable logic gate array module, and at this time, the data generated by the programmable logic gate array module can be temporarily stored through the FIFO, so that the host computer 10 can process the data at a normal speed without losing the data. By providing temporary storage and data flow control, the FIFO can ensure normal operation of the system and improve the stability of the system.

As shown in fig. 5, in some embodiments, the test apparatus further includes a flash memory module 80, the flash memory module 80 is electrically connected to the editable logic gate array module, and the flash memory module 80 stores operating firmware. When testing is needed, the editable logic gate array module can directly read the firmware from the flash memory. Because the firmware is directly loaded into the hardware, the starting time of the test can be shortened, the firmware is tightly combined with the hardware, is less influenced by an external environment or an operating system, and is not easy to fail or crash.

In some embodiments, the test device further includes a power module electrically connected to the signal acquisition module 20 and the test socket 30. It can be appreciated that the power supply module can provide appropriate voltages to the signal acquisition module 20 and the test socket 30, so that the whole test device can operate smoothly, and faults are prevented.

The above description of the preferred embodiments of the present utility model should not be taken as limiting the scope of the utility model, but rather should be understood to cover all modifications, variations and adaptations of the present utility model using its general principles and the following detailed description and the accompanying drawings, or the direct/indirect application of the present utility model to other relevant arts and technologies.

Claims (10)

1. A memory card timing test apparatus for testing secure digital memory cards and embedded multimedia cards, the test apparatus comprising:

An upper computer;

The test seat is provided with a signal output interface which is connected with a signal pin of the memory card to be tested;

The signal acquisition module is electrically connected with the signal output interface;

The signal acquisition module comprises an analog-to-digital converter and an SPI controller arranged on the analog-to-digital converter, the SPI controller is used for configuring the analog-to-digital converter, and the analog-to-digital converter and the SPI controller are electrically connected with the upper computer.

2. The test device of claim 1, wherein the memory card timing test device further comprises an editable logic gate array module electrically connecting the host computer and the signal acquisition module.

3. The test device of claim 2, wherein the analog-to-digital converter is electrically connected to the programmable logic gate array module via an FMC interface, and wherein the SPI controller is connected to the programmable logic gate array module via an SPI interface.

4. The test device of claim 3, wherein the memory card timing test device further comprises a clock synchronization module electrically connected to the signal acquisition module, the programmable logic gate array module, and the test socket for controlling the signal acquisition module, the programmable logic gate array module, and the memory card under test to be clocked.

5. The test device of claim 4, wherein the clock synchronization module comprises a phase locked loop circuit.

6. The test device of claim 5, further comprising a signal conversion module, wherein the signal acquisition module is electrically connected to the test socket via the signal conversion module.

7. The test device of claim 6, wherein the signal conversion module comprises an operational amplifier unit and a differential drive chip, the operational amplifier unit is electrically connected with the test socket, the differential drive chip is electrically connected with the operational amplifier unit, and the signal acquisition module is electrically connected with the differential drive chip.

8. The test device of claim 2, further comprising a first-in first-out memory, wherein the programmable logic gate array module is electrically coupled to the upper computer via the first-in first-out memory.

9. The test device of claim 2, further comprising a flash memory module electrically connected to the programmable logic gate array module, the flash memory module having operating firmware stored therein.

10. The test device of any one of claims 1-9, further comprising a power module electrically connected to the signal acquisition module and the test socket.