Circuit for increasing charge pump charge rate
Technical Field
The utility model belongs to the technical field of electronic circuits, and particularly relates to a circuit for improving the charge rate of a charge pump.
Background
A Charge Pump (Charge Pump), also called a switched capacitor voltage converter, is a DC/DC converter that uses a capacitor to store energy, and can raise or lower an input voltage, and an internal FET (FIELD EFFECT Transistor) switch array controls the Charge and discharge operations of a Pump capacitor in a certain manner, so that the input voltage is raised or lowered by a certain factor, thereby obtaining a required output voltage. Charge pumps are generally classified into three main categories, switching regulator booster pumps, unregulated capacitive charge pumps, and adjustable capacitive charge pumps. The application of the high-side power transistor is very wide, and the high-side power transistor is commonly applied to a gate driver, and in the gate driver application, the high-side driver needs to output a high level higher than a power supply voltage to drive the high-side power transistor, so that the power supply voltage needs to be subjected to boosting treatment to supply power for the high-side driver.
The simple charge pump structure block diagram shown in fig. 1 comprises a clock signal processing circuit, a driving circuit, a charge-discharge circuit and a sampling detection circuit. Because the set-up time of the output voltage of the charge pump is a charging and discharging process, the time for the output voltage to rise to the set voltage is the set-up time of the charge pump, the set-up time of the charge pump circuit represents the driving capability of the charge pump, and the shorter the set-up time of the circuit is, the stronger the driving capability of the charge pump is. Therefore, the setup time parameter of the charge pump is an important parameter index. The prior art charge pump boosting has the problem that the voltage VCP needs to be increased to a voltage value which is not less than the voltage VM of the power supply, and the required pump capacitance is relatively large, so that the VCP is established for a relatively long time and the efficiency is relatively low. The setup time of the charge pump is long, resulting in weak driving capability of the charge pump.
Disclosure of utility model
In view of the above, the present utility model provides a circuit for increasing the charge rate of a charge pump.
In order to solve the technical problems, the utility model adopts the following technical scheme:
A circuit for improving charge rate of a charge pump comprises a sampling module, a comparator, an oscillator, a high-voltage power supply, a high-voltage bias module, a low-voltage bias module, a high-side power tube, a low-side power tube, a first diode, a second diode, a pump capacitor and a filter capacitor, wherein the input end of the sampling module is connected with output voltage of the charge pump, the output end of the sampling module is connected with an in-phase end of the comparator, an inverting input end of the comparator is connected with reference voltage, the output end of the comparator is connected with an input end of the high-voltage bias module, the oscillator outputs a first clock signal with a certain frequency, the output end of the oscillator is respectively connected with the high-voltage bias module, the low-voltage bias module and an input end of the high-voltage power supply, the other input end of the high-voltage power supply is connected with a power supply VM, the high-level power tube outputs a high-level VM, the low-level is 0 and is in phase with a second clock signal of the first clock signal, the output end of the high-side power tube is connected with an input end of the high-side power tube, the output end of the sampling module is connected with an input end of the comparator, the inverting input end of the low-side power tube is connected with the low-side power tube, the output end of the comparator is connected with the high-side power tube, the output end of the high-voltage bias module is connected with an input end of the high-level power tube, the CPL is connected with the charge pump, the high-level pump is connected with the voltage, the other end of the charge pump is connected with the charge pump, and the charge pump is connected with the other end of the charge pump.
In one possible implementation manner, the high-side power tube is an NMOS power tube.
In one possible implementation manner, the low-side power transistor is an NMOS power transistor.
In one possible implementation manner, the high-voltage power supply includes a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor.
In one possible implementation manner, the sources of the first PMOS tube and the second PMOS tube are connected with a power supply, the drain electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube and is connected with bias current, the grid electrode of the first NMOS tube is connected with the output of the oscillator, the source electrode of the first NMOS tube is grounded, and the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube to serve as the output end of the high-voltage power supply.
The utility model has the following beneficial effects:
(1) The VCP establishment time can be effectively shortened, the efficiency is higher, and the driving capability of the charge pump is stronger.
(2) The circuit part has the advantages of simple circuit structure, low power consumption and strong applicability.
Drawings
FIG. 1 is a schematic block diagram of a charge pump of the prior art;
FIG. 2 is a schematic block diagram of a circuit for increasing the charge rate of a charge pump according to an embodiment of the present utility model;
FIG. 3 is a schematic diagram of a high voltage power supply in a circuit for increasing charge rate of a charge pump according to an embodiment of the present utility model;
fig. 4 is a schematic diagram of a VCP setup time waveform according to a prior art scheme and an embodiment of the present utility model.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
Referring to fig. 2, a schematic block diagram of a circuit for increasing a charge rate of a charge pump according to an embodiment of the present utility model is shown, which includes a sampling module 12, a comparator 13, an oscillator 14, a high-voltage power supply 17, a high-voltage bias module 15, a low-voltage bias module 16, a high-side power tube 18, a low-side power tube 19, a first diode 20, a second diode 21, a pump capacitor 23 and a filter capacitor 22, wherein an input end of the sampling module 12 is connected with an output voltage VCP of the charge pump, an output end of the sampling module 12 is connected with an in-phase end of the comparator 13, an inverting input end of the comparator 13 is connected with a reference voltage REF, and an output end of the comparator 13 is connected with an input end of the high-voltage bias module 15; the oscillator 14 outputs a first oscillating clock signal with a certain frequency, the output end of the oscillator is respectively connected with the high-voltage bias module 15, the low-voltage bias module 16 and one input end of the high-voltage power supply 17, the other input end of the high-voltage power supply 17 is connected with the power supply VM, the high-voltage power supply outputs a second clock signal with high level of VM and low level of 0 and same phase with the first clock signal, the oscillator is connected with one input end of the high-side power tube 18, the output end of the high-voltage bias module 15 is connected with one input end of the high-side power tube 18, the output end of the low-voltage bias module 16 is connected with one input end of the low-side power tube 19, one output ends of the high-side power tube 18 and the low-side power tube 19 are connected with the low-potential CPL of the charge pump switch, the cathodes of the first diode 20 and the anodes of the second diode 21 are connected with the high-potential CPH of the charge pump switch, the anodes of the first diode are connected with the power supply VM, the cathodes of the second diode are connected with the output voltage VCP of the charge pump, one end of the filter capacitor 22 is connected with the power supply VM, the other end of the filter capacitor 22 is connected with the output voltage of the charge pump output voltage, one end of the charge pump 23 is connected with the low-potential CPL of the charge pump switch, the other end of the pump capacitor 23 is connected to the charge pump switch high potential CPL.
In the circuit for improving the charge rate of the charge pump according to an embodiment of the present utility model, the high-side power transistor 18 and the low-side power transistor 19 are NMOS power transistors.
With continued reference to fig. 3, the high voltage power supply in the circuit for increasing the charge rate of the charge pump according to an embodiment of the present utility model includes a first PMOS transistor 24, a second PMOS transistor 25, and a first NMOS transistor 27. The first PMOS tube 24 and the second PMOS tube 25 are connected with power sources, the drain electrode of the first PMOS tube 24 is connected with the grid electrode, and is connected with the grid electrode of the second PMOS tube 25 and is connected with bias current, the grid electrode of the first NMOS tube 27 is connected with the output of the oscillator, the source electrode of the first NMOS tube 27 is grounded, and the drain electrode of the second PMOS tube 25 and the drain electrode of the first NMOS tube 24 are connected to serve as output ends of a high-voltage power source.
With circuitry provided for increasing the charge pump charge rate, the sampling module 12 detects the charge pump output voltage VCP and outputs a voltage proportional to VCP. The comparator 13 compares the voltage output from the sampling circuit 12 with the reference voltage REF, and outputs a high-low level signal. The high-voltage bias module 15 receives the clock signal of the oscillator 14 and outputs a level signal HO with high-low variation for controlling the high-side power tube 18, the low-voltage bias module 16 receives the clock signal of the oscillator 14 and outputs a level signal LO with high-low variation for controlling the low-side power tube 19, the high-side power tube 18 and the low-side power tube 19 output signal high-low oscillation signals CPL, the CPH node voltage is continuously charged and discharged through the pump capacitor 23 to raise, and the CPH node voltage is unidirectionally transmitted to the VCP through the diode 21, and finally the charge pump voltage VCP larger than the power supply voltage VM is obtained. The high voltage power supply 17 receives the clock signal provided by the oscillator 14, outputs a second clock signal with a high level VM and a low level 0 and in phase with the first clock signal, and controls the high side power transistor 18 to be turned on and off together with the high voltage bias 15. When the VM power supply supplies power, the oscillator 14 outputs the clock signal control signals HO and LO to output high and low levels, and when the HO output is high and the LO output low level, the high voltage bias module 15 outputs a voltage lower than the VM voltage and the high voltage power supply 17 outputs the VM voltage because the VCP is not yet charged, so that the HO output high level VM voltage and the CPL output voltage VM-V GS,18. When the HO output is low and the LO output is high, the CPL output voltage is 0, so the CPL outputs a square wave signal with a high level VM-V GS,18 and a low level 0 under the clock control of the oscillator 14, where V GS,18 is the voltage between the gate and the source of the high-side power transistor 18. Thereafter, the VCP voltage is raised by charging and discharging by the pump capacitor 23. Compared with the prior art, the CPL high-level voltage is VM-V GS, and the CPL high-level voltage in the prior art is VM-2V Z-VGS, so the CPL is VM-V GS from high level, The pump capacitor is charged and discharged from a low level of 0, while the prior art scheme CPL is charged and discharged from a high level of VM-V GS-2VZ and a low level of 0, in contrast, the embodiment of the utility model has shorter charge and discharge time and higher efficiency, thereby shortening the VCP establishment time. As shown in the following timing chart fig. 4, t1 is the prior art VCP setup time, t2 is the inventive technical VCP setup time, and t2 is less than t1.
It should be understood that the exemplary embodiments described herein are illustrative and not limiting. Although one or more embodiments of the present utility model have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present utility model as defined by the following claims.