CN222167280U

CN222167280U - CPO optical module packaging structure

Info

Publication number: CN222167280U
Application number: CN202420461100.3U
Authority: CN
Inventors: 于圣韬; 葛崇祜; 刘军; 郝沁汾
Original assignee: Xinlihui Technology Wuxi Co ltd; Wuxi Core Optical Interconnect Technology Research Institute Co ltd
Current assignee: Xinlihui Technology Wuxi Co ltd; Wuxi Core Optical Interconnect Technology Research Institute Co ltd
Priority date: 2024-03-11
Filing date: 2024-03-11
Publication date: 2024-12-13
Anticipated expiration: 2034-03-11

Abstract

The utility model relates to the technical field of optical packaging, and specifically discloses a CPO optical module packaging structure, including: a housing component, including a housing top part and a housing bottom part that are relatively arranged; a substrate component, located above the housing bottom part; a reconstructed electric chip component, located on the side of the substrate component away from the housing bottom part, and bonded to the substrate component; an optical chip component, flipped on the side of the reconstructed electric chip component away from the substrate component, and at least electrically connected to the driver of the reconstructed electric chip component; an optical fiber array component, located on the side of the reconstructed electric chip component away from the substrate component; a heat conductive component, at least including a first heat conductive pad located between the reconstructed electric chip component and the housing top part, and a second heat conductive pad located between the reconstructed electric chip component and the housing bottom part. The CPO optical module packaging structure provided by the utility model has the advantage of high integration.

Description

CPO optical module packaging structure

Technical Field

The utility model relates to the technical field of optical packaging, in particular to a CPO optical module packaging structure.

Background

With the increasing capacity of ASIC chips for data centers and AI applications, the transmission rate of high-speed optical modules has evolved from 100 Gbps to 800Gbps. For a single optical module, the number of optoelectronic chips and the number of internal channels on the internal PCB (Printed Circuit Board ) board also increases. On the premise of meeting the packaging standard of the existing optical module and switch, realizing multi-chip, high-integration and low-loss interconnection, and manufacturing a reliable and low-insertion-loss optical coupling packaging scheme matched with the packaging design, the method is an important technical challenge facing future optical modules and CPO (Co-packaged Optics, photoelectric Co-packaging) modules.

The current commonly used optical module product with the speed of more than 400Gbps mainly meets the module packaging standard related to QSFP and OSFP, and the width of an internal patch area is generally 16 mm-18.5 mm. At present, the highest speed of a transmitting module chip (laser chip, modulator chip, driver chip) and a receiving module chip (detector and transimpedance amplifier) which are produced in mass at home is generally about 400 Gbps. Therefore, with the increase of the capacity of the switch, the increase of the number of photoelectric chips and the single chip size inside the incoherent optical module with the speed of more than 800Gbps is an unavoidable problem. Meanwhile, the interconnection of the optoelectronic chips inside the optical module is mainly a COB (Chip On Board) process, and the interconnection mode of wire bonding often occupies a larger On-Board space, and the increasing number of wires also causes delay and accumulation of power consumption.

Currently, advanced packaging is one of the solutions to increase the integration level and the number of I/O interfaces per unit area. However, since the PIC (Photonics Integrated Circuit, photonic integrated chip) is a heat sensitive device with small coupling tolerance, and the end-face coupler on the PIC is usually located at the edge of the chip, the present advanced packaging process is difficult to effectively protect the PIC optical port structure, and is difficult to adapt to a stable and reliable optical connection scheme at the same time.

The inventor finds that part of the loss and delay sources of the existing high-speed optical module are caused by the increase of the integrated level and the accumulated lead number when the packaging form of the optical module is studied, and the bonding Pad (Pad) type is mainly positive-mounted due to the chip mounting mode of COB, so that the area of the chip surface which can be attached with the radiating fin is smaller.

Therefore, how to provide an optical module packaging structure with high integration and low loss is a technical problem to be solved by those skilled in the art.

Disclosure of Invention

The utility model provides a CPO optical module packaging structure, which solves the problems of low integration level and high loss in the related technology.

As one aspect of the present utility model, there is provided a CPO optical module package structure, including:

A housing assembly including oppositely disposed housing top and bottom portions;

a base plate assembly located above and connected to the housing bottom portion;

The reconstructed electric chip component is positioned on one side of the substrate component, which is away from the bottom part of the shell, and is connected with the substrate component in a bonding way, wherein the reconstructed electric chip component is formed by at least encapsulating a photoelectric detector, a transimpedance amplifier and a driver together;

The optical chip assembly is flipped on one side of the reconfiguration electric chip assembly, which is away from the substrate assembly, and is at least electrically connected with a driver of the reconfiguration electric chip assembly;

The optical fiber array component is positioned at one side of the reconstruction electric chip component, which is away from the substrate component, and is respectively coupled with the photoelectric detector and the optical chip component;

A thermally conductive assembly including at least a first thermally conductive pad between the reconstituted electrical chip assembly and the top portion of the housing and a second thermally conductive pad between the reconstituted electrical chip assembly and the bottom portion of the housing;

The housing top portion is located on a side of the reconstituted electrical chip assembly facing away from the substrate assembly and covers at least the optical chip assembly, the optical fiber array assembly and the first thermally conductive pad.

Further, the reconstituted electrical chip assembly comprises:

the chip layer comprises an injection molding material body, an electrical lead-in unit embedded in the injection molding material body, and a photoelectric detector, a transimpedance amplifier and a driver which are arranged at intervals;

The first rewiring layer is connected to the upper surface of the chip layer and can be used for respectively realizing the electrical connection between the photoelectric detector and the electrical introduction unit, between the driver and the electrical introduction unit and between the photoelectric detector and the transimpedance amplifier, wherein the upper surface of the chip layer is one side of the reconstructed electrical chip component, which is far away from the substrate component;

The first electrical connection piece is positioned on the surface of the first rewiring layer, which is away from the chip layer, and at least realizes the electrical connection between the driver and the optical chip assembly;

The second rewiring layer is connected to the lower surface of the chip layer and is electrically connected with the electrical lead-in unit of the chip layer, wherein the lower surface of the chip layer is one side of the reconstructed electrical chip assembly facing the substrate assembly;

The second electrical connection piece is positioned on the surface of the second redistribution layer, which is away from the chip layer, and at least realizes the electrical connection between the reconfiguration electrical chip assembly and the substrate assembly.

Further, the optical chip assembly includes a chip body, an end face coupler formed on the chip body, and a third electrical connection member, where the third electrical connection member contacts with the first electrical connection member to electrically connect the driver and the optical chip assembly.

Further, the fiber array assembly includes a first fiber array assembly portion and a second fiber array assembly portion,

The first optical fiber array component part is positioned on the surface of the reconfiguration electric chip component, which is far away from the substrate component, the end surface of the first optical fiber array component part is coupled with the end surface of the photoelectric detector, a coupling area between the first optical fiber array component part and the photoelectric detector is filled with transparent dielectric materials, and a metal connecting wire of a first rewiring layer is not arranged in the coupling area;

The second optical fiber array component is partially positioned on the side surface of the optical chip component, which is away from the first heat conduction gasket;

Wherein the first fiber array assembly portion is coupled to the photodetector and the second fiber array assembly portion is coupled to the optical chip assembly.

Further, the substrate assembly comprises a PCB and a fourth electrical connector formed on the surface of the PCB;

a step-shaped PCB through hole is formed on the PCB, and a metal heat sink material is filled in the step-shaped PCB through hole;

The fourth electrical connection piece is in contact with the second electrical connection piece of the reconfiguration electrical chip assembly to realize the electrical connection of the reconfiguration electrical chip assembly and the substrate assembly, and the metal heat sink material is in contact with the reconfiguration electrical chip assembly and is located in the projection area of the transimpedance amplifier and the driver.

The CPO optical module packaging structure provided by the utility model is formed by packaging the shell component, the substrate component, the reconstruction electric chip component, the optical fiber array component and the heat conduction component, and has the advantages of high integration level, low loss and good heat dissipation performance.

Drawings

The accompanying drawings are included to provide a further understanding of the utility model, and are incorporated in and constitute a part of this specification, illustrate the utility model and together with the description serve to explain, without limitation, the utility model.

Fig. 1 is a cross-sectional view of a CPO optical module package structure provided by the present utility model.

Fig. 2 is a flowchart of a method for manufacturing a CPO optical module package structure provided by the present utility model.

Fig. 3 is a schematic structural diagram of forming a first light-emitting layer according to the present utility model.

Fig. 4 is a schematic structural diagram of the bonded photodetector, transimpedance amplifier, and driver according to the present utility model.

Fig. 5 is a schematic view of the structure of the injection molding material of fig. 4 after filling.

Fig. 6 is a schematic diagram of the thinned wafer structure of fig. 5 according to the present utility model.

Fig. 7 is a schematic diagram of a structure of the wafer structure of fig. 6 after photo-induced bonding and flipping.

Fig. 8 is a schematic structural diagram of the present utility model after spin-coating the first PI glue on the basis of the structure of fig. 7.

Fig. 9 is a schematic structural view of forming a second light-emitting layer according to the present utility model.

Fig. 10 is a schematic structural diagram of the spin-coated negative photoresist according to the present utility model.

Fig. 11 is a schematic structural view of an inverted trapezoidal window formed after development according to the present utility model.

Fig. 12 is a schematic structural diagram of the evaporated seed layer according to the present utility model.

Fig. 13 is a schematic structural diagram of a copper pillar structure formed by electroplating according to the present utility model.

Fig. 14 is a schematic structural diagram of the present utility model after removing the negative photoresist.

Fig. 15 is a schematic structural diagram of the temporary co-sealed chip and the reconstituted electric chip support structure after being adhered.

Fig. 16 is a schematic view of the structure of the material for secondary injection according to the present utility model.

Fig. 17 is a schematic structural diagram of the thinned structure according to the present utility model.

Fig. 18 is a schematic structural diagram of the spin-coated second PI glue and the first redistribution layer after preparation.

Fig. 19 is a schematic diagram of the structure of fig. 18 after photo-induced bonding.

Fig. 20 is a schematic structural diagram of the second redistribution layer after preparation according to the present utility model.

Fig. 21 is a schematic diagram of the wafer structure of fig. 20 after being flipped.

Fig. 22 is a schematic structural diagram of the optical chip assembly bonded to the reconstituted electrical chip assembly according to the present utility model.

Fig. 23 is a schematic structural view of a stepped PCB through hole and a PCB bump formed on a PCB board according to the present utility model.

Fig. 24 is a schematic structural diagram of filling a metal heat sink material in a stepped PCB through hole according to the present utility model.

Fig. 25 is a schematic diagram of the structure of fig. 22 bonded to a substrate assembly according to the present utility model.

Fig. 26 is a schematic structural diagram of the underfill according to the present utility model.

FIG. 27 is a schematic view of the assembled fiber array assembly according to the present utility model.

Fig. 28 is a schematic structural view of a housing assembly according to the present utility model.

Fig. 29 is a schematic view showing the assembly of the housing assembly, the heat conducting assembly and the structure of fig. 27 according to the present utility model.

Fig. 30 is a flow chart of the preparation of the reconstituted electrical chip assembly provided by the utility model.

Fig. 31 is a flow chart of bonding an optical chip assembly to the reconstituted electrical chip assembly based on a flip-chip process according to the present utility model.

Fig. 32 is a flowchart of a method for bonding a first bonding assembly to a substrate assembly according to the present utility model.

FIG. 33 is a flow chart of assembling a fiber array assembly according to the present utility model.

Detailed Description

It should be noted that, without conflict, the embodiments of the present utility model and features of the embodiments may be combined with each other. The utility model will be described in detail below with reference to the drawings in connection with embodiments.

In order that those skilled in the art will better understand the present utility model, a technical solution in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the utility model herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In this embodiment, there is provided a CPO optical module package structure, and fig. 1 is a cross-sectional view of the CPO optical module package structure provided in an embodiment of the present utility model, as shown in fig. 1, including:

a housing assembly 100 including oppositely disposed housing top and bottom portions 110, 120;

A substrate assembly 200 positioned above the housing bottom portion 120 and connected to the housing bottom portion 120;

A reconstituted electrical chip assembly 300 located on a side of the substrate assembly 200 facing away from the housing bottom portion 120 and in bonding connection with the substrate assembly 200, wherein the reconstituted electrical chip assembly 300 is formed by co-packaging at least a photodetector, a transimpedance amplifier, and a driver;

The optical chip assembly 400 is flipped on one side of the reconstituted electric chip assembly 300 away from the substrate assembly 200 and is electrically connected with at least a driver of the reconstituted electric chip assembly 300;

The optical fiber array assembly 500 is positioned at one side of the reconstruction electric chip assembly 300 away from the substrate assembly 200 and is respectively coupled with the photoelectric detector and the optical chip assembly 400;

A thermally conductive assembly 600 comprising at least a first thermally conductive pad 610 located between the reconstituted electrical chip assembly 300 and the housing top portion 110 and a second thermally conductive pad 620 located between the reconstituted electrical chip assembly 300 and the housing bottom portion 120;

the housing top portion 110 is located on a side of the reconstituted electrical chip assembly 300 facing away from the substrate assembly 200 and covers at least the optical chip assembly 400, the optical fiber array assembly 500, and the first thermally conductive pad 610.

In particular to a CPO optical module packaging structure, when the CPO optical module packaging structure specifically works, an optical fiber array assembly is connected with a photoelectric detector in a coupling way, input light reaches the photoelectric detector through the optical fiber array assembly to realize the light detection function, namely, an optical signal is converted into an electric signal, and in addition, the driver can drive the optical chip assembly to work through the electric connection of the driver and the optical chip assembly, so that the optical signal is emitted out through the optical fiber array assembly. In the embodiment of the utility model, the optical fiber array component and the reconstruction electric chip component are of a stacked structure which is arranged up and down, and the optical chip component is arranged on the reconstruction electric chip component in a flip-chip manner, so that the normal operation of the CPO optical module packaging structure can be met, the integration level of a unit area can be improved, and the packaging size can be reduced.

Therefore, in the embodiment of the utility model, the photoelectric detector, the transimpedance amplifier and the driver are packaged together to form the reconstructed electric chip assembly, so that the integration level of a unit area is effectively improved, and in addition, the packaging size can be further reduced and the integration level of a packaging structure is improved by reversely mounting the optical chip assembly on the reconstructed electric chip assembly. In addition, in the embodiment of the utility model, the heat conduction assembly is arranged, so that the packaging structure is provided with two heat dissipation paths at the top and the bottom, and the overall heat dissipation capacity of the packaging structure is improved.

Therefore, the CPO optical module packaging structure provided by the utility model is formed by packaging a shell component, a substrate component, a reconstruction electric chip component, an optical fiber array component and a heat conduction component, and the integrated level of unit area is improved because the reconstruction electric chip component is formed by a co-packaged chip of a photoelectric detector, a transimpedance amplifier and a driver, and the packaging size can be effectively reduced through the flip-chip arrangement of the optical chip component, and in addition, the heat conduction component can effectively improve the heat dissipation capability.

In an embodiment of the present utility model, as shown in fig. 1, the reconstituted electrical chip assembly 300 includes:

The chip layer 310 comprises an injection molding material body 311, an electrical introduction unit embedded in the injection molding material body 311, and a photoelectric detector 313, a transimpedance amplifier 314 and a driver 315 which are arranged at intervals;

The first rewiring layer 320 is connected to the upper surface of the chip layer 310, and is capable of respectively realizing electrical connection between the photodetector 313 and the electrical lead-in unit, between the driver 315 and the electrical lead-in unit, and between the photodetector 313 and the transimpedance amplifier 314, wherein the upper surface of the chip layer 310 is a side of the reconstituted electric chip assembly 300 facing away from the substrate assembly 200;

the first electrical connection 330 is located on the surface of the first redistribution layer 320 facing away from the chip layer 310, and at least electrically connects the driver 315 and the optical chip assembly 400;

The second redistribution layer 340 is connected to the lower surface of the chip layer 310 and is electrically connected to the electrical lead-in unit of the chip layer 310, wherein the lower surface of the chip layer 310 is the side of the reconstituted electrical chip assembly 300 facing the substrate assembly 200;

The second electrical connection 350 is located on the surface of the second redistribution layer 340 facing away from the chip layer 310, and at least electrically connects the reconstituted electrical chip assembly 300 and the substrate assembly 200.

Specifically, the electrical introducing units embedded in the injection molding material body 311 in the chip layer 310 are exemplified by the first electrical introducing unit 312a and the second electrical introducing unit 312b shown in fig. 1, and the photodetector 313, the transimpedance amplifier 314 and the driver 315 shown in fig. 1 are disposed between and spaced apart from the first electrical introducing unit 312a and the second electrical introducing unit 312 b.

When the first redistribution layer 320 is electrically connected, taking the structure shown in fig. 1 as an example, the first redistribution layer 320 can electrically connect the first electrical lead-in unit 312a with the photodetector 313, electrically connect the photodetector 313 with the transimpedance amplifier 314, electrically lead-in/out the driver 315, and electrically connect the driver 315 with the second electrical lead-in unit 312 b.

Taking the structure shown in fig. 1 as an example, the first electrical connection 330 can be electrically connected to the first redistribution layer 320 corresponding to the driver 315 and the second electrical lead-in unit 312b, respectively. Specifically, in the embodiment of the present utility model, the first electrical connection 330 may be a UBM Pad.

Taking the structure shown in fig. 1 as an example, the second redistribution layer 340 may specifically include a first portion 341 and a second portion 342, where the first portion 341 is electrically connected to the first electrical introducing unit 312a, and the second portion 342 is electrically connected to the second electrical introducing unit 312 b.

Taking the structure shown in fig. 1 as an example, the second electrical connection member 350 can be electrically connected to the first portion 341 and the second portion 342, respectively. Specifically, in the embodiment of the present utility model, the second electrical connection 350 may be a UBM Pad.

It should be noted that, in the embodiment of the present utility model, the first electrical introducing unit 312a and the second electrical introducing unit 312b may be specifically copper pillar structures.

In the embodiment of the utility model, the photoelectric detector 313, the transimpedance amplifier 314 and the driver 315 are integrated on the chip layer 310, so that the integration level of the reconstituted electric chip assembly is effectively improved, in addition, the first rerouting layer is arranged on the chip layer 310 to realize the electrical connection of the chip layer 310, the first electrical connector 330 is arranged to realize the electrical connection of the first rerouting layer 320 and the chip layer 310, the second rerouting layer 340 and the second electrical connector 350 are arranged to realize the electrical connection of the chip layer 310 and the substrate assembly 200, and the like, and the connecting lines of the electronic devices of the chip layer are arranged in the metal layer at the top or the bottom of the chip due to the arrangement of the first rerouting layer and the second rerouting layer, so that the size and the space are greatly saved, in addition, the high-density interconnection structure can be realized, the delay and the power consumption of signal transmission are reduced, and the working performance of the circuit is improved.

In the embodiment of the utility model, as shown in fig. 1, the optical chip assembly 400 includes a chip body 410, and an end-face coupler 420 and a third electrical connector 430 formed on the chip body 410, where the third electrical connector 430 contacts with the first electrical connector 330 to electrically connect the driver 315 with the optical chip assembly 400.

It should be understood that the optical chip assembly 400 can dispose the end-face coupler 420 on the chip body 410, and the end-face coupler 420 can electrically connect with the reconstituted electrical chip assembly 300 through the third electrical connector 430 and the first electrical connector 330. Since the optical chip assembly 400 is electrically connected to the reconstituted electrical chip assembly 300 by a flip-chip process, the integration level can be further improved and the device size can be reduced.

In the embodiment of the utility model, the third electrical connection member 430 may be a bump structure formed on the chip body 410.

In an embodiment of the present utility model, the fiber array assembly 500 includes a first fiber array assembly portion 510 and a second fiber array assembly portion 520,

The first optical fiber array component part 510 is positioned on the surface of the reconstructed electrical chip component 300 facing away from the substrate component 200, the end surface between the first optical fiber array component part 510 and the photodetector 313 is coupled, the coupling area between the first optical fiber array component part 510 and the photodetector 313 is filled with transparent dielectric material, and no metal connecting wire of a first rewiring layer exists in the coupling area;

the second fiber array assembly portion 520 is located on a side of the optical chip assembly 400 facing away from the first thermally conductive pad 610;

The first optical fiber 530 is used as an incident optical fiber, and transmits the received optical signal to the first optical fiber array component part 510, the first optical fiber array component part 510 changes the propagation direction of the received optical signal through the curved path in fig. 1, so that the optical signal propagates downward, the first optical fiber array component part 510 is coupled with the photodetector 400, and then the received optical signal propagates to the photodetector 313 through the first optical fiber array component part 510, and the optical chip component 400 is coupled with the second optical fiber array component part 520, so that the optical signal in the optical chip component 400 can propagate to the second optical fiber array component part 520, then propagates to the second optical fiber 540, and outputs the optical signal through the second optical fiber 540.

Specifically, in the embodiment of the present utility model, as shown in fig. 1, after the first optical fiber 530 is horizontally connected to the first optical fiber array component part 510 as an incident optical fiber, the incident optical fiber is converted into an optical signal transmitted vertically downward through a bend in the first optical fiber array component part 510, and the optical signal is transmitted to the photodetector 313 based on the coupling of the first optical fiber array component part 510 with the end face of the photodetector 313, and then the photodetector performs photoelectric conversion to obtain an electrical signal. In order to achieve the coupling function between the photodetector 313 and the first fiber array assembly portion 510, a transparent dielectric material is filled in the first dielectric layer of the coupling region between the photodetector 313 and the first fiber array assembly portion 510, and the metal connection lines of the first redistribution layer are not disposed in the coupling region. In addition, the driver is electrically connected with the optical chip assembly to drive the optical chip assembly, and the optical chip assembly is coupled with the second optical fiber array assembly part 520 through the second optical fiber 540, and the second optical fiber 540 can be used as an emergent optical fiber to emit the optical signal output by the optical chip assembly.

Therefore, the first optical fiber array component part and the reconstruction optical chip component are arranged in a vertically stacked mode, the first optical fiber array component part is connected with the photoelectric detector in the reconstruction optical chip component in a coupling mode, the optical signals received by the first optical fiber array component part from the first optical fibers are converted into optical signals transmitted towards the photoelectric detector after passing through the bent path arranged in the first optical fiber array component part, transparent medium materials are filled in the coupling area (comprising the first medium layer and the part between the photoelectric detector and the first optical fiber array component part) of the photoelectric detector and the first optical fiber array component part, the function of the photoelectric detector in the CPO optical module packaging structure is achieved, the integration level of a unit area can be effectively improved, and in addition, the packaging size can be further reduced and the integration level of the CPO optical module packaging structure can be improved by reversely mounting the optical chip component on the reconstruction optical chip component.

As shown in fig. 1, the first fiber array assembly portion 510 is located on the surface of the reconstituted electrical chip assembly facing away from the substrate assembly and above the photodetector 313 in the reconstituted electrical chip assembly 300. Specifically, whether the first fiber array component part 510 is located above or directly above the photodetector 313, or how much the positional deviation is, is determined according to the positions of the light outlet of the first fiber array component part 510 and the light inlet of the photodetector 313, so as to ensure that the light outlet of the first fiber array component part 510 is coupled with the light inlet of the photodetector 313.

In the embodiment of the present utility model, the second fiber array assembly portion 520 is located on the outer side of the optical chip assembly, and the first thermal pad 610 is located on the inner side of the optical chip assembly, that is, the second fiber array assembly portion 520 is located on the side of the optical chip assembly 400 facing away from the first thermal pad 610.

Specifically, the fiber array assembly 500 further includes a glass cover plate 550, the glass cover plate 550 being positioned between the housing top portion 110 and the reconstituted electrical chip assembly 300, the glass cover plate 550 covering at least the second fiber array assembly portion 520 and a portion of the optical chip assembly 400. As shown in fig. 1, the glass cover plate 550 is located directly above the second optical fiber array assembly portion 520, and can cover not only the second optical fiber array assembly portion 520 but also a part of the optical chip assembly 400.

In the embodiment of the present utility model, as shown in fig. 1, the substrate assembly 200 includes a PCB 210 and a fourth electrical connector 220 formed on a surface of the PCB 210;

A step-shaped PCB through hole 211 is formed on the PCB 210, and a metal heat sink material is filled in the step-shaped PCB through hole 211;

The fourth electrical connection 220 is in contact with the second electrical connection 350 of the reconstituted electrical chip assembly 300 to electrically connect the reconstituted electrical chip assembly with the substrate assembly, and the metal heat sink material is in contact with the reconstituted electrical chip assembly 300 and is located in the projection area of the transimpedance amplifier and the driver.

It should be understood that in the embodiment of the present utility model, the substrate assembly 200 includes a PCB board 210 and a fourth electrical connector 220, the fourth electrical connector 220 is used to electrically connect the substrate assembly 200 and the reconstituted electric chip assembly 300, and a stepped PCB through hole 211 is formed on the PCB board 210, and a metal heat sink material is filled in the PCB through hole 211, so that the heat dissipation capability of the substrate assembly can be effectively improved. Specifically, as an alternative embodiment, the projection of the stepped PCB through hole 211 near the stepped PCB through hole of the reconstituted electrical chip assembly 300 at least partially coincides with the projection of the transimpedance amplifier and the driver on the surface.

In the embodiment of the present utility model, the fourth electrical connection 220 may be a PCB bump.

Specifically, the PCB through hole 211 formed in the middle of the PCB board may be filled with a tungsten copper heat sink material, and the second heat conductive pad 620 corresponds to the right lower side of the PCB through hole 211, and the heat generated by the reconstructed electrical chip assembly 300 is transferred to the second heat conductive pad 620 through the heat sink material filled in the PCB through hole 211, so that the heat dissipation capability of the CPO optical module package structure can be effectively improved.

In addition, in order to fix the case assembly 100, screw holes may be provided on the case bottom part 120, and screw holes may be provided on the PCB board 210 at positions corresponding to the case bottom part 120, and the case bottom part 120 is connected to the substrate assembly 200 by fastening screws.

In summary, the CPO optical module packaging structure provided by the utility model not only can effectively improve the integration level, but also can reduce the loss and improve the heat dissipation capacity of the CPO optical module packaging structure.

As another aspect of the present utility model, there is provided a method for preparing a CPO optical module package structure, for preparing the CPO optical module package structure described above, where, as shown in fig. 2, the preparation method includes:

S100, preparing a reconstructed electric chip assembly based on a fan-out process, wherein the reconstructed electric chip assembly is formed by packaging at least a photoelectric detector, a transimpedance amplifier and a driver together;

In the embodiment of the utility model, the reconstructed electric chip assembly is prepared based on the fan-out process, and the packaging structure with low power loss can be formed by utilizing the high-density wiring manufacturing process.

Specifically, a reconstituted electrical chip assembly is prepared based on a fan-out process, as shown in fig. 30, comprising:

S110, providing a first temporary substrate, and pasting a photoelectric detector, a transimpedance amplifier and a driver on the first temporary substrate to obtain a temporary co-packaged chip;

As shown in fig. 3, a first temporary substrate 1 is provided, and a photo-releasing paste is spin-coated on the first temporary substrate 1 to form a first photo-releasing layer 2.

As shown in fig. 4, the photodetector 313, the transimpedance amplifier 314, and the driver 315 are pasted in a face-down (face-down patch) manner.

As shown in fig. 5, the surface of the wafer structure shown in fig. 4 is filled with an injection molding material 6 once by an injection molding process to realize plastic packaging, cover the space on the back surface and the periphery of the chip, and complete thermal curing.

As shown in fig. 6, the wafer structure of fig. 5 after injection molding is thinned until all of the substrate material on the back side of the die is exposed, i.e., until the substrate material on the back side of the photodetector 313, transimpedance amplifier 314, and driver 315 is exposed.

As shown in fig. 7, the co-encapsulated wafer is photo-debonded using UV light and the photo-debonded structure is flipped.

As shown in fig. 8, the temporary co-packaged chip 8 is obtained by spin-coating the first PI glue 7 on the surface of the flipped wafer (i.e., the PAD side of the photodetector 313, the transimpedance amplifier 314, and the driver 315) and completing the curing.

S120, providing a second temporary substrate, and preparing an electrical lead-in unit on the second temporary substrate to obtain a reconstructed electrical chip supporting structure;

In an embodiment of the utility model, the reconstituted electrical chip support structure is obtained by preparing an electrical lead-in unit on the second temporary substrate base plate.

Specifically, as shown in fig. 9, a second temporary substrate 3 is provided, and a photo-releasing paste is spin-coated on the second temporary substrate 3 to form a second photo-releasing layer 9.

As shown in fig. 10, two layers of negative photoresist 10 are spin-coated on the second photo-releasing layer 9.

As shown in fig. 11, the negative photoresist is notched with a developer solution into an inverted trapezoid notch 11.

As shown in fig. 12, a thin Ti/Cu layer is deposited as a seed layer 12 in the inverted trapezoidal notch 11.

As shown in fig. 13, a copper pillar structure is formed on the seed layer 12 in fig. 12 by performing an electroplating process to form electrical lead-in units (a first electrical lead-in unit 312a and a second electrical lead-in unit 312 b).

As shown in fig. 14, the reconstituted electrical chip support structure 14 is obtained after removing part or all of the two layers of negative photoresist in the wafer of fig. 13. Whether the two layers of negative photoresist are completely removed or a part of the negative photoresist is removed can be operated according to actual requirements, and the scheme is not particularly limited.

S130, adhering the temporary co-packaged chip on the reconstructed electrical chip supporting structure, so that the photoelectric detector, the transimpedance amplifier, the driver and the electrical lead-in unit are positioned on the reconstructed electrical chip supporting structure together;

In an embodiment of the utility model, the temporary co-packaged chip 8 shown in fig. 8 is glued to the reconstituted electrical chip support structure 14.

Specifically, in the embodiment of the present utility model, the electrical introducing units are exemplified by the first electrical introducing unit 312a and the second electrical introducing unit 312b shown in fig. 1, and the photodetector 313, the transimpedance amplifier 314 and the driver 315 shown in fig. 1 are disposed between and spaced apart from the first electrical introducing unit 312a and the second electrical introducing unit 312 b. Specifically, the first electrical introducing unit 312a and the second electrical introducing unit 312b may be specifically copper pillar structures. As shown in fig. 15, the temporary co-packaged chip 8 is attached to the area between the copper pillar structures of the reconstituted electrical chip support structure 14 by means of face-up.

As shown in fig. 16, the bonded wafer structure is filled with the overmolding material 15.

S140, performing injection molding and thinning on a wafer structure formed by adhering the temporary co-sealed chip and the reconstructed electric chip supporting structure to form a chip layer;

As shown in fig. 17, the wafer structure filled with the secondary injection molding material 15 is thinned until PI glue on the surfaces of the electrical property introducing unit and the temporary co-sealing chip 8 are exposed at the same time, thereby obtaining a chip layer.

S150, sequentially forming a first rewiring layer and a first electric connection piece on the upper surface of the chip layer, wherein the first rewiring layer can be used for realizing electric connection among the photoelectric detector, the electric introduction unit, the driver, the electric introduction unit and the transimpedance amplifier respectively, the upper surface of the chip layer is one side of the temporary co-sealed chip, which is away from the reconstructed electric chip supporting structure, the first electric connection piece is positioned on the surface of the first rewiring layer, which is away from the chip layer, and at least the electric connection between the driver and the optical chip assembly is realized;

As shown in fig. 18, after the second PI glue 18 is spin-coated on the surface of the thinned wafer structure shown in fig. 17, a first redistribution layer 320 is prepared, and contact holes 16 are formed on the first electrical property introducing unit 312a and the second electrical property introducing unit 312b and electrically connected to the first redistribution layer 320. In addition, a first electrical connection 330 is formed on the first redistribution layer 320, where the first electrical connection 330 is located at a position of the first redistribution layer away from the driver side, and is located at a position of the first redistribution layer away from the second electrical lead-in unit 312 b.

The second PI glue 18 shown in fig. 18 can cover the first redistribution layer and the chip layer, and in the actual process, the coverage area of the second PI glue 18 can be set according to the actual requirement, which is not specifically limited in this scheme.

As shown in fig. 19, the structure shown in fig. 18 is subjected to photoinduced debonding, i.e., the second photoinduced release layer 9 and the second temporary substrate base plate 3 on the back surface of the chip layer are removed.

S160, sequentially forming a second redistribution layer and a second electrical connection piece on the lower surface of the chip layer, wherein the second redistribution layer is electrically connected with the electrical introduction unit, the second electrical connection piece is positioned on the surface, deviating from the chip layer, of the second redistribution layer, and at least the electrical connection between the reconfiguration electrical chip assembly and the substrate assembly is realized.

As shown in fig. 20, the second photo-release layer 9 is removed from the chip layer, and the third PI glue 20 is spin-coated on the surface of the second temporary substrate 3 (i.e., the lower surface of the chip layer), and a second redistribution layer 340 and a second electrical connector 350 are prepared, wherein the second redistribution layer 340 includes a first portion 341 formed at a position of the first electrical lead-in unit 312a therein, and a second portion 342 formed at a position of the second electrical lead-in unit 312b, and the second electrical connector 350 is formed on both the first portion 341 and the second portion 342, respectively.

The third PI glue 20 spin-coated on the lower surface of the chip layer can cover the second redistribution layer 340 and the second electrical connection 350.

S200, bonding the optical chip assembly and the reconstruction electric chip assembly based on a flip-chip process to obtain a first bonding assembly;

In the embodiment of the present utility model, as shown in fig. 21, the wafer structure of fig. 20 is flipped.

Specifically, bonding an optical chip assembly to the reconstituted electrical chip assembly based on a flip-chip process, as shown in fig. 31, includes:

S210, providing an optical chip assembly, wherein the optical chip assembly comprises a chip body, an end face coupler and a third electric connecting piece, wherein the end face coupler is formed on the chip body;

As shown in fig. 22, the optical chip assembly 400 includes a chip body 410, and an end-face coupler 420 and a third electrical connector 430 formed on the chip body 410.

And S220, bonding the optical chip assembly with the reconfiguration electric chip assembly based on a flip-chip process, wherein the third electric connecting piece is contacted with the first electric connecting piece of the reconfiguration electric chip assembly so as to realize electric connection between the driver and the optical chip assembly.

As shown in fig. 22, the optical chip assembly 400 is bonded on the reconstituted electric chip assembly 300 based on the flip-chip process, wherein the third electrical connection member 430 is in contact with the first electrical connection member 330 to achieve electrical connection.

S300, bonding the first bonding assembly on the substrate assembly to obtain a second bonding assembly;

In an embodiment of the present utility model, a substrate assembly is provided, and the first bonding assembly is bonded to the substrate assembly.

Specifically, bonding the first bonding assembly to the substrate assembly, as shown in fig. 32, includes:

S310, providing a PCB;

s320, forming a stepped PCB through hole on the PCB, and forming a fourth electrical connection piece on the surface of the PCB;

As shown in fig. 23, a stepped PCB through hole 211 is formed on the PCB 210, and a ball mounting process is performed at a PCB PAD230 on the surface of the PCB 210, so as to obtain a fourth electrical connector 220. Meanwhile, in order to achieve connection fixation with the housing assembly 100, a plurality of first screw holes 212 are also formed on the PCB board 210.

S330, filling a metal heat sink material 240 in the stepped PCB through hole to form a substrate assembly;

As shown in fig. 24, a metal heat sink material is filled in the stepped PCB through hole 211, specifically, in the embodiment of the present utility model, a tungsten copper heat sink material is filled, and the adhesion of the tungsten copper heat sink material to the PCB board 210 is completed.

And S340, bonding the first bonding assembly on the substrate assembly 230, wherein the fourth electrical connection piece is in contact with the second electrical connection piece of the reconstructed electrical chip assembly to realize the electrical connection between the reconstructed electrical chip assembly and the substrate assembly, and the metal heat sink material is in contact with the reconstructed electrical chip assembly and is positioned in the projection area of the transimpedance amplifier and the driver.

As shown in fig. 25, the first bonding assembly obtained in fig. 20 is bonded on the substrate assembly of fig. 24, and the fourth electrical connection member 220 is in contact with the second electrical connection member 350 to electrically connect the first bonding assembly and the substrate assembly. The metal heat sink material of the substrate assembly is contacted with the reconstruction electric chip assembly to realize the heat dissipation function of the CPO optical module packaging assembly.

As shown in fig. 26, the gap between the substrate assembly and the first bonding assembly is filled with a first underfill 33, and the gap between the optical chip assembly and the reconstituted electrical chip assembly is filled with a second underfill 32, and thermal curing is completed.

S400, assembling an optical fiber array assembly on one side of the first bonding assembly, which is away from the substrate assembly, so that the optical fiber array assembly is respectively coupled with the photoelectric detector and the optical chip assembly;

In an embodiment of the present utility model, the assembly of the fiber array assembly is performed on the basis of the structure shown in fig. 26.

Specifically, the optical fiber array assembly is assembled on the side of the first bonding assembly facing away from the substrate assembly, as shown in fig. 33, and includes:

S410, assembling a first optical fiber array component part on the surface of the first bonding component, which is away from the substrate component, wherein the first optical fiber array component part is coupled with the end surface between the photodetectors, a coupling area between the first optical fiber array component part and the photodetectors is filled with a transparent dielectric material, and a metal connecting wire of a first rewiring layer is not arranged in the coupling area;

s420, assembling a second optical fiber array assembly part on the side surface of the optical chip assembly, which faces away from the first optical fiber array assembly part;

As shown in fig. 27, the first optical fiber array assembly portion 510 on the top surface of the photodetector is coupled and stuck in a corresponding position by active coupling, and pre-curing is completed by UV glue, then the first optical fiber 530 which is horizontally emitted is coupled with the end surface of the optical chip assembly, and the glass carrier plate 550 is glued and stuck on the top surface of the optical chip assembly 400 and the top surface of the second optical fiber array assembly portion 520, pre-curing is completed by UV glue, and the pre-cured optical module is sent into a high temperature oven, so as to complete final glue curing.

S500, the second bonding assembly, the shell assembly and the heat conduction assembly are assembled together after the optical fiber array assembly is assembled, and the CPO optical module packaging structure is obtained.

As shown in fig. 28, which is a schematic structural view of the housing assembly 100, specifically includes a housing top portion 110 and a housing bottom portion 120 disposed opposite to each other, and as an alternative embodiment, a plurality of second threaded holes 40 are formed in the housing bottom portion 120.

As shown in fig. 29, a second heat conducting spacer 620 is adhered to the bottom part 120 of the housing, and heat conducting silicone grease is smeared on the surface of the second heat conducting spacer 620 facing away from the bottom part 120 of the housing, and the structure shown in fig. 27 is assembled with the bottom part 120 of the housing, and fastening screws 39 can be used to fasten the structure through first threaded holes on the PCB board and second threaded holes on the bottom part 120 of the housing, so as to achieve the fitting and fixing of the PCB board and the bottom part of the housing.

And pasting a first heat conduction gasket 610 on the top of the area, which is positioned on the transimpedance amplifier and the driver, of the upper surface of the chip layer, and assembling a top part 110 of the shell to complete the packaging of the CPO optical module, so as to obtain the CPO optical module packaging structure.

In summary, the preparation method of the CPO optical module packaging structure provided by the utility model obtains the reconstructed electric chip assembly through a fan-out process and a rewiring process, and obtains the optical chip assembly through a flip-chip process, thereby improving the integration level of the reconstructed electric chip assembly and the optical chip assembly, reducing the device size, arranging heat conducting gaskets on the upper surface and the lower surface of a chip layer, and filling a metal heat sink material on a substrate assembly to communicate the chip with the second heat conducting gasket so as to improve the heat dissipation capacity of the substrate, and further effectively improving the heat dissipation capacity of the whole module. Therefore, the CPO optical module packaging structure obtained by the preparation method provided by the utility model effectively improves the integration level and the heat dissipation performance of the CPO optical module packaging structure.

It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present utility model, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the utility model, and are also considered to be within the scope of the utility model.

Claims

1. A CPO optical module package structure, comprising:

2. The CPO optical module package as claimed in claim 1, wherein said reconstituted electrical chip assembly comprises:

3. The CPO optical module package as claimed in claim 2, wherein the optical chip assembly includes a chip body, and an end-face coupler and a third electrical connector formed on the chip body, the third electrical connector being in contact with the first electrical connector to electrically connect the driver and the optical chip assembly.

4. The CPO optical module package as claimed in claim 1, wherein said fiber array assembly includes a first fiber array assembly portion and a second fiber array assembly portion,

5. The CPO optical module package as claimed in claim 1, wherein said substrate assembly comprises a PCB board and a fourth electrical connection formed on a surface of said PCB board;