CN222146206U

CN222146206U - Packaging device

Info

Publication number: CN222146206U
Application number: CN202420535661.3U
Authority: CN
Inventors: 田兴国; 李志成
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2024-03-19
Filing date: 2024-03-19
Publication date: 2024-12-10
Anticipated expiration: 2034-03-19

Abstract

The application provides a packaging device which comprises a first packaging body, a conductive column and a functional layer structure, wherein the first packaging body comprises a substrate, the conductive column is arranged on the substrate and is provided with a concave part, the concave part is recessed from the upper surface of the conductive column towards the direction of the substrate, the functional layer structure is arranged on the substrate, and the functional layer structure at least covers the side surface of the conductive column part. The concave part can accommodate part of the solder balls, so that the adjacent solder balls are effectively prevented from being connected together under the action of high-temperature reflow soldering and pressure, and bridging of the adjacent solder balls is not easy to occur.

Description

Packaging device

Technical Field

The application relates to the technical field of semiconductor packaging, in particular to a packaging device.

Background

Referring to fig. 1, fig. 1 is a schematic diagram of a packaging apparatus for a product at present. As shown in fig. 1, in PoP (Package on Package ) technology, solder balls 03 are often used as electrical connectors for connecting the upper package body 01 and the lower package body 02, and the amount and distribution of the solder balls 03 may affect whether bridging is at risk, and when the solder balls 03 are subjected to high temperature reflow and pressure, adjacent solder balls 03 may be connected together to cause bridging.

Disclosure of utility model

It is an object of the present application to provide a packaging device with reduced risk of bridging of solder balls thereon.

The application provides a packaging device, which comprises a first packaging body, wherein the first packaging body comprises:

A substrate;

The conductive column is arranged on the substrate and is provided with a concave part, and the concave part is recessed from the upper surface of the conductive column towards the direction of the substrate;

and the functional layer structure is arranged on the substrate and at least coats the side surface of the conductive column part.

As described above, in order to solve the technical problem that solder balls arranged on adjacent conductive columns in a PoP structure are easy to bridge, the application provides a packaging device, wherein a concave portion is designed on the upper surface of a conductive column to form a concave conductive column structure, so that the concave portion can be used for accommodating the solder balls, the solder balls on the adjacent conductive columns are not easy to bridge, and the bridging risk is reduced.

In some alternative embodiments, the first package body and the second package body are connected, wherein the first package body comprises a substrate, a conductive post and a functional layer structure, the conductive post is arranged on the substrate, the upper surface of the conductive post is provided with a concave part, the concave part is concave from the upper surface of the conductive post towards the direction of the substrate, when the first package body and the second package body are connected through solder balls, the concave part can accommodate part of the solder balls, so that adjacent solder balls are effectively prevented from being connected together under the action of high-temperature reflow soldering and pressure, bridging of the adjacent solder balls is not easy to occur, the functional layer structure is arranged on the substrate and at least covers part of the side surface of the conductive post, or the functional layer structure is arranged on the substrate and at least covers all of the side surface of the conductive post, and the adjacent conductive post and the surrounding circuit structure thereof are effectively protected through the functional layer structure.

In some alternative embodiments, the conductive posts are configured to connect with an electrical connector, and the recesses are configured to receive portions of the electrical connector.

In some alternative embodiments, the packaging structure further comprises a second packaging body arranged on the first packaging body, and the second packaging body is electrically connected with the first packaging body through the electric connector.

In some alternative embodiments, the functional layer structure includes an insulating layer or a mold seal layer.

In some alternative embodiments, the functional layer structure includes an insulating layer and a mold seal layer;

The insulating layer is arranged on the substrate, the insulating layer covers part of the side surface of the conductive column, the mold sealing layer is arranged on one side of the insulating layer, which is away from the substrate, and the upper surface of the mold sealing layer is flush with the upper surface of the conductive column.

In some alternative embodiments, the insulating layer and the mold seal layer are the same thickness.

In some alternative embodiments, the thickness of the insulating layer and the mold seal layer are different.

In some alternative embodiments, the first package further includes a chip electrically connected to the substrate;

The orthographic projection of the chip on the substrate and the orthographic projection of the conductive column on the substrate are not overlapped.

In some alternative embodiments, the mold seal has an opening exposing an upper surface of the chip that is flush with the upper surface of the mold seal.

In some alternative embodiments, the chip is encapsulated by the mold seal, and the upper surface of the chip is not flush with the upper surface of the mold seal.

In some alternative embodiments, the first package further includes a filler layer disposed between the chip and the substrate.

In some alternative embodiments, the second package includes terminals disposed in one-to-one correspondence with the conductive posts, the terminals being at least partially located in the recesses of the conductive posts.

In some alternative embodiments, the conductive pillars further have a seed layer disposed between the conductive pillars and the contact surface of the functional layer structure.

In some alternative embodiments, the bottom surface of the recess is vertically lower than the interface of the insulating layer and the mold seal layer.

In some alternative embodiments, the recess includes first and second holes arranged in a vertical direction, the first and second holes having different pore sizes.

In some alternative embodiments, the first aperture has a larger aperture size than the second aperture in a direction in which the second package is directed toward the first package.

In some alternative embodiments, the first aperture and the second aperture form a stepped aperture.

In some alternative embodiments, the insulating layer has a second notch for receiving the conductive post, and the mold layer has a first notch exposing the conductive post, the first notch having an area smaller than an area of the second notch.

In some alternative embodiments, the insulating layer has a second notch for receiving the conductive post, and the mold layer has a first notch exposing the conductive post, the first notch having an area greater than an area of the second notch.

In some alternative embodiments, the first package further includes a pad on the substrate, the pad being electrically connected to the conductive post, an orthographic projection of the conductive post on the substrate covering an orthographic projection of the pad on the substrate.

In some alternative embodiments, the insulating layer has a second notch for receiving the conductive post, the mold seal has a first notch exposing the conductive post, the first notch has an area smaller than the second notch, and the first notch has an area smaller than the pad area.

In some alternative embodiments, the insulating layer has a second notch for receiving the conductive post, the mold seal has a first notch exposing the conductive post, the first notch has an area smaller than an area of the second notch, and the first notch has an area larger than the pad area.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:

FIG. 1 is a schematic view of a partial longitudinal cross-sectional structure of a prior art packaging apparatus;

FIG. 2 is a schematic view of a partial longitudinal cross-sectional structure of one embodiment 2a of a packaging apparatus according to the present application;

FIG. 3 is a schematic view of a partial longitudinal cross-sectional structure of one embodiment 3a of a packaging apparatus according to the present application;

FIG. 4 is a schematic view of a partial longitudinal cross-sectional structure of one embodiment 4a of a packaging apparatus according to the present application;

FIG. 5 is a schematic view of a partial longitudinal cross-sectional structure of one embodiment 5a of a packaging unit according to the present application;

FIGS. 6A-6E are schematic views of steps in the manufacture of one embodiment 2a of the encapsulation device of the present application;

FIG. 7 is a schematic view of a partial cross-sectional structure of a functional layer structure in one embodiment of a package device according to the present application;

FIG. 8 is a schematic view of a partial cross-sectional structure of an embodiment 8a of a packaging apparatus employing a solder mask bond pad defining process according to the present application;

FIG. 9 is a schematic view of a partial cross-sectional structure of an embodiment 9a of a packaging apparatus employing a solder mask bond pad defining process according to the present application;

FIG. 10 is a schematic view of a partial cross-sectional structure of one embodiment 10a of a package device employing a non-solder mask defined bonding pad process in accordance with the present application;

FIG. 11 is a schematic view of a partial cross-sectional structure of an embodiment 11a of a package device employing a non-solder mask limited pad process according to the present application;

FIG. 12 is an enlarged partial schematic view corresponding to FIG. 11 in accordance with the present application;

FIG. 13 is a schematic view of a partial longitudinal cross-sectional structure of one embodiment 13a of a packaging apparatus according to the present application;

FIG. 14 is a schematic view of a partial longitudinal cross-sectional configuration of one embodiment 14a of a packaging unit according to the present application;

FIG. 15 is a schematic view of a partial longitudinal cross-sectional configuration of one embodiment 15a of a packaging apparatus according to the present application;

FIG. 16 is a schematic view of a partial longitudinal cross-sectional configuration of one embodiment 16a of a packaging apparatus according to the present application;

FIGS. 17A-17E are schematic views of steps in the manufacture of one embodiment 13a of the encapsulation device of the present application;

fig. 18 is a schematic structural view of a terminal of one embodiment 18a of the packaging apparatus according to the present application;

Fig. 19 is a schematic structural view of a terminal of one embodiment 19a of the packaging apparatus according to the present application;

Fig. 20 is a schematic structural view of a terminal of one embodiment 20a of the packaging apparatus according to the present application.

Reference numerals/symbol description:

01-upper package, 02-lower package, 03-electrical connector;

10-first package, 11-substrate, 12-conductive post, 121-recess, 1211-first hole, 1212-second hole, 122-seed layer, 13-functional layer structure, 131-mold seal, 1311-first notch, 132-insulating layer, 1321-second notch, 14-chip, 15-fill layer, 16-pad, 20-second package, 21-terminal, 30-electrical connector.

Detailed Description

The following description of the embodiments of the present application will be given with reference to the accompanying drawings and examples, and it is easy for those skilled in the art to understand the technical problems and effects of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. In addition, for convenience of description, only a portion related to the related application is shown in the drawings.

It should be readily understood that the meanings of "on", "above" and "above" in the present application should be interpreted in the broadest sense so that "on" means not only "directly on" but also "on" including intermediate components or layers that exist therebetween.

Further, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "layer" as used herein refers to a portion of material that includes regions having a certain thickness. The layers may extend over the entire underlying or overlying structure, or may have a degree less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate 11 (substrate) may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or thereon. One layer may comprise multiple layers. For example, the semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

The term "substrate 11" as used herein refers to a material to which a subsequent material layer is added. The substrate 11 itself may be patterned. The material added to the top of the substrate 11 may be patterned or may remain unpatterned. In addition, the substrate 11 may include various semiconductor materials such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate 11 may be made of a non-conductive material, such as glass, plastic, or sapphire wafer, or the like. Further alternatively, the substrate 11 may have a semiconductor device or a circuit formed therein.

It should be noted that, the structures, proportions, sizes, etc. shown in the drawings are only used for being matched with those described in the specification for understanding and reading, and are not intended to limit the applicable limitation of the present application, so that the present application has no technical significance, and any modification of structures, changes in proportions or adjustment of sizes, without affecting the efficacy and achievement of the present application, should still fall within the scope covered by the technical content disclosed in the present application. Also, the terms "upper", "first", "second", and "a" and the like are used herein for descriptive purposes only and are not intended to limit the scope of the application for which the application may be practiced, but rather for relative changes or modifications without materially altering the technical context.

It should be further noted that, in the embodiment of the present application, the corresponding longitudinal section may be a section corresponding to a front view direction, the corresponding transverse section may be a section corresponding to a right view direction, and the corresponding horizontal section may be a section corresponding to an upper view direction.

In addition, the embodiments of the present application and the features in the embodiments may be combined with each other without collision. The application will be described in detail below with reference to the drawings in connection with embodiments.

Referring to fig. 2, fig. 2 is a schematic view of a partial longitudinal sectional structure of an embodiment 2a of a packaging apparatus according to the present application. As shown in fig. 2, a packaging device 2a according to the present application includes a first package body 10.

The first package 10 includes a substrate 11, a conductive pillar 12 and a functional layer structure 13, in which the conductive pillar 12 is disposed on the substrate 11, the conductive pillar 12 has a recess 121, the recess 121 is recessed from an upper surface of the conductive pillar 12 toward the substrate 11, the functional layer structure 13 is disposed on the substrate 11, and the functional layer structure 13 at least covers a side surface of a portion of the conductive pillar 12.

Here, the conductive posts 12 are configured to connect to the electrical connectors 30, e.g., the electrical connectors 30 are solder balls, the recesses 121 are configured to receive portions of the solder balls, the solder balls may also be solder balls, e.g., a portion of the solder balls may be received within the recesses 121.

According to the packaging device 2a of the application, the concave part 121 is designed on the upper surface of the conductive post 12 to form the notch conductive post structure, and the concave part 121 on the conductive post 12 can be used for accommodating the solder balls, so that the solder balls on the adjacent conductive posts 12 are not easy to bridge, and the bridging risk is reduced.

In some alternative embodiments, the packaging device 2a of the present application further includes a second package 20 disposed opposite the first package 12, the first package 10 and the second package 20 being connected by an electrical connection 30. The electrical connector 30 is disposed on the conductive post 12 and is partially received in the recess 121.

Here, when the first package body 10 and the second package body 20 are connected through the electrical connection member 30, the recess 121 may accommodate a portion of the electrical connection member 30, thereby effectively preventing the adjacent electrical connection members 30 from being connected together under the effect of high temperature reflow soldering and pressure, so that bridging of the adjacent electrical connection members 30 is not likely to occur, and the functional layer structure 13 is disposed on the substrate 11 and covers at least a portion of the side surface of the conductive pillar 12, or the functional layer structure 13 is disposed on the substrate 11 and covers at least all of the side surface of the conductive pillar 12, thereby effectively protecting the adjacent conductive pillar 12 and the circuit structure around thereof through the functional layer structure 13.

Of course, the functional layer structure 13 may be selected in various manners, for example, the functional layer structure 13 is an insulating layer 132, or the functional layer structure 13 is a mold seal layer 131, or the functional layer structure 13 includes an insulating layer 132 and a mold seal layer 131 that are stacked, where the insulating layer 132 is disposed on the substrate 11, the insulating layer 132 covers a portion of a side surface of the conductive post 12, the mold seal layer 131 is disposed on a side of the insulating layer 132 facing away from the substrate 11, and an upper surface of the mold seal layer 131 is flush with an upper surface of the conductive post 12.

In some alternative embodiments, the encapsulation device 2a of the present application may further comprise a chip 14 provided on the substrate 11. For example, the chip 14 may be electrically connected to the substrate 11 by bumps in a flip-chip manner.

For example, the chip 14 may be various types of bare chips 14 (i.e., die). The present application is not particularly limited thereto. For example, logic function chips 14, memory chips 14, communication chips 14, microprocessor chips 14, graphics chips 14, microelectromechanical systems (MEMS) chips 14, radio frequency chips 14, die or chip 14 scale packages, interposers, or combinations thereof, and the like may be included.

For example, the mold layer 131 may be made of various mold materials. By way of example, the molding material may include Epoxy (Epoxy resin), filler (Filler), catalyst (Pigment), release Agent (RELEASE AGENT), flame retardant (FLAME RETARDANT), coupling Agent (Coupling Agent), hardener (Harden), low stress absorber (Low Stress Absorber), adhesion promoter (Adhesion Promoter), ion scavenger (Ion TRAPPING AGENT), and the like.

In some specific embodiments, with continued reference to fig. 2, the functional layer structure 13 includes a mold seal layer 131 and an insulating layer 132, where the insulating layer 132 is disposed on the substrate 11, the insulating layer 132 encapsulates a portion of a side surface of the conductive pillar 12, where a portion of a side surface of the conductive pillar 12 that is not encapsulated by the insulating layer 132, and a portion of a side surface of the conductive pillar 12 that is not encapsulated by the insulating layer 132 is encapsulated by the mold seal layer 131, where an upper surface of the mold seal layer 131 is flush with an upper surface of the conductive pillar 12 to expose an upper surface of the conductive pillar 12, where the mold seal layer 131 has an opening exposing an upper surface of the chip 14, and where the upper surface of the chip 14 is flush with an upper surface of the mold seal layer 131, where the mold seal layer 131 exposes the chip 14 is convenient for heat transfer and dissipation of the chip 14, which helps to reduce a temperature of the chip 14, and improves a stability and reliability of the package provided by the embodiment of the application. For example, the insulating layer 132 and the mold seal layer 131 may have the same thickness, and the insulating layer 132 and the mold seal layer 131 may have different thicknesses. The orthographic projection of the chip 14 on the substrate 11 does not overlap with the orthographic projection of the conductive pillar 12 on the substrate 11.

Referring to fig. 3, fig. 3 is a schematic view of a partial longitudinal cross-section of an embodiment 3a of a packaging apparatus according to the present application, and fig. 3 is different from fig. 2 in that a chip 14 is completely embedded inside the chip 14 in fig. 3.

As shown in fig. 3, the functional layer structure 13 includes a mold seal layer 131 and an insulating layer 132, the insulating layer 132 is disposed on the substrate 11, the insulating layer 132 covers a part of the side surface of the conductive pillar 12, a part of the side surface of the conductive pillar 12 that is not covered by the insulating layer 132 is covered by the insulating layer 132, and a part of the side surface of the conductive pillar 12 that is not covered by the insulating layer 132 is covered by the mold seal layer 131, which of course, in order to ensure that the conductive pillar 12 contacts with the electrical connector 30, the upper surface of the mold seal layer 131 is flush with the upper surface of the conductive pillar 12, and the upper surface of the conductive pillar 12 is exposed, at this time, the chip 14 is covered by the mold seal layer 131, and the upper surface of the chip 14 is not flush with the upper surface of the mold seal layer 131. For example, the insulating layer 132 and the mold seal layer 131 may have the same thickness, and the insulating layer 132 and the mold seal layer 131 may have different thicknesses. The first package 10 further includes a chip 14 electrically connected to the substrate 11, and an orthographic projection of the chip 14 on the substrate 11 and an orthographic projection of the conductive pillar 12 on the substrate 11 do not overlap.

Referring to fig. 4, fig. 4 is a schematic view of a partial longitudinal cross-section structure of an embodiment 4a of a packaging device according to the present application, and fig. 4 is different from fig. 2 in that a filling layer 15 is disposed between a chip 14 and a substrate 11, the filling layer 15 may be, for example, underfill (unref ill), the chip 14 is firmly fixed on the substrate 11 through the filling layer 15, loosening or falling off is prevented during use, stability and reliability of electronic components are ensured, and the filling layer 15 also protects bumps between the chip 14 and the substrate 11.

The underfill is filled in the micro gap between the chip 14 and the substrate 11, so that the heat conduction performance is improved, the heat dissipation is facilitated, the working temperature of the chip 14 is reduced, and the service life of the chip 14 is prolonged. The underfill may form an insulating layer 132 between the chip 14 and the substrate 11 to prevent short circuits between electronic components and improve stability and safety of the circuit. The underfill may fill the minute voids, preventing moisture and dust from entering the gap between the chip 14 and the substrate 11, and protecting the electronic components from the external environment. The underfill may also provide cushioning and protection to reduce mechanical shock and vibration to which the chip 14 is subjected during shipping and use, and reduce the risk of damage. The first package 10 further includes a chip 14 electrically connected to the substrate 11, and an orthographic projection of the chip 14 on the substrate 11 and an orthographic projection of the conductive pillar 12 on the substrate 11 do not overlap.

Fig. 5 is a schematic view showing a partial longitudinal sectional structure of an embodiment 5a of the packaging device according to the present application, as shown in fig. 5. Compared with fig. 3, the difference of fig. 5 is that a filling layer 15 is disposed between the chip 14 and the substrate 11, and the filling layer 15 may be, for example, an underfill, and the chip 14 is firmly fixed on the substrate 11 by the underfill, so as to prevent loosening or falling off during use, and ensure stability and reliability of the electronic component. The underfill is filled in the micro gap between the chip 14 and the substrate 11, so that the heat conduction performance is improved, the heat dissipation is facilitated, the working temperature of the chip 14 is reduced, and the service life of the chip 14 is prolonged. The underfill may form an insulating layer 132 between the chip 14 and the substrate 11 to prevent short circuits between electronic components and improve stability and safety of the circuit. The underfill may fill the minute voids, preventing moisture and dust from entering the gap between the chip 14 and the substrate 11, and protecting the electronic components from the external environment. The underfill may also provide cushioning and protection to reduce mechanical shock and vibration to which the chip 14 is subjected during shipping and use, and reduce the risk of damage. The first package 10 further includes a chip 14 electrically connected to the substrate 11, and an orthographic projection of the chip 14 on the substrate 11 and an orthographic projection of the conductive pillar 12 on the substrate 11 do not overlap.

Fig. 6A-6E are schematic diagrams corresponding to the steps of manufacturing the structure of fig. 2, respectively. As shown in fig. 6A to 6E, the manufacturing steps of an embodiment 2a of the packaging device of the present application include:

As shown in fig. 6A, a substrate 11 is provided, a chip 14 is electrically connected to an upper surface of the substrate 11, then an insulating layer 132 and a molding layer 131 are sequentially formed, the structure shown in fig. 6B is formed by laser drilling the structure of fig. 6A, a conductive pillar 12 having a recess 121 is formed on an upper surface of the structure in fig. 6B by electroplating (e.g., track plating) in fig. 6C, the recess 121 is located at a position where a solder ball will be subsequently provided on the upper surface of the conductive pillar 12, a bottom surface of the recess 121 is lower than an interface between the insulating layer 132 and the molding layer 131 in a vertical height, a plating layer formed on the upper surface of the molding layer 131 in a track plating process is removed by continuing to expose the upper surface of the chip 14 to the molding layer 131 by a grinding process, and a second package 20 having a bottom provided with an electrical connector 30 is provided on the first package 10 by continuing to fig. 6E, wherein the electrical connector 30 is electrically connected to the corresponding conductive pillar 12 and the corresponding conductive pillar 121 is accommodated in the recess 12 by the electrical connector 30.

Fig. 7 is a schematic view of a partial cross-sectional structure of a functional layer structure 13 in an embodiment of a package device according to the present application, a conductive pillar 12 having a recess 121 is provided on a substrate 11, and the functional layer structure 13, the functional layer structure 13 including an insulating layer 132 and a mold layer 131 which are stacked. In fig. 7, the functional layer structure 13 is merely an example, and the functional layer structure 13 may be an insulating layer 132 and a mold layer 131 that are stacked, or the functional layer structure 13 may be the insulating layer 132, or the functional layer structure 13 may be the mold layer 131. When the functional layer structure 13 includes the insulating layer 132 and the mold seal layer 131 which are stacked, the thicknesses of the insulating layer 132 and the mold seal layer 131 may be the same or different.

Various structures are used in relation to the specific structure of the recess 121, including:

As shown in fig. 8, fig. 8 is a schematic view of a partial cross-sectional structure of an embodiment 8a of a package device according to the present application using SMD (Solder MASK DEFINED, solder mask process), wherein the insulating layer 132 has a second notch 1321 for accommodating the conductive post 12, the molding layer 131 has a first notch 1311 exposing the conductive post 12, and the area of the first notch 1311 is smaller than the area of the second notch 1321.

As shown in fig. 9, fig. 9 is a schematic partial cross-sectional structure of an embodiment 9a of the package device according to the present application using SMD (Solder MASK DEFINED, solder mask process), the insulating layer 132 has a second notch 1321 for accommodating the conductive post 12, the molding layer 131 has a first notch 1311 exposing the conductive post 12, and the area of the first notch 1311 is larger than the area of the second notch 1321. The recess 121 includes first and second holes 1211 and 1212 arranged in a vertical direction, the first and second holes 1211 and 1212 having different aperture sizes, the first hole 1211 having a larger aperture size than the second hole 1212 in a direction in which the second package 20 is directed toward the first package 10, and the first and second holes 1211 and 1212 forming a stepped hole.

As shown in fig. 10, fig. 10 is a schematic view of a partial cross-sectional structure of an embodiment 10a of a packaging apparatus according to the present application using NSMD (Non-Solder MASK DEFINED PAD DESIGN, non-solder-mask-limited pad design), wherein the first package body 10 further includes a pad 16 located on the substrate 11, the pad 16 is electrically connected to the conductive post 12, and an orthographic projection of the conductive post 12 on the substrate 11 covers an orthographic projection of the pad 16 on the substrate 11. The insulating layer 132 has a second notch 1321 for accommodating the conductive post 12, the mold layer 131 has a first notch 1311 exposing the conductive post 12, the area of the first notch 1311 is smaller than the area of the second notch 1321, and the area of the first notch 1311 is smaller than the area of the pad 16.

As shown in fig. 11, fig. 11 is a schematic view of a partial cross-sectional structure of an embodiment 11a of a packaging apparatus according to the present application using NSMD (Non-Solder MASK DEFINED PAD DESIGN, non-solder-mask-limited pad design), the first package body 10 further includes a pad 16 located on the substrate 11, the pad 16 is electrically connected to the conductive post 12, and an orthographic projection of the conductive post 12 on the substrate 11 covers an orthographic projection of the pad 16 on the substrate 11. The insulating layer 132 has a second notch 1321 for accommodating the conductive post 12, the mold layer 131 has a first notch 1311 exposing the conductive post 12, the area of the first notch 1311 is smaller than the area of the second notch 1321, and the area of the first notch 1311 is larger than the area of the pad 16.

In some alternative embodiments, as shown in fig. 12, the encapsulation device of the present application further includes a seed layer 122 (i.e., seed layer). The seed layer 122 is formed during the electroplating process, and a metal layer is deposited as the seed layer 122 prior to electroplating the conductive pillars 12, for example, by a Physical Vapor Deposition (PVD) process, so as to facilitate subsequent electroplating.

For ease of understanding the specific location of the seed layer 122 (i.e., seed layer), as shown in fig. 12, fig. 12 is a partially enlarged schematic view corresponding to fig. 11 according to the present application, the seed layer 122 is disposed between the contact surface of the conductive pillars 12 and the functional layer structure 13.

In some embodiments, referring to fig. 13, fig. 13 is a schematic view of a partial longitudinal section of an embodiment 13a of a packaging device according to the present application, fig. 13 is compared with fig. 2, except that the second package 20 includes terminals 21. With continued reference to fig. 13, the first package body 10 and the second package body 20 are connected by an electrical connector 30, the second package body 20 includes terminals 21, the terminals 21 are disposed in one-to-one correspondence with the conductive posts 12, the terminals 21 are at least partially disposed in the recesses 121 of the conductive posts 12, and the coating and electrical conductivity between the first package body 10 and the second package body 20 are increased by disposing the terminals 21 in the second package body 20. The functional layer structure 13 includes a molding layer 131 and an insulating layer 132, the insulating layer 132 is disposed on the substrate 11, the insulating layer 132 covers a part of side surfaces of the conductive columns 12, a part of side surfaces of the conductive columns 12 not covered by the insulating layer 132 are covered by the molding layer 131, and of course, in order to ensure that the conductive columns 12 are in contact with the electrical connectors 30, the upper surfaces of the molding layer 131 are flush with the upper surfaces of the conductive columns 12, and the upper surfaces of the conductive columns 12 are exposed, at this time, the molding layer 131 has an opening exposing the upper surfaces of the chips 14, and the upper surfaces of the chips 14 are flush with the upper surfaces of the molding layer 131, and the exposed structure of the molding layer 131 facilitates heat transfer and dissipation of the chips 14, which is helpful for reducing the temperature of the chips 14 and improving the stability and reliability of the packaging device provided by the embodiment of the application. For example, the insulating layer 132 and the mold seal layer 131 may have the same thickness, and the insulating layer 132 and the mold seal layer 131 may have different thicknesses.

In some embodiments, fig. 14 shows a schematic view of a partial longitudinal cross-section of an embodiment 14a of a packaging device according to the present application, fig. 14 being compared to fig. 3, except that the second package 20 comprises terminals 21. With continued reference to fig. 14, the first package body 10 and the second package body 20 are connected by an electrical connector 30, the second package body 20 includes terminals 21, the terminals 21 are disposed in one-to-one correspondence with the conductive posts 12, the terminals 21 are at least partially located in the recesses 121 of the conductive posts 12, and the coating and electrical conductivity between the first package body 10 and the second package body 20 are increased by providing the terminals 21 in the second package body 20. The functional layer structure 13 includes a molding layer 131 and an insulating layer 132, the insulating layer 132 is disposed on the substrate 11, the insulating layer 132 coats a part of side surfaces of the conductive columns 12, part of side surfaces of the conductive columns 12 which are not coated by the insulating layer 132 are coated by the molding layer 131, of course, in order to ensure that the conductive columns 12 are in contact with the electrical connectors 30, the upper surfaces of the molding layer 131 are flush with the upper surfaces of the conductive columns 12, the upper surfaces of the conductive columns 12 are exposed, at this time, the chip 14 is coated by the molding layer 131, the upper surfaces of the chip 14 are not flush with the upper surfaces of the molding layer 131, the chip 14 can be protected by covering the chip 14 with the molding layer 131, the chip 14 is prevented from being influenced by external environments such as mechanical damage, dust, moisture and the like, stability and reliability of the chip 14 are improved, and the molding layer 131 covers the chip 14 to provide insulating protection for the chip 14, the chip 14 is prevented from being in electrical contact with the external environment or other elements, and short circuit and faults are avoided. For example, the insulating layer 132 and the mold seal layer 131 may have the same thickness, and the insulating layer 132 and the mold seal layer 131 may have different thicknesses.

In some embodiments, fig. 15 shows a schematic view of a partial longitudinal cross-section of an embodiment 15a of a packaging device according to the present application, fig. 15 being compared to fig. 4, except that the second package 20 comprises terminals 21. With continued reference to fig. 15, the first package body 10 and the second package body 20 are connected by an electrical connector 30, the second package body 20 includes terminals 21, the terminals 21 are disposed in one-to-one correspondence with the conductive posts 12, the terminals 21 are at least partially located in the recesses 121 of the conductive posts 12, and the coating and electrical conductivity between the first package body 10 and the second package body 20 are increased by providing the terminals 21 in the second package body 20. The functional layer structure 13 includes a molding layer 131 and an insulating layer 132, the insulating layer 132 is disposed on the substrate 11, the insulating layer 132 covers a part of side surfaces of the conductive columns 12, a part of side surfaces of the conductive columns 12 not covered by the insulating layer 132 are covered by the molding layer 131, and of course, in order to ensure that the conductive columns 12 are in contact with the electrical connectors 30, the upper surfaces of the molding layer 131 are flush with the upper surfaces of the conductive columns 12, and the upper surfaces of the conductive columns 12 are exposed, at this time, the molding layer 131 has an opening exposing the upper surfaces of the chips 14, and the upper surfaces of the chips 14 are flush with the upper surfaces of the molding layer 131, and the exposed structure of the molding layer 131 facilitates heat transfer and dissipation of the chips 14, which is helpful for reducing the temperature of the chips 14 and improving the stability and reliability of the packaging device provided by the embodiment of the application. For example, the insulating layer 132 and the mold seal layer 131 may have the same thickness, and the insulating layer 132 and the mold seal layer 131 may have different thicknesses. A filling layer 15 is disposed between the chip 14 and the substrate 11, and the filling layer 15 may be, for example, an underfill, and the chip 14 is firmly fixed on the substrate 11 by the underfill, so as to prevent loosening or falling during use, and ensure stability and reliability of the electronic component. The underfill is filled in the micro gap between the chip 14 and the substrate 11, so that the heat conduction performance is improved, the heat dissipation is facilitated, the working temperature of the chip 14 is reduced, and the service life of the chip 14 is prolonged. The underfill may form an insulating layer 132 between the chip 14 and the substrate 11 to prevent short circuits between electronic components and improve stability and safety of the circuit. The underfill may fill the minute voids, preventing moisture and dust from entering the gap between the chip 14 and the substrate 11, and protecting the electronic components from the external environment. The underfill may also provide cushioning and protection to reduce mechanical shock and vibration to which the chip 14 is subjected during shipping and use, and reduce the risk of damage.

In some embodiments, referring to fig. 16, fig. 16 is a schematic view of a partial longitudinal cross-sectional structure of an embodiment 16a of a packaging apparatus according to the present application, fig. 16 is compared to fig. 5, except that the second package 20 includes terminals 21. With continued reference to fig. 16, the first package body 10 and the second package body 20 are connected by an electrical connector 30, the second package body 20 includes terminals 21, the terminals 21 are disposed in one-to-one correspondence with the conductive posts 12, the terminals 21 are at least partially disposed in the recesses 121 of the conductive posts 12, and the coating and electrical conductivity between the first package body 10 and the second package body 20 are increased by disposing the terminals 21 in the second package body 20. The functional layer structure 13 includes a molding layer 131 and an insulating layer 132, the insulating layer 132 is disposed on the substrate 11, the insulating layer 132 coats a part of side surfaces of the conductive columns 12, part of side surfaces of the conductive columns 12 which are not coated by the insulating layer 132 are coated by the molding layer 131, of course, in order to ensure that the conductive columns 12 are in contact with the electrical connectors 30, the upper surfaces of the molding layer 131 are flush with the upper surfaces of the conductive columns 12, the upper surfaces of the conductive columns 12 are exposed, at this time, the chip 14 is coated by the molding layer 131, the upper surfaces of the chip 14 are not flush with the upper surfaces of the molding layer 131, the chip 14 can be protected by covering the chip 14 with the molding layer 131, the chip 14 is prevented from being influenced by external environments such as mechanical damage, dust, moisture and the like, stability and reliability of the chip 14 are improved, and the molding layer 131 covers the chip 14 to provide insulating protection for the chip 14, the chip 14 is prevented from being in electrical contact with the external environment or other elements, and short circuit and faults are avoided. For example, the insulating layer 132 and the mold seal layer 131 may have the same thickness, and the insulating layer 132 and the mold seal layer 131 may have different thicknesses. A filling layer 15 is disposed between the chip 14 and the substrate 11, and the filling layer 15 may be, for example, an underfill, and the chip 14 is firmly fixed on the substrate 11 by the underfill, so as to prevent loosening or falling during use, and ensure stability and reliability of the electronic component. The underfill is filled in the micro gap between the chip 14 and the substrate 11, so that the heat conduction performance is improved, the heat dissipation is facilitated, the working temperature of the chip 14 is reduced, and the service life of the chip 14 is prolonged. The underfill may form an insulating layer 132 between the chip 14 and the substrate 11 to prevent short circuits between electronic components and improve stability and safety of the circuit. The underfill may fill the minute voids, preventing moisture and dust from entering the gap between the chip 14 and the substrate 11, and protecting the electronic components from the external environment. The underfill may also provide cushioning and protection to reduce mechanical shock and vibration to which the chip 14 is subjected during shipping and use, and reduce the risk of damage.

Referring to fig. 17A-17E, fig. 17A-17B are schematic views of steps of manufacturing an embodiment 13a of the package device of the present application, respectively, fig. 17A provides a substrate 11in a first package body 10, and a functional layer structure 13 and a chip 14 disposed on the substrate 11, wherein the functional layer structure 13 includes an insulating layer 132 and a mold layer disposed in layers, fig. 17B is a laser via hole formed on the structure in fig. 17, fig. 17C is a mask plate formed on an upper surface of the structure in fig. 17B with a plating layer having a recess 121 as a part of a conductive post 12, the recess 121 being located at a position corresponding to the conductive post 12, continuing to refer to fig. 17D, grinding the plating layer away from a position corresponding to the chip 14 so that the chip 14 is exposed, continuing to fig. 17E, a terminal 21 is disposed on a lower surface of a second package body 20, an electrical connector 30 is disposed in the recess 121, and the first package body 10 and the second package body 20 are connected by embedding the terminal 21 in the electrical connector 30.

As to the position of the terminal 21 in the second package 20, as shown in fig. 18 to 20, in fig. 18, the terminal 21 in the second package 20 is located in the middle of the recess 121 of the conductive post 12, in fig. 19, the terminal 21 in the second package 20 is located on the right side of the recess 121 of the conductive post 12, and in fig. 20, the terminal 21 in the second package 20 is located on the left side of the recess 121 of the conductive post 12.

In some specific embodiments, when the functional layer structure 13 is only the insulating layer 132 (not shown in the drawings), only the insulating layer 132 is disposed on the substrate 11, and the insulating layer 132 covers the side surface of the conductive post 12, in order to ensure that the conductive post 12 contacts the electrical connector 30, the upper surface of the insulating layer 132 is flush with the upper surface of the conductive post 12 and exposes the upper surface of the conductive post 12, for example, the chip 14 may be covered by the insulating layer 132, the upper surface of the chip 14 is not flush with the upper surface of the insulating layer 132, covering the chip 14 with the insulating layer 132 may provide protection for the chip 14 from mechanical damage, dust, moisture, and other external environments, and improve stability and reliability of the chip 14, and the insulating layer 132 may provide insulating protection for the chip 14, prevent the chip 14 from making electrical contact with the external environment or other elements, and avoid circuit short-circuits and faults. For example, at this time, the insulating layer 132 has an opening exposing the upper surface of the chip 14, the upper surface of the chip 14 is flush with the upper surface of the insulating layer 132, and the exposed structure of the insulating layer 132 facilitates heat transfer and dissipation of the chip 14, which is helpful for reducing the temperature of the chip 14 and improving the stability and reliability of the package device provided by the embodiment of the present application, and in addition, since the chip 14 not covered by the insulating layer 132 can reduce the thickness of the whole package device and reduce the weight. For example, a filler layer 15 may be provided between the chip 14 and the substrate 11.

In some specific embodiments, when the functional layer structure 13 is only the mold seal layer 131 (not shown in the drawings), only the mold seal layer 131 is disposed on the substrate 11, and the mold seal layer 131 covers the side surface of the conductive post 12, and of course, in order to ensure that the conductive post 12 contacts with the electrical connector 30, the upper surface of the mold seal layer 131 is flush with the upper surface of the conductive post 12, and exposes the upper surface of the conductive post 12, for example, the chip 14 may be covered by the mold seal layer 131, and the upper surface of the chip 14 is not flush with the upper surface of the mold seal layer 131, and covering the chip 14 with the mold seal layer 131 may provide protection for the chip 14 from mechanical damage, dust, moisture, and other external environments, so as to improve stability and reliability of the chip 14, and covering the chip 14 with the mold seal layer 131 may provide insulation protection for the chip 14, prevent the chip 14 from making electrical contact with the external environment or other elements, and avoid circuit short-circuits and faults. For example, at this time, the mold layer 131 has an opening exposing the upper surface of the chip 14, the upper surface of the chip 14 is flush with the upper surface of the mold layer 131, and the exposed structure of the mold layer 131 to facilitate heat transfer and dissipation of the chip 14 is helpful for reducing the temperature of the chip 14 and improving the stability and reliability of the package device provided by the embodiment of the present application, and in addition, the thickness of the entire package device can be reduced and the weight can be reduced due to the chip 14 not covered by the mold layer 131. For example, a filler layer 15 may be provided between the chip 14 and the substrate 11.

While the application has been described and illustrated with reference to specific embodiments thereof, the description and illustration is not intended to limit the application. It will be apparent to those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments thereof without departing from the true spirit and scope of the application as defined by the appended claims. The illustrations may not be drawn to scale. There may be a distinction between technical reproduction and actual implementation in the present application due to variables in the manufacturing process, etc. Other embodiments of the application not specifically illustrated may exist. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present application. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods applied herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present disclosure. Thus, the order and grouping of the operations is not a limitation of the present application unless specifically indicated herein.

Claims

1. A packaging apparatus comprising a first package, the first package comprising:

A substrate;

2. The packaging device of claim 1, wherein the conductive post is configured to connect with an electrical connector, the recess configured to receive a portion of the electrical connector.

3. The package assembly of claim 2 further comprising a second package disposed on said first package, said second package being electrically connected to said first package by said electrical connection.

4. The packaging device of claim 1, wherein the functional layer structure comprises an insulating layer or a mold layer.

5. The packaging device of claim 1, wherein the functional layer structure comprises an insulating layer and a mold seal layer;

6. The package of claim 5, wherein the first package further comprises a chip electrically connected to the substrate;

7. The package of claim 6, wherein the mold seal has an opening exposing an upper surface of the chip, the upper surface of the chip being flush with an upper surface of the mold seal.

8. The packaging device of claim 7, wherein the chip is encapsulated by the mold seal, and wherein an upper surface of the chip is not flush with an upper surface of the mold seal.

9. A packaging arrangement according to claim 3, wherein the second package comprises terminals arranged in a one-to-one correspondence with the conductive posts, the terminals being at least partially located in the recesses of the conductive posts.

10. The package of claim 3, wherein the conductive pillars further have a seed layer disposed between the conductive pillars and the contact surface of the functional layer structure.