CN222015392U

CN222015392U - HEMT transistor and device

Info

Publication number: CN222015392U
Application number: CN202420294453.9U
Authority: CN
Inventors: A·康斯坦特; F·尤科纳洛; C·特林加利; M·E·卡斯塔尼亚
Original assignee: Italian Semiconductor International Co
Current assignee: Italian Semiconductor International Co
Priority date: 2023-02-10
Filing date: 2024-02-08
Publication date: 2024-11-15
Anticipated expiration: 2034-02-08
Also published as: CN118486656A

Abstract

The present disclosure relates to HEMT transistors and devices. A HEMT transistor comprising: a first semiconductor layer; a gate electrode on the first side of the first semiconductor layer; and a first passivation layer made of a first dielectric material extending over the first face of the first semiconductor layer, a side face of the gate electrode, and at least a peripheral portion of a face of the gate electrode opposite the first semiconductor layer, wherein a second passivation layer made of a second dielectric material extends between the face of the gate electrode and the first passivation layer, the side face of the gate electrode being devoid of the second passivation layer.

Description

HEMT transistor and device

Cross Reference to Related Applications

The present application claims priority from french patent application FR2301258 entitled "transmitter HEMT" filed on 10, 2, 2023, which is incorporated herein by reference to the maximum extent allowed by law.

Technical Field

The present disclosure relates generally to the field of transistors, and more particularly to the field of high electron mobility transistors (also referred to as HEMTs).

Background

HEMT transistors rely on the formation of a heterojunction of two-dimensional electron gas (also known as 2 DEG) at their surface.

There is a need for improved HEMT transistors and methods of manufacturing the same.

Disclosure of utility model

To achieve this, an embodiment provides a HEMT transistor including:

a first semiconductor layer;

A gate electrode on the first surface of the first semiconductor layer; and

A first passivation layer made of a first dielectric material extending over the first face of the first semiconductor layer, the side of the gate electrode and at least a peripheral portion of the face of the gate electrode opposite the first semiconductor layer,

Wherein a second passivation layer made of a second dielectric material extends between the face of the gate and the first passivation layer, the side of the gate being free of the second passivation layer.

According to some embodiments, the first semiconductor layer is a gallium nitride-based layer.

According to some embodiments, the first semiconductor layer is made of aluminum gallium nitride.

According to some embodiments, the first passivation layer is made of aluminum oxide.

According to some embodiments, the second passivation layer is made of nitride.

According to some embodiments, the second passivation layer is made of silicon nitride, silicon carbonitride or aluminum nitride.

According to some embodiments, the second passivation layer is made of an oxide, for example, made of aluminum oxide or silicon dioxide.

According to some embodiments, the transistor includes a second semiconductor layer in contact with the second face of the first semiconductor layer on a side opposite the first face.

According to some embodiments, the second semiconductor layer is made of gallium nitride.

According to some embodiments, the transistor includes source contact metallization and drain contact metallization on either side of the gate, respectively.

Another embodiment provides a power conversion or matching circuit comprising at least one transistor according to the above embodiments.

Another embodiment provides a method of manufacturing a HEMT transistor, including the steps of:

a) Forming a first semiconductor layer;

Forming a gate electrode on the first surface of the first semiconductor layer; and

Forming a first passivation layer of a first dielectric material extending over the first face of the first semiconductor layer, the side of the gate electrode and at least a peripheral portion of the face of the gate electrode opposite the first semiconductor layer,

And wherein a second passivation layer made of a second dielectric material extends between the face of the gate and the first passivation layer, the side of the gate being free of the second passivation layer.

According to an embodiment, the method comprises the following successive steps:

depositing a layer made of a material of the gate electrode on a first face of the first semiconductor layer;

Depositing a layer made of a second dielectric material over the entire surface of the layer made of the material of the gate electrode;

The layer made of the material of the gate electrode and the layer made of the second dielectric material are locally etched through the same etching mask so that the gate electrode and the second passivation layer are formed, respectively.

Other embodiments also provide an apparatus comprising: a semiconductor stack having a first face; a gate layer over the semiconductor stack on the first side, the gate layer having a second side different from the first side of the semiconductor stack; a first passivation layer on the second side of the gate layer; and a second passivation layer covering the first passivation layer and the first side of the semiconductor stack.

In some embodiments, the second face of the gate layer includes an opening, and the first passivation layer and the second passivation layer cover the second face except for the opening.

In some embodiments, the semiconductor stack comprises: a substrate; a conductive layer over the substrate; and a semiconductor layer over the conductive layer, wherein the semiconductor stack is configured to form a two-dimensional electron gas between the conductive layer and the semiconductor layer.

In some embodiments, the semiconductor layer is made of aluminum gallium nitride. In some embodiments, the conductive layer is gallium nitride. In some embodiments, the first passivation layer is aluminum oxide. In some embodiments, the second passivation layer is aluminum oxide or silicon dioxide. In some embodiments, the second passivation layer is silicon nitride, silicon carbonitride, or aluminum nitride.

Drawings

The above features and advantages and other features and advantages are described in detail in the detailed description of the particular embodiments, which is given by way of example and not limitation in the remainder of the disclosure with reference to the accompanying drawings wherein:

Fig. 1 is a partially simplified cross-sectional view of an example of a HEMT transistor according to a first embodiment;

Fig. 2A, 2B, 2C, 2D, 2E, 2F, and 2G are cross-sectional views illustrating steps of an example of a manufacturing method of the HEMT transistor illustrated in fig. 1; and

Fig. 3 is a partially simplified cross-sectional view of an example of a HEMT transistor according to the second embodiment.

Detailed Description

Like features are indicated by like reference numerals in the various figures. In particular, structural and/or functional features common between the various embodiments may have the same reference numerals and may have the same structural, dimensional, and material characteristics.

For clarity, only the steps and elements useful for understanding the embodiments described herein are illustrated and described in detail. In particular, applications that the described HEMT transistor may have are not described in detail, embodiments are compatible with typical applications of HEMT transistors. More particularly, consider herein the field of HEMT transistors capable of withstanding relatively high voltages (e.g., voltages of about 100 to 650 volts) in the off (off) state. The described transistors may be used, for example, in various power conversion or matching circuits, such as industrial equipment, display or lighting devices, telecommunications equipment, automotive equipment, and the like.

Unless otherwise indicated, when two elements are referred to as being connected together, this means that there is no direct connection of any intermediate elements other than conductors, and when two elements are referred to as being coupled together, this means that the two elements may be connected or they may be coupled via one or more other elements.

In the following disclosure, unless otherwise indicated, when absolute positional qualifiers such as the terms "front", "rear", "top", "bottom", "left", "right", etc., or relative positional qualifiers such as the terms "above", "below", "upper", "lower", etc., or orientation qualifiers such as "horizontal", "vertical", etc., are referenced with respect to the orientation of the figures.

Unless otherwise indicated, the expressions "about", "substantially" and "approximately" mean within 10%, and preferably within 5%.

Fig. 1 is a partially simplified cross-sectional view of an example of a HEMT transistor 11 according to an embodiment.

The HEMT transistor 11 includes a first semiconductor layer 13 disposed on a second conductive layer 23. The semiconductor layer 23 is in contact with the upper surface of the conductive layer 23, for example, through its lower surface. As an example, a stack including the semiconductor layer 13 and the semiconductor layer 23 is located on the substrate 21. The semiconductor layer 23 is in contact with the upper surface of the substrate 21, for example, through its lower surface. The interface between the semiconductor layer 13 and the semiconductor layer 23 defines a heterojunction, at the surface of which a two-dimensional electron gas 2DEG, also referred to as an electron channel, is formed.

The semiconductor layers 13 and 23 are made of, for example, a III-V semiconductor material (e.g., based on gallium nitride (GaN)). The semiconductor layer 13 is made of, for example, aluminum gallium nitride (AlGaN). The semiconductor layer 23 is made of gallium nitride (GaN), for example.

As an example, the substrate 21 is made of a semiconductor material. The substrate 21 is made of silicon or silicon carbide, for example. As a modification, the substrate 21 is made of aluminum nitride. The substrate 21 includes, for example, on its upper surface side, a buffer layer made of, for example, gallium nitride, which is not described in detail in the drawings. The buffer layer is in contact with the lower surface of the semiconductor layer 23, for example, through its upper surface.

The HEMT transistor 11 includes a gate electrode 15 on the upper surface of the semiconductor layer 13. The gate electrode 15 is in contact with the upper surface of the semiconductor layer 13, for example, through its lower surface.

The gate 15 is made of, for example, a semiconductor material, for example, a III-V semiconductor material, for example, P-doped gallium nitride.

As an example, the HEMT transistor 11 further includes a source contact metallization 29 and a drain contact metallization 31. As an example, the contact metallizations 29 and 31 are based on titanium, titanium nitride and/or alloys of aluminum and copper. The source contact metallization 29 and the drain contact metallization 31 each define an ohmic contact with the semiconductor layer 13, for example. Contact metallizations 29 and 31 are located above semiconductor layer 13 and in contact with semiconductor layer 13, for example on either side of gate 15.

The HEMT transistor 11 also includes a passivation layer 25 made of a dielectric material that extends over the upper surface of the gate 15 but not over the sides of the gate. The passivation layer 25 is in contact with the upper surface of the gate electrode 15, for example, through its lower surface.

The passivation layer 25 has, for example, a thickness in the range of 1nm to 20nm, for example, a thickness in the range of 1nm to 10nm, for example, a thickness of about 2 nm.

The passivation layer 25 is made of nitride, for example, silicon nitride (Si ₃N₄), silicon carbonitride (SiO _xN_y), or aluminum nitride (AlN). The passivation layer 25 is made of, for example, oxide, such as aluminum oxide (Al ₂O₃) or silicon dioxide (SiO ₂).

The HEMT transistor 11 further includes a passivation layer 17 that covers at least a portion of the side and upper surfaces of the passivation layer 25, the side of the gate electrode 15, and extends over a portion of the upper surface of the semiconductor layer 13 that is not covered by the gate electrode 15. As an example, the passivation layer 17 is in contact with the upper surface of the semiconductor layer 13 through the lower surface thereof. The passivation layer 17 is also in contact with the sides of the gate 15, for example. The passivation layer 17 is also in contact with the upper surface of the semiconductor layer 13, for example, through its lower surface. In the embodiment of fig. 1, the passivation layer 17 extends laterally between the source contact metallization 29 and the drain contact metallization 31.

The passivation layer 17 has, for example, a thickness in the range of 2nm to 20nm, for example, a thickness in the range of 2nm to 10nm, for example, a thickness of about 5 nm. The passivation layer 17 is made of, for example, a dielectric material, such as aluminum oxide (Al ₂O₃), silicon dioxide (SiO ₂), aluminum nitride (AlN), or hafnium acid (HfO ₂).

For example, on top of the gate 15 is a gate contact metallization 27.

As an example, the gate contact metallization 27 is in contact with the upper surface of the gate 15 through its lower surface. Gate contact metallization 27 then extends through layers 17 and 25, layers 17 and 25 covering the upper surface of gate 15 only at the periphery of the upper surface of gate 15.

As a variant, the gate contact metallization 27 is in contact with the upper surface of the passivation layer 25 by its lower surface, the passivation layer 25 extending over the entire surface of the upper surface of the gate 15. Gate contact metallization 27 then extends through layer 17, layer 17 only peripherally covering passivation layer 25. This variant is illustrated, for example, by fig. 3 described below.

As an example, the gate contact metallization 27 is based on titanium nitride and/or titanium, and/or tantalum, and/or an alloy of tungsten and titanium, and/or an alloy of aluminum and copper.

The HEMT transistor 11 includes, for example, a multi-layered insulating layer, for example, a metallization is formed inside and on top of it.

As an example, the HEMT transistor 11 includes an insulating layer 33 on and in contact with the upper surface of the passivation layer 17. As an example, the insulating layer 33 covers the entire surface of the passivation layer 17. The insulating layer 33 is open, for example, in front of the central portion of the gate 15 to be penetrated by the gate contact metallization 27. The insulating layer 33 is made of, for example, a dielectric material, for example, an oxide, for example, silicon dioxide (SiO ₂).

As an example, the HEMT transistor 11 includes a metal region 37 that extends over a portion of the surface of the insulating layer 33. As an example, the metal region 37 is based on titanium nitride and/or titanium, and/or tantalum, and/or an alloy of tungsten and titanium, and/or an alloy of aluminum and copper. The metal region 37 is made of, for example, the same material as the gate contact metallization 27.

The HEMT transistor 11 may include a second insulating layer 39 that covers the entire structure except for the source contact metallization 29 and the drain contact metallization 31. The second insulating layer 39 is made of, for example, the same material as the insulating layer 33.

As an example, the source contact metallization 29 further extends towards the drain contact metallization 31 on the upper surface of the insulating layer 39 without reaching the drain contact metallization 31.

In the transistor of fig. 1, the 2DEG channel is for example normally off, i.e. it is interrupted under the gate 15, which prevents current from flowing between the source and drain of the transistor. The transistor is said to be in an off state. The channel may be restored (i.e., turned on) by the bias of the gate 15. In this case, a current can be established between the source and drain of the transistor. The described embodiments may also be applied to normally-on (normal-off) type transistors.

The presence of the passivation layer 17 allows to protect the upper surface of the semiconductor layer 13, on which dangling bonds may be present and leakage currents and/or a reduction of the transistor breakdown voltage may occur. The passivation layer 17 fills these bonds to electrically inert the surface of the semiconductor layer 13.

The passivation layer 17 also enables the semiconductor layer 13 to be protected from oxidation and to improve its surface state (to which the 2DEG channel is sensitive).

While passivation layer 17 plays an important role in the quality and lifetime of the transistor, its presence may result in accumulation of electrons under passivation layer 17 along the sides of gate 15. This phenomenon is enhanced by, for example, damage to the gate side caused by etching of the gate 15. The presence of the passivation layer 25 on the upper surface of the gate 15 allows to reduce the lateral leakage currents originating from the upper surface of the gate 15 and transported by these electrons.

The gate 15, preferably formed by epitaxy, for example has a gallium polarity, i.e. in its atomic arrangement the gate 15 ends at gallium atoms at the level of its upper surface, leaving nitrogen vacancies at the surface of that surface. An advantage of forming the second nitride passivation layer 25 at the surface of the upper surface of the gate electrode 15 is that it enables filling of nitrogen vacancies existing at the surface of the upper surface of the gate electrode 15 that may generate leakage current.

Fig. 2A, 2B, 2C, 2D, 2E, 2F, and 2G are cross-sectional views illustrating successive steps of an example of a method of manufacturing the HEMT transistor shown in fig. 1.

Fig. 2A illustrates an initial structure including, in order from the lower surface of the structure, a substrate 21, a second semiconductor layer 23, and a first semiconductor layer 13. The initial structure further includes a gate layer 15 with a passivation layer 25 on top. In the initial structure shown in fig. 2A, layers 23, 13, 15 and 25 extend continuously over the entire upper surface of substrate 21 and have a substantially uniform thickness.

As an example, the gate electrode 15 is formed on the upper surface of the layer 13 by a vapor deposition method (for example, a metal organic chemical vapor deposition or MOCVD method). As an example, the deposition of the gate 15 is performed under at least partial vacuum.

As an example, the passivation layer 25 is formed on the upper surface of the gate electrode 15 by MOCVD, for example, under at least partial vacuum. In this example, the passivation layer 25 and the gate electrode 15 are formed in the same chamber without vacuum break between the two depositions. Such a deposition method is used, for example, for forming a nitride passivation layer 25 made of, for example, silicon nitride or aluminum nitride.

As a modification, a passivation layer 25 is formed on the upper surface of the gate electrode 15 by an atomic layer deposition or ALD method. By way of example, the deposition method of the passivation layer 25 is plasma enhanced. Such a deposition method is used, for example, for forming a nitride passivation layer 25, the nitride passivation layer 25 being made of, for example, silicon nitride, aluminum nitride or silicon carbonitride.

Fig. 2B illustrates the structure obtained at the end of the step of partial etching of the gate layer 15 and the passivation layer 25 to leave only a portion of each layer forming the gate stack of the transistor of fig. 1.

During this step, the passivation layer 25 is etched, for example by a plasma etching method, for example by a chlorine-based plasma etching method (for example by boron trichloride (BCl ₃) plasma etching).

During this step, the gate electrode 15 is further etched, for example by a plasma etching method, for example by a chlorine-based plasma etching method, for example by chlorine (Cl ₂) and oxygen (O ₂) plasma etching.

As an example, the gate electrode 15 and the passivation layer 25 are etched through the same mask. At the end of this step, the gate 15 and the passivation layer 25 are thus aligned, i.e. their sides are aligned.

The steps of etching the gate 15 and the passivation layer 25 are for example performed simultaneously, i.e. they are formed in the same etching chamber. As a variant, the etching steps of the gate 15 and of the passivation layer 25 are performed one after the other.

These etching steps are followed by, for example, a cleaning step of the upper surface of the structure, for example, to remove residues originating from the etching mask and impurities originating from etching the passivation layer 25 and the gate electrode 15. The cleaning of the structure includes, for example, a step of stripping by an oxygen and nitrogen (N ₂) plasma. The cleaning of the structure may further comprise a step of removing the organic residues by means of a solvent.

Fig. 2C illustrates the structure obtained at the end of the step of forming the passivation layer 17 and the insulating layer 33 on the upper surface of the structure shown in fig. 2B.

During this step, the passivation layer 17 is first manufactured in a continuous manner so that it covers the entire upper surface of the structure shown in fig. 2B.

The passivation layer 17 is formed in contact with, for example, the upper surface of the semiconductor layer 13, the side surface of the gate electrode 15, and the side and upper surfaces of the passivation layer 25.

The passivation layer 17 is formed, for example, by a thin layer deposition method (for example, by ALD). By way of example, the deposition method of the passivation layer 17 is plasma enhanced.

Then, in this example, the insulating layer 33 is formed in a continuous manner so that it covers the entire upper surface of the passivation layer 17. The insulating layer 33 is formed in contact with the passivation layer 17, for example. The insulating layer 33 is formed by, for example, plasma enhanced chemical vapor deposition or PECVD. At the end of this step, the insulating layer 33 has a thickness in the range of, for example, 150nm to 400nm, for example, 200nm to 350nm, for example, about 260 nm.

By way of example, the step of depositing passivation layer 17 and insulating layer 33 is preceded by one or more preparation steps of the surface of the structure shown in fig. 2B. The preparation of the surface of the structure shown in fig. 2B may include cleaning, including for example chemical cleaning with the aid of an acid, such as hydrogen chloride (HCl) or Hydrogen Fluoride (HF). The preparation of the surface of the structure shown in fig. 2B may also include cleaning, including for example surface oxidation. Thus, the passivation layer 17 will be formed in contact with the oxide film, which itself is formed in contact with the upper surface of the layer 13.

Fig. 2D illustrates the structure obtained at the end of the opening step of layers 17, 25 and 33 in front of gate 15 of the structure shown in fig. 2C.

More specifically, during this step, the passivation layers 17 and 25 and the insulating layer 33 are removed in front of the central portion of the upper surface of the gate electrode 15.

As an example, this step first includes removing layer 33, then removing layers 17 and 25. As an example, the removal of layer 33 is performed by, for example, fluorine-based (e.g., carbon tetrafluoride (CF ₄) -based) plasma etching.

As an example, the removal of layers 17 and 25 is performed by, for example, a chlorine-based, for example, boron trichloride (BCl ₃) -based plasma etch. In this example, layers 17 and 25 are etched to expose the upper surface of gate 15.

As a modification, during this step, the passivation layer 25 is not removed in front of the central portion of the upper surface of the gate electrode 15, and when the upper surface of the passivation layer 25 is exposed, etching of the passivation layer 17 is interrupted.

For example, the etching described above may be followed by a cleaning step of the upper surface of the structure, for example similar to that described in connection with fig. 2B.

Fig. 2E illustrates the structure obtained at the end of the step of forming the metallization 27 and the region 37 on the upper surface of the structure shown in fig. 2D.

During this step, the gate contact metallization 27 is formed, for example, in openings formed in the layers 17 and 33 in front of the central portion of the gate 15. As an example, a gate contact metallization 27 is formed on and in contact with the upper surface of the gate electrode 15. As a modification, a gate contact metallization 27 is formed on and in contact with the upper surface of the passivation layer 25.

As an example, during this step, a region 37 is also formed on a portion of the surface of the first insulating layer 33. The gate contact metallization 27 and the region 37 are formed, for example, by depositing one or more layers made of a metallic material followed by an etching step.

As an example, the step of forming the gate contact metallization 27 and the region 37 is preceded by a preparation step of the surface of the structure shown in fig. 2D, for example comprising a chemical cleaning by means of an acid, for example hydrogen chloride (HCl).

Fig. 2F illustrates the structure obtained at the end of the step of forming the insulating layer 39 on the upper surface of the structure shown in fig. 2E.

During this step, an insulating layer 39 is formed, for example, over the entire wafer such that it covers the entire upper surface of the structure shown in fig. 2E, i.e., the upper surface and sides of gate contact metallization 27 and region 37, as well as a portion of layer 33. The insulating layer 39 is formed by, for example, the same method as the method of forming the layer 33 described with respect to fig. 2C. At the end of this step, the insulating layer 39 has a thickness, for example, in the range of 150nm to 400nm, for example in the range of 200nm to 350nm, for example about 260 nm.

Fig. 2G illustrates the steps at the end of the step of forming openings localized in the stack of dielectric or dielectric layers 39, 33 and 17 so as to expose the upper surface of semiconductor layer 13 facing the source and drain contact regions of the transistor, followed by the step of forming source and drain contact metallizations 29 and 31 in said openings. The structure thus obtained is for example identical or similar to the structure shown in fig. 1.

The openings intended to accommodate the source contact metallization 29 and the drain contact metallization 31 are formed, for example, by a fluorine-based, e.g. carbon tetrafluoride (CF ₄) based, plasma etching method. The etching described above is, for example, selective and does not etch the gallium nitride semiconductor layer 13. Thus, the etching of layers 17, 33 and 39 stops when the upper surface of layer 13 is exposed. The step of forming the opening intended to accommodate the contact metallizations 29 and 31 is followed, for example, by a step of cleaning the upper surface of the structure, for example similar to the steps already described in connection with fig. 2B. As an example, a surface of the upper surface of layer 13 in the preparation opening may be provided to accommodate the step of contacting metallizations 29 and 31. This step comprises, for example, a chemical cleaning with the aid of an acid, such as hydrogen chloride (HCl).

In the second stage, source contact metallization 29 and drain contact metallization 31 are formed, for example in openings formed previously. The metallizations 29, 31 and the regions 41 are formed, for example, by depositing one or more layers made of a metallic material over the entire upper surface of the structure (here, the upper surface of the layers 13 and 39), and then performing an etching step to laterally define the source and drain contact metallizations 29 and 31.

Fig. 3 is a partially simplified cross-sectional view of an example of a HEMT transistor 11' according to the second embodiment.

The transistor 11 'shown in fig. 3 is similar to the transistor 11 shown in fig. 1, except that in the method of manufacturing the transistor 11', the source contact metallization 29 and the drain contact metallization 31 have been formed before the gate contact metallization 27 is formed, whereas in the method of manufacturing the transistor 11, the source contact metallization 29 and the drain contact metallization 31 are formed after the gate contact metallization 27 is formed.

More specifically, in this example, transistor 11' differs from transistor 11 in that gate contact metallization 27 spans layer 39 and layer 39 covers contact metallizations 29 and 31.

Various embodiments and modifications have been described. Those skilled in the art will appreciate that certain features of the various embodiments and variations may be combined and that other variations will occur to those skilled in the art.

Further, although an example of an embodiment in which the transistor gate electrode 15 is in contact with the upper surface of the upper semiconductor layer 13 has been described above, as a modification, the gate electrode 15 may be separated from the semiconductor layer 13 by a gate insulating layer.

Finally, embodiments are not limited to numerical examples mentioned in this disclosure nor to material examples.

Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the competence of a person skilled in the art.

A HEMT transistor (11) may be summarized as including: a first semiconductor layer (13); a gate electrode (15) on a first surface of the first semiconductor layer (13); and a first passivation layer (17) made of a first dielectric material extending over said first face of the first semiconductor layer, a side face of the gate (15) and at least a peripheral portion of a face of the gate opposite the first semiconductor layer, wherein a second passivation layer (25) made of a second dielectric material extends between said face of the gate and the first passivation layer, said side face of the gate (15) being free of said second passivation layer (25).

The first semiconductor layer (13) may be a gallium nitride based layer.

The first semiconductor layer (13) may be made of aluminum gallium nitride.

The first passivation layer (17) may be made of aluminum oxide.

The second passivation layer (25) may be made of nitride.

The second passivation layer (25) may be made of silicon nitride, silicon carbonitride or aluminum nitride.

The second passivation layer (25) may be made of an oxide, for example, aluminum oxide (Al ₂O₃) or silicon dioxide (SiO ₂).

The transistor may include a second semiconductor layer (23) in contact with the second face of the first semiconductor layer (13) on a side opposite to the first face.

The second semiconductor layer (23) may be made of gallium nitride.

The transistor may include source contact metallization (29) and drain contact metallization (31) on either side of the gate (15), respectively.

A power conversion or matching circuit may be summarized as including at least one transistor.

A method of manufacturing a HEMT transistor can be summarized as including the steps of: a) Forming a first semiconductor layer (13); forming a gate electrode (15) on a first face of the first semiconductor layer (13); and forming a first passivation layer (17) made of a first dielectric material extending over said first face of the first semiconductor layer, a side face of the gate (15) and at least a peripheral portion of a face of the gate opposite the first semiconductor layer, and a second passivation layer (25) made of a second dielectric material extending between said face of the gate and the first passivation layer, said side face of the gate (15) being free of said second passivation layer (25).

The method may comprise the following successive steps: depositing a layer made of a material of the gate electrode (15) on a first face of the first semiconductor layer (13); depositing a layer of a second dielectric material over the entire surface of the layer of the material of the gate (15); the layer made of the material of the gate electrode (15) and the layer made of the second dielectric material are locally etched through the same etching mask so that the gate electrode (15) and the second passivation layer (25) are formed, respectively.

The various embodiments described above may be combined to provide further embodiments. Aspects of the embodiments can be modified to provide additional embodiments if necessary to employ concepts of the various patents, applications and publications.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims

1. A kind of HEMT transistor, characterized by comprising the following steps:

a first semiconductor layer;

A gate electrode on the first surface of the first semiconductor layer; and

A first passivation layer of a first dielectric material extending over the first face of the first semiconductor layer, the side of the gate electrode and at least a peripheral portion of the face of the gate electrode opposite the first semiconductor layer,

A second passivation layer of a second dielectric material extends between the face of the gate and the first passivation layer, the side of the gate being free of the second passivation layer.

2. The transistor of claim 1, comprising a second semiconductor layer in contact with the second face of the first semiconductor layer on a second face opposite the first face.

3. The transistor of claim 1, comprising source contact metallization and drain contact metallization on either side of the gate, respectively.

4. An apparatus, comprising:

A semiconductor stack having a first face;

A gate layer over the semiconductor stack on the first side, the gate layer having a second side different from the first side of the semiconductor stack;

a first passivation layer on the second side of the gate layer; and

And a second passivation layer covering the first passivation layer and the first side of the semiconductor stack.

5. The apparatus of claim 4, wherein the second face of the gate layer comprises an opening, and the first passivation layer and the second passivation layer cover the second face except for the opening.

6. The apparatus of claim 4, wherein the semiconductor stack comprises:

A substrate;

a conductive layer over the substrate; and

And a semiconductor layer over the conductive layer, wherein the semiconductor stack includes forming a two-dimensional electron gas between the conductive layer and the semiconductor layer.