CN221960961U - High power density integrated circuit module packaging structure - Google Patents

Abstract

A high-power density integrated circuit module packaging structure belongs to the field of microelectronic device packaging technology. In the inner cavity assembly area of the ceramic package shell, a heat sink area and a functional area are set in the chip assembly area. The heat sink area and the functional area are set as flat-bottomed pits. According to the chip power in the circuit, the chip is graded and a stepped structure of 2 or more levels is adopted. The chip power is distributed from large to small, from deep flat-bottomed pits to shallow flat-bottomed pits. The heat sink area is lower than the functional area. The high-power power chip is assembled in the heat sink area, and the low-power functional chip is assembled in the functional area. A metal through hole penetrating the ceramic base body is set under the heat sink area or the functional area to perform the shortest path heat dissipation and the shortest path internal and external electrical connection. It solves the problems of low power density, low integration, large parasitic impedance and parasitic inductance, low reliability and high application cost of existing high-power devices (components or modules). It is widely used in the field of high-reliability power integrated circuit module integration technology.

Description

A high power density integrated circuit module packaging structure

Technical Field

The utility model belongs to the technical field of microelectronic device packaging, and further relates to the technical field of power hybrid integrated circuit ceramic packaging, and specifically, to a high power density integrated circuit module packaging structure.

Background Art

Integrated packaging is the science and technology of establishing interconnections and a suitable working environment for electronic circuits. It is the bridge between chips, devices, components and products. In the integrated circuit packaging industry, one generation of chips requires one generation of packaging. With the reduction of the feature size of integrated circuits and the increase of operating speed, the industry has also put forward new and higher requirements for integrated circuit packaging technology. Driven by the needs of precision-guided weapons, aerospace automobile industry, consumer electronics and other fields, challenges have been raised to traditional packaging processes. The semiconductor industry is developing rapidly towards high integration and small size. System-level packaging (SIP) with advantages such as large-scale, multi-chip, and 3D stereoscopic packaging has received more and more attention. In order to meet higher requirements, advanced packaging technologies such as system-level packaging (SIP) are increasingly used in the field of navigation and guidance control. Using system-level packaging (SIP), the packaging of high-power devices (components or modules) has the characteristics of high power density, high reliability, and high conversion efficiency. The heat dissipation design of high-power devices (components or modules) is the main problem that limits the power density design and device integration design of high-power devices. The heat dissipation measures are complex, the volume is large, the product integration is difficult to improve, the parasitic impedance and parasitic inductance are large, the application cost is high, and the reliability is low. Therefore, it is of great significance to realize the high power, integration and miniaturization of hybrid integrated circuits of high-power devices (components or modules) and to design a miniaturized and highly integrated ceramic part.

In view of this, the present utility model is proposed.

Summary of the invention

The technical problem to be solved by the utility model is to solve the problems of low power density, low integration, large parasitic impedance and parasitic inductance, low reliability and high application cost of existing high-power devices (components or modules).

The inventive concept of the utility model is: in the inner cavity assembly area of the ceramic package shell, the chip assembly area is set with a heat sink area and a functional area, the heat sink area and the functional area are set as flat bottom pits, and the chip power in the circuit is graded, and a stepped structure of 2 or more levels is adopted, and the chip power is distributed from large to small, from deep flat bottom pits to shallow flat bottom pits, and the heat sink area is lower than the functional area. The high-power power chip is assembled in the heat sink area, and the low-power functional chip is assembled in the functional area. A metal through hole penetrating the ceramic base body is set below the heat sink area or the functional area to perform the shortest path heat dissipation and the shortest path internal and external electrical connection. In the local area (key parasitic parameter area) of the packaging structure, a high-conductivity and high-thermal-conductivity metal through hole material is used to penetrate the ceramic base body to achieve a through connection, which greatly improves the heat dissipation efficiency of the product to the equipment base, reduces the parasitic impedance and inductive reactance of the product, and thus improves the product reliability. The power hybrid integrated circuit device is made high-power, integrated, and miniaturized, which can meet the high reliability, high integration and technical requirements of the power hybrid integrated circuit device in scientific research and production of the external packaging product.

To this end, the utility model provides a high power density hybrid integrated circuit module packaging structure, as shown in Figures 1-8. It includes:

Ceramic base body 1, annular frame 101, ceramic isolation wall 102, heat sink area 2, functional area 3, heat sink area chip welding metal layer 4, functional area chip welding metal layer 5, package internal cavity 6, sealing ring 7, through-type metal through hole 8, bottom surface electrode 9, cover plate 10, inner lead bonding area and conductive tape 11.

The sealing ring 1 is located on the top of the annular frame 101 of the ceramic base body 1 .

The ceramic base body 1 is a multi-layer ceramic co-fired body, each ceramic layer has metal through holes and interconnection lines, and the layers are electrically connected through the metal through holes and interconnection lines according to the set circuits.

The bottom surface of the ceramic base body 1 has at least one bottom surface electrode 9 , and the bottom surface electrode 9 is connected to the corresponding electrode terminal of the internal cavity 6 of the package.

The ceramic base body 1 includes a raised annular frame 101 and an assembly area below the bottom of the annular frame. The assembly area includes a through metal via 8, a heat sink area chip welding metal layer 4, a functional area chip welding metal layer 5, an inner lead bonding area and a conductive tape 11.

The chip welding metal layer 4 in the heat sink area and the chip welding metal layer 5 in the functional area are isolated by a ceramic isolation wall 102. According to the circuit performance requirements, each chip welding metal layer is made in a flat bottom pit area with different depths.

The through-type metal via 8 is located directly below the chip welding metal layer and vertically penetrates the ceramic base body 1 . The inner surface of the through-type metal via 8 is connected to the back of the chip, and the outer surface of the through-type metal via 8 is connected to the corresponding bottom surface electrode 9 .

The corresponding devices in the assembly area are connected to the inner lead bonding area 11 through bonding wires.

The cover plate 10 is located on the sealing ring 7 and is sealedly connected to the sealing ring 7 .

In summary, the utility model has the characteristics of good insulation performance, ultra-small size, ultra-high integration, ultra-light weight, fast heat dissipation, high reliability, and wide coverage of product categories. It solves the problems of heat conduction and high current conduction as well as bonding problems, and improves the high power density and reliability of the package. It can be widely used in various products with high reliability requirements such as semiconductor devices, semiconductor power devices, and hybrid integrated circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of the longitudinal structure of the packaging structure.

FIG. 2 is a schematic diagram of the internal planar structure of the packaging structure.

FIG. 3 is a schematic diagram of the bottom surface electrode layout structure of the packaging structure.

FIG. 4 is a schematic diagram showing the position of the section line of the packaging structure.

FIG. 5 is a schematic diagram of a cross-sectional structure of the packaging structure along the AA cross-sectional line.

FIG. 6 is a schematic diagram of a cross-sectional structure of the packaging structure along the BB cross-sectional line.

FIG. 7 is a schematic diagram of the longitudinal side structure of the packaging structure.

FIG. 8 is a schematic diagram of the lateral side structure of the packaging structure.

In the figure: 1 is the ceramic base body, 101 is the annular frame, 102 is the ceramic isolation wall, 2 is the heat sink area, 3 is the functional area, 4 is the chip welding metal layer in the heat sink area, 5 is the chip welding metal layer in the functional area, 6 is the internal cavity of the package, 7 is the sealing ring, 8 is the through-type metal through hole, 9 is the bottom surface electrode, 10 is the cover plate, and 11 is the inner lead bonding area and the guide strip.

DETAILED DESCRIPTION

As shown in FIG. 1-8 , taking a package shell of a multi-channel high-voltage field effect transistor module array as an example, the specific implementation of the high power density integrated circuit module packaging method and its packaging structure is as follows:

The heat sink area 2 and the functional area 3 adopt a two-level stepped structure, and the heat sink area 2 is lower than the functional area 3.

The sealing ring 7 and the cover plate 10 are sealed and connected by parallel seam welding.

The heat sink area consists of six areas, the functional area consists of six areas, and the inner lead bonding area consists of twelve areas.

The bottom surface electrodes 9 are L-shaped and distributed along the packaging shell on both sides of the ceramic base body 1 , with 9 electrodes each, the vertical portion being located on the side of the ceramic base body 1 and the horizontal portion being located on the bottom surface of the ceramic base body 1 .

1. Packaging structure:

(1) As shown in Figure 2, A1, C1, A2, C2, A3, C3, A4, C4, A5, C5, A6, C6 are inner lead bonding areas and conduction strips; B1, B3, B5, B8, B10, B12 are chip welding metal layers in the heat sink area (inner cavity metallized electrode area); B2, B4, B6, B7, B9, B11 are chip welding metal layers in the functional area (inner cavity metallized electrode area).

(2) As shown in Figure 3, A1-1, B1-1/B2-1, C1-1, A2-1, B3-1/B4-1, C2-1, A3-1, B5-1/B6-1, C3-1, A4-1, B7-1/B8-1, C4-1, A5-1, B9-1/B10-1, C5-1, A6-1, B11-1/B12-1, and C6-1 are bottom surface electrodes 9, and there are 18 bottom surface electrodes in total.

The connection relationship between the bottom surface electrode and the inner cavity metallized electrode area is: A1 is connected to A1-1, B1 and B2 are connected to B1-1/B2-1, C1 is connected to C1-1, A2 is connected to A2-1, B3 and B4 are connected to B3-1/B4-1, C2 is connected to C2-1, A3 is connected to A3-1, B5 and B6 are connected to B5-1/B6-1, C3 is connected to C3-1, A4 is connected to A4-1, B7 and B8 are connected to B7-1/B8-1, C4 is connected to C4-1, A5 is connected to A5-1, B9 and B10 are connected to B9-1/B10-1, C5 is connected to C5-1, A6 is connected to A6-1, B11 and B12 are connected to B11-1/B12-1, and C6 is connected to C6-1.

(3) The metal layer (external lead-out electrode, wire bonding area, chip welding area) is composed of multiple layers of metal materials, the surface layer material is a gold layer, the second layer material is a metal nickel layer, a nickel-cobalt layer or a nickel-phosphorus layer, and the third layer material is a metal tungsten layer or a molybdenum-manganese layer. The surface layer material is pure gold, the second layer material is metal nickel, nickel-cobalt or nickel-phosphorus, and the third layer material is metal tungsten or molybdenum-manganese. The surface layer and the second layer material are plated by electroplating, and the third layer material is a metal paste first printed on the ceramic and then solidified.

(4) The thickness range of each metal layer in the metallization layer of the external lead-out electrode, the wire bonding area, and the chip welding area is as follows: the thickness of the surface material gold is 1.3 to 5.7 um, with a purity of ≥99.9%; the thickness of the second layer material metal nickel, nickel cobalt or nickel phosphorus is 1.3 to 8.9 um; the thickness of the third layer material metal tungsten or molybdenum manganese is 5 to 30 um.

(5) As shown in FIG. 1 , the key materials of the various parts of the package shell are: the material of the sealing ring 7 is 4J42/4J29; the material of the ceramic base body 1 is more than 95% Al ₂ O ₃ ceramic or AlN ceramic; the material of the through-type metal via 8 is tungsten slurry.

(6) The shell sealing ring and the cover plate are connected by parallel seam welding.

2. Packaging method:

(1) Cleaning the outer shell (base, cover)

First, wet clean the shell and use vacuum or nitrogen baking: first soak the package shell in acetone for 10 minutes, then use ultrasonic low-frequency cleaning for 3 minutes, conventional water rinse for 5 minutes, ionized water rinse for 10 minutes, alcohol dehydration treatment, and bake in a nitrogen oven at 60°C.

Then the shell is cleaned by argon plasma: the power of argon plasma cleaning is set to 100W, the argon flow rate is ≯50SCCM, the cleaning time is set to 180s, and each cleaning must be used up within 24 hours.

(2) Wet clean the packaging mold and bake it using vacuum or nitrogen: the method is the same as step (1).

(3) Prepare the power MOS chip, subsystem control chip and peripheral auxiliary control chip to be packaged, passive components, and select welding materials (high-temperature solder pads). The solder pads need to be plasma cleaned before use (the method is the same as step (1)).

(4) Assembling the chip: First, install solder pads in each welding area. Then, place the chip on the solder pads in each welding area according to the set position requirements. Then, place a quartz press on the chip. Finally, place the assembled mold as a whole in a vacuum sintering furnace for high-temperature sintering.

(5) Place the module of step (4) into a vacuum sintering furnace: heat the module to a preset temperature T1 at a set heating rate V1 under nitrogen conditions, vacuumize after keeping the temperature for t1 time, and refill with nitrogen after vacuumizing for t2 time; heat the module to a preset temperature T2 at a set heating rate V2, vacuumize after keeping the temperature for t3 time, and refill with nitrogen after vacuumizing for t4 time; heat the module to a preset temperature T3 (maximum temperature) at a set heating rate V3, start cooling after keeping the temperature for t5 time, set the cooling rate V4, start filling with nitrogen when the temperature drops below the melting point, and finally cool naturally with the furnace to complete the device sintering. The heating rate is: V1＞V2＞V3＞V4.

(6) After sintering, the module is wire-bonded between the bonding points on the chip and the inner surface electrodes using bonding wires according to the circuit connection requirements to obtain a module with interconnected electrical properties.

(7) Place the module with electrically interconnected properties in step (6) into a parallel seam welding device, install a cover plate on the housing, and perform sealing welding between the housing sealing ring and the cover plate to achieve module packaging of a high power density integrated circuit module.

The chips are all silicon-based chips, and the back metallization layer is an Au layer or an Ag layer.

The soldering sheet material of the chip and the metal layer is AuSn or PbSnAg.

The eutectic welding temperature range of the AuSn or PbSnAg welding sheet is 320° C. to 350° C., the welding time is 30s to 150s, and the welding atmosphere is vacuum.

The cover plate is a metal cover plate (composition is 4J42 or 4J29),

After the shell and the cover plate are hermetically sealed by parallel seam welding, the internal water vapor content is ≤5000ppm and the leakage rate is ≤1×10 ^-1 Pa·cm ³ /s.

The bonding wire is a silicon aluminum wire with a wire diameter of ≥380 μm.

Finally, it should be noted that the above embodiments are only examples for clear explanation. The present utility model includes but is not limited to the above embodiments. It is not necessary and impossible to list all implementation methods here. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made on the basis of the above description. All implementation methods that meet the requirements of the present utility model belong to the protection scope of the present utility model.

Claims (9)

1. A high power density integrated circuit module package structure, characterized by: the ceramic base comprises a ceramic base body, an annular frame, a ceramic partition wall, a heat sink region, a functional region, a heat sink region chip welding metal layer, a functional region chip welding metal layer, a package internal cavity, a sealing ring, a penetrating metal through hole, a bottom surface electrode, a cover plate, an inner lead bonding region and a conduction band;

the sealing ring is positioned at the top of the annular frame of the ceramic base body;

The ceramic base body is a multilayer ceramic cofiring body, each layer of ceramic is provided with a metal through hole and an interconnection line, and the layers are electrically connected through the metal through holes and the interconnection lines according to a set line;

The bottom surface of the ceramic base body is provided with more than 1 bottom surface electrode, and the bottom surface electrode is connected with the electrode end corresponding to the internal cavity of the package;

The ceramic base body comprises a raised annular frame and an assembly area lower than the bottom of the annular frame, wherein the assembly area comprises a penetrating metal through hole, a heat sink area chip welding metal layer, a functional area chip welding metal layer, an inner lead bonding area and a conduction band;

The heat sink area chip welding metal layers and the functional area chip welding metal layers are isolated by ceramic isolation walls, and each chip welding metal layer is manufactured in a flat bottom pit area with different depths according to the circuit performance requirements;

The penetrating metal through hole is positioned under the chip welding metal layer, vertically penetrates through the ceramic base body, the inner surface of the penetrating metal through hole is connected with the back surface of the chip, and the outer surface of the penetrating metal through hole is connected with the corresponding bottom surface electrode;

the corresponding devices in the assembly area are connected with the inner lead bonding area through bonding wires;

the cover plate is positioned on the sealing ring and is connected with the sealing ring in a sealing way.

2. The high power density integrated circuit module package structure of claim 1, wherein: the heat sink area and the functional area adopt a 2-level step structure, and the heat sink area is lower than the functional area.

3. The high power density integrated circuit module package structure of claim 1, wherein: the sealing ring is in sealing connection with the cover plate by adopting parallel seam welding.

4. The package structure of claim 1, wherein the specific structure is:

A1, C1, A2, C2, A3, C3, A4, C4, A5, C5, A6, C6 are inner wire bond regions and conduction bands;

B1, B3, B5, B8, B10 and B12 are heat sink area chip welding metal layers;

b2, B4, B6, B7, B9 and B11 are functional area chip welding metal layers;

A1-1、B1-1/B2-1、C1-1、A2-1、B3-1/B4-1、C2-1、A3-1、B5-1/B6-1、C3-1、A4-1、B7-1/B8-1、C4-1、A5-1、B9-1/B10-1、C5-1、A6-1、B11-1/B12-1、C6-1 Is a bottom surface electrode;

The connection relation between the bottom surface electrode and the chip welding metal layer is as follows: a1 is connected with A1-1, B1 and B2 are connected with B1-1/B2-1, C1 is connected with C1-1, A2 is connected with A2-1, B3 and B4 are connected with B3-1/B4-1, C2 is connected with C2-1, A3 is connected with A3-1, B5 and B6 are connected with B5-1/B6-1, C3 is connected with C3-1, A4 is connected with A4-1, B7 and B8 are connected with B7-1/B8-1, C4 is connected with C4-1, A5 is connected with A5-1, B9 and B10 are connected with B9-1/B10-1, C5 is connected with C5-1, A6 is connected with A6-1, B11 and B12 are connected with B11-1/B12-1, and C6 is connected with C6-1.

5. The high power density integrated circuit module package structure of claim 1, wherein: the bottom surface electrode is L type, distributes in the both sides of ceramic base body along the encapsulation shell, and every 9, and vertical part is located the side of ceramic base body, and horizontal part is located the bottom surface of ceramic base body.

6. The high power density integrated circuit module package structure of claim 1, wherein: the metal layer is composed of a plurality of layers of metal materials, the surface layer material is a gold layer, the second layer material is a metal nickel layer, a nickel cobalt layer or a nickel phosphorus layer, and the third layer material is a metal tungsten layer or a molybdenum manganese layer.

7. The high power density integrated circuit module package structure of claim 1, wherein: the thickness range of each layer of metal in the metal layer is as follows: the thickness of the surface layer is 1.3-5.7 um, the thickness of the second layer is 1.3-8.9 um, and the thickness of the third layer is 5-30 um.

8. The high power density integrated circuit module package structure of claim 1, wherein: and a soldering lug layer is arranged between the chip and the metal layer, and the soldering lug material is AuSn or PbSnAg.

9. The high power density integrated circuit module package structure of claim 1, wherein: after the sealing ring and the cover plate are hermetically sealed by parallel seam welding, the internal water vapor content is less than or equal to 5000ppm, and the leakage rate is less than or equal to 1 multiplied by 10 ^-1 Pa·cm³/s.