CN221960231U - Anti-interference load detection circuit - Google Patents

Abstract

The present application provides an anti-interference load detection circuit, which relates to the field of load detection technology. The anti-interference load detection circuit has parasitic capacitance, and the load detection circuit includes a first diode and a second diode, the positive electrode of the first diode is connected to the live wire, the negative electrode of the first diode is connected to one end of the parasitic capacitance, and the negative electrode of the first diode is used to connect the input end of the load; the positive electrode of the second diode is connected to the other end of the parasitic capacitance, and the positive electrode of the second diode is used to connect the output end of the load, and the negative electrode of the second diode is connected to the neutral line and the detection port, which can reduce the interference of the parasitic capacitance on the load detection process.

Description

Anti-interference load detection circuit

Technical Field

The present application relates to the technical field of load detection, and in particular to an interference-resistant load detection circuit.

Background Art

The AC power supplies power to the load end through the line. The more power the load uses, the smaller the corresponding parallel equivalent impedance. According to Ohm's law, the greater the current value of the AC current flowing through the entire path, the greater the current value. When the current exceeds a certain threshold, the signal detected by the detection port is judged as a strong signal, otherwise it is a weak signal.

In the actual application scenarios of electrical equipment in daily life, the wiring is long, and parasitic capacitance must exist in the entire wire. The longer the wire is, the greater the capacitance value of the parasitic capacitance will be. In the case of AC power supply, even if there is no load, the AC signal can be output to the detection port through the parasitic capacitance, resulting in misconduction. At this time, the detection port collects the wrong signal, which interferes with the normal load detection process.

Utility Model Content

The purpose of the present application includes, for example, providing an interference-resistant load detection circuit, which can reduce the interference of parasitic capacitance on the load detection process.

This application can be implemented as follows:

The present application provides an anti-interference load detection circuit, wherein the anti-interference load detection circuit has a parasitic capacitor, and the anti-interference load detection circuit includes:

a first diode, wherein the positive electrode of the first diode is connected to the live wire, the negative electrode of the first diode is connected to one end of the parasitic capacitor, and the negative electrode of the first diode is used to connect to the input end of the load;

A second diode, wherein the anode of the second diode is connected to the other end of the parasitic capacitor, and the anode of the second diode is used to connect to the output end of the load, and the cathode of the second diode is connected to the neutral line and the detection port.

Optionally, the anti-interference load detection circuit includes a first current limiting resistor, one end of the first current limiting resistor is connected to the live wire, and the other end of the first current limiting resistor is connected to the positive electrode of the first diode.

Optionally, the anti-interference load detection circuit includes a second current limiting resistor, one end of the second current limiting resistor is connected to the cathode of the first diode, and the other end of the second current limiting resistor is connected to the neutral line and the detection port.

Optionally, the anti-interference load detection circuit includes a third diode, the anode of the third diode is connected to one end of the second current limiting resistor, and the cathode of the third diode is connected to the detection port.

Optionally, the anti-interference load detection circuit includes a voltage-dividing resistor, one end of the voltage-dividing resistor is connected to the anode of the third diode, and the other end of the voltage-dividing resistor is connected to the neutral line.

Optionally, the anti-interference load detection circuit includes a first filter capacitor, and two ends of the first filter capacitor are respectively connected to two ends of the voltage-dividing resistor.

Optionally, the anti-interference load detection circuit includes a second filter capacitor, one end of the second filter capacitor is connected to the cathode of the third diode, and the other end of the second filter capacitor is connected to the neutral line.

Optionally, the anti-interference load detection circuit includes a peak detection circuit, an input end of the peak detection circuit is connected to the cathode of the third diode, and an output end of the peak detection circuit is connected to the neutral line.

Optionally, the peak detection circuit includes an energy storage capacitor and a detection resistor, the positive electrode of the energy storage capacitor is connected to the negative electrode of the third diode, the negative electrode of the energy storage capacitor is connected to the neutral line, and the detection resistor is connected in parallel with the energy storage capacitor.

Optionally, the resistance of the detection resistor is 100-1000KΩ.

The beneficial effects of the anti-interference load detection circuit of the present application include, for example: in order to reduce the interference of parasitic capacitance on the load detection process, an anti-interference load detection circuit is designed, the load detection circuit has parasitic capacitance, the load detection circuit includes a first diode and a second diode, the positive electrode of the first diode is connected to the live wire, the negative electrode of the first diode is connected to one end of the parasitic capacitance, and the negative electrode of the first diode is used to connect the input end of the load; the positive electrode of the second diode is connected to the other end of the parasitic capacitance, and the positive electrode of the second diode is used to connect the output end of the load, the negative electrode of the second diode is connected to the neutral line and the detection port, in the process of load detection, the input end and the output end of the load are respectively connected to the negative electrode of the first diode and the positive electrode of the second diode, due to the unidirectional conduction of the first diode and the second diode, the reverse current of the alternating current is intercepted by the first diode and the second diode, so that the parasitic capacitance is not easy to conduct, thereby reducing the interference of the parasitic capacitance on the load detection process and improving the anti-interference ability of the circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

FIG. 1 is a schematic diagram of an anti-interference load detection circuit in an embodiment of the present application.

Icon: VD1-first diode; VD2-second diode; VD3-third diode; C0-parasitic capacitor; C1-first filter capacitor; C2-second filter capacitor; C3-energy storage capacitor; R1-first current limiting resistor; R2-second current limiting resistor; R3-voltage dividing resistor; R4-detection resistor.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

In the description of the present application, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, it is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the utility model product is usually placed when used. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.

The inventor of the present application has found that parasitic capacitance must exist at the wires with longer wiring, and the longer the wire is, the greater the capacitance value of the parasitic capacitance exists. In the case of mains power supply, even if there is no load, the AC signal can be output to the detection port through the parasitic capacitance, resulting in misconnection. At this time, the detection port collects an erroneous signal, which interferes with the normal load detection process. The embodiment of the present application provides an anti-interference load detection circuit, which can reduce the interference of parasitic capacitance on the load detection process.

Please refer to Figure 1. The anti-interference load detection circuit provided in the embodiment of the present application has a parasitic capacitor C0. The anti-interference load detection circuit includes a first diode VD1 and a second diode VD2. The positive electrode of the first diode VD1 is connected to the live wire, the negative electrode of the first diode VD1 is connected to one end of the parasitic capacitor C0, and the negative electrode of the first diode VD1 is used to connect to the input end of the load; the positive electrode of the second diode VD2 is connected to the other end of the parasitic capacitor C0, and the positive electrode of the second diode VD2 is used to connect to the output end of the load, and the negative electrode of the second diode VD2 is connected to the neutral line and the detection port.

It should be noted that the meaning of parasitic capacitance is that there is no originally designed capacitance, but because there is always mutual capacitance between the wirings, the mutual capacitance is like parasitic between the wirings, so it is called parasitic capacitance, also known as stray capacitance.

When the load is connected to the load detection circuit, the input end of the load, the cathode of the first diode VD1, and one end of the parasitic capacitor C0 are connected to each other, and the output end of the load, the anode of the second diode VD2, and the other end of the parasitic capacitor C0 are connected to each other.

During the load detection process, the input end of the load is connected to the cathode of the first diode VD1, and the output end of the load is connected to the anode of the second diode VD2. At this time, one end of the parasitic capacitor C0 is connected to the cathode of the first diode VD1, and the other end of the parasitic capacitor C0 is connected to the anode of the second diode VD2. Due to the unidirectional conduction of the first diode VD1 and the second diode VD2, the reverse current of the alternating current is intercepted by the first diode VD1 and the second diode VD2, making it difficult for the parasitic capacitor C0 to conduct. Therefore, the interference of the parasitic capacitor C0 on the load detection process is reduced, and the anti-interference ability of the circuit is improved.

In this embodiment, the anti-interference load detection circuit includes a first current limiting resistor R1, one end of the first current limiting resistor R1 is connected to the live wire, and the other end of the first current limiting resistor R1 is connected to the positive electrode of the first diode VD1.

A first current limiting resistor R1 is provided in the load detection circuit. The first current limiting resistor R1 is located at the front end of the first diode VD1, so as to limit the current input from the live wire and protect the circuit. The resistance value of the first current limiting resistor R1 can be determined according to the actual working conditions.

The anti-interference load detection circuit also includes a second current limiting resistor R2, one end of the second current limiting resistor R2 is connected to the cathode of the first diode VD1, and the other end of the second current limiting resistor R2 is connected to the neutral line and the detection port.

A second current limiting resistor R2 is provided in the load detection circuit. The second current limiting resistor R2 is located at the rear end of the second diode VD2 to further limit the current passing through the load and protect the circuit. The resistance value of the second current limiting resistor R2 can be determined according to actual working conditions.

The anti-interference load detection circuit includes a third diode VD3, the anode of the third diode VD3 is connected to one end of the second current limiting resistor R2, and the cathode of the third diode VD3 is connected to the detection port. The third diode VD3 is arranged at the rear end of the second current limiting resistor R2 to prevent the current from conducting in the reverse direction.

In this embodiment, the anti-interference load detection circuit includes a voltage-dividing resistor R3 , one end of the voltage-dividing resistor R3 is connected to the anode of the third diode VD3 , and the other end of the voltage-dividing resistor R3 is connected to the neutral line.

One end of the second current limiting resistor R2, the positive electrode of the third diode VD3, and one end of the voltage dividing resistor R3 are connected to each other, and the other end of the voltage dividing resistor R3 is connected to the neutral line. The voltage dividing resistor R3 plays a voltage dividing role for the entire circuit. The actual signal detected by the detection port is a voltage signal. The voltage signal takes the voltage value across the voltage dividing resistor R3. The greater the current passing through the load, the greater the voltage value across the voltage dividing resistor R3, and the stronger the voltage signal detected by the detection port.

The anti-interference load detection circuit includes a first filter capacitor C1 , and two ends of the first filter capacitor C1 are respectively connected to two ends of a voltage-dividing resistor R3 .

In fact, the first filter capacitor C1 is connected in parallel with the voltage-dividing resistor R3 to filter out high-frequency noise and enhance the anti-interference capability of the circuit.

The anti-interference load detection circuit includes a second filter capacitor C2, one end of the second filter capacitor C2 is connected to the cathode of the third diode VD3, and the other end of the second filter capacitor C2 is connected to the neutral line.

In fact, similar to the first filter capacitor C1, the second filter capacitor C2 can also filter out high-frequency noise and improve the anti-interference ability of the circuit.

In this embodiment, the anti-interference load detection circuit includes a peak detection circuit, an input end of the peak detection circuit is connected to the cathode of the third diode VD3, and an output end of the peak detection circuit is connected to the neutral line.

It should be noted that the peak detection circuit is a circuit that can detect the peak value of an AC signal. The input of the peak detection circuit is the signal to be detected, and the output is a stable voltage (the peak value of the AC signal) under ideal conditions, which is displayed as a horizontal straight line on an oscilloscope; by collecting the output voltage of the peak detection circuit, the voltage peak value of the input signal can be obtained.

In this embodiment, the peak detection circuit includes a storage capacitor C3 and a detection resistor R4, the positive electrode of the storage capacitor C3 is connected to the negative electrode of the third diode VD3, the negative electrode of the storage capacitor C3 is connected to the neutral line, and the detection resistor R4 is connected in parallel with the storage capacitor C3.

The peak detection circuit formed by the energy storage capacitor C3 and the detection resistor R4 can achieve the effect of fast charging and slow discharging, so that the detection port can perform peak detection.

In this embodiment, the resistance of the detection resistor R4 is 100-1000KΩ. Exemplarily, the resistance of the detection resistor R4 is 100KΩ, 200KΩ, 500KΩ, 800KΩ or 1000KΩ.

The detection resistor R4 is connected in parallel with the energy storage capacitor C3. Since the resistance of the detection resistor R4 is relatively large, the voltage across the detection resistor R4 is relatively large during the charging process, so that the energy storage capacitor C3 is charged faster. During the discharging process, the energy storage capacitor C3 is discharged through the detection resistor R4. Since the resistance of the detection resistor R4 is relatively large, the discharge time is relatively long, and the purpose of peak detection is achieved. The use of peak detection can make the peak value change of the sampled voltage signal smaller and the detection signal more stable.

In summary, the embodiment of the present application provides an anti-interference load detection circuit. During the load detection process, the input end of the load is connected to the cathode of the first diode VD1, and the output end of the load is connected to the anode of the second diode VD2. At this time, one end of the parasitic capacitor C0 is connected to the cathode of the first diode VD1, and the other end of the parasitic capacitor C0 is connected to the anode of the second diode VD2. Due to the unidirectional conduction of the first diode VD1 and the second diode VD2, the reverse current of the alternating current is intercepted by the first diode VD1 and the second diode VD2, so that The parasitic capacitor C0 is not easy to conduct, which reduces the interference of the parasitic capacitor C0 on the load detection process. In addition, the first current limiting resistor R1 and the second current limiting resistor R2 are designed in the circuit to limit the current in the circuit; and the first filter capacitor C1 and the second filter capacitor C2 are also designed to filter out high-frequency noise and improve the anti-interference ability of the circuit; and the energy storage capacitor C3 and the detection resistor R4 are also designed to form a peak detection circuit to achieve the purpose of peak detection. The use of peak detection can make the peak value change of the sampled voltage signal smaller and the detection signal more stable.

The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims (10)

1. An anti-interference load detection circuit, wherein the anti-interference load detection circuit has a parasitic capacitor, and wherein the anti-interference load detection circuit comprises: a first diode, wherein the positive electrode of the first diode is connected to the live wire, the negative electrode of the first diode is connected to one end of the parasitic capacitor, and the negative electrode of the first diode is used to connect to the input end of the load; A second diode, wherein the anode of the second diode is connected to the other end of the parasitic capacitor, and the anode of the second diode is used to connect to the output end of the load, and the cathode of the second diode is connected to the neutral line and the detection port. 2. The anti-interference load detection circuit according to claim 1 is characterized in that the anti-interference load detection circuit includes a first current limiting resistor, one end of the first current limiting resistor is connected to the live wire, and the other end of the first current limiting resistor is connected to the positive electrode of the first diode. 3. The anti-interference load detection circuit according to claim 1 is characterized in that the anti-interference load detection circuit includes a second current limiting resistor, one end of the second current limiting resistor is connected to the cathode of the first diode, and the other end of the second current limiting resistor is connected to the neutral line and the detection port. 4. The anti-interference load detection circuit according to claim 3 is characterized in that the anti-interference load detection circuit includes a third diode, the anode of the third diode is connected to one end of the second current limiting resistor, and the cathode of the third diode is connected to the detection port. 5. The anti-interference load detection circuit according to claim 4 is characterized in that the anti-interference load detection circuit includes a voltage-dividing resistor, one end of the voltage-dividing resistor is connected to the positive electrode of the third diode, and the other end of the voltage-dividing resistor is connected to the neutral line. 6 . The anti-interference load detection circuit according to claim 5 , characterized in that the anti-interference load detection circuit comprises a first filter capacitor, and two ends of the first filter capacitor are respectively connected to two ends of the voltage-dividing resistor. 7. The anti-interference load detection circuit according to claim 5 is characterized in that the anti-interference load detection circuit includes a second filter capacitor, one end of the second filter capacitor is connected to the cathode of the third diode, and the other end of the second filter capacitor is connected to the neutral line. 8. The anti-interference load detection circuit according to claim 4 is characterized in that the anti-interference load detection circuit includes a peak detection circuit, the input end of the peak detection circuit is connected to the cathode of the third diode, and the output end of the peak detection circuit is connected to the neutral line. 9. The anti-interference load detection circuit according to claim 8 is characterized in that the peak detection circuit includes an energy storage capacitor and a detection resistor, the positive electrode of the energy storage capacitor is connected to the negative electrode of the third diode, the negative electrode of the energy storage capacitor is connected to the neutral line, and the detection resistor is connected in parallel with the energy storage capacitor. 10 . The anti-interference load detection circuit according to claim 9 , wherein the resistance of the detection resistor is 100-1000 KΩ.