CN221841639U - Integrated circuit system - Google Patents

Abstract

The present disclosure relates to integrated circuit systems. A memory circuit includes an address port, a data input port, and a data output port. The upstream shadow logic circuit is coupled to provide address data to an address port of the memory circuit and to provide input data to a data input port of the memory circuit. The downstream shadow logic circuit is coupled to receive output data from the data output port of the memory circuit. The memory circuit includes a bypass path between an address port and a data output port. This bypass path is activated during a test operation to pass bits of address data (forming test data) applied by the upstream shadow logic circuit from the address port to the data output port.

Description

Integrated Circuit System

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. Provisional Patent Application No. 63/411,683, filed on September 30, 2022, the disclosure of which is incorporated herein by reference.

Technical Field

Embodiments herein relate to testing integrated circuits, and in particular to testing integrated circuits including shadow logic and multi-port and multi-clock memories for at-speed switching faults.

Background Art

Complex integrated circuits include a combination of non-logic circuits (such as memory circuits, analog circuits) surrounded by digital logic circuits. Testing of integrated circuits is a requirement. It is known in the art to use built-in self-test (BIST) mechanisms to achieve the purpose of testing non-logic circuits. For example, BIST testing is commonly used for memory testing. However, BIST is not well suited to provide test coverage for surrounding digital logic circuits (often referred to as shadow logic in the art). Scan chain test mechanisms can be used to test digital logic circuits separately. However, testing of digital logic circuits surrounding programmable non-logic circuits remains a challenge, especially in the context of performing full-speed conversion fault testing and in the case where programmable non-logic circuits operate asynchronously in read and write modes.

Summary of the invention

In an embodiment, an integrated circuit system includes: a memory circuit having a memory array, a control circuit coupled to an address port, and an input/output circuit coupled to a data input port and a data output port. The control circuit includes an address register configured to latch a read address in response to a read clock. Each input/output circuit includes: a first data path controlled by a write clock and coupling a data input of a data input port to a write bit line of the memory array; and a second data path controlled by a read clock and coupling a read bit line of the memory array to a data output of a data output port. The second data path in each input/output circuit includes a multiplexer circuit having a first input coupled to the read bit line, a second input coupled to a bypass path, and an output coupled to the data output. A test bit is applied to a second input of the multiplexer in each input/output circuit in response to the read clock. The multiplexer is controlled to select the second input during a test operation.

In an embodiment, an integrated circuit system includes: a memory circuit having a memory array, a control circuit coupled to an address port, and an input/output circuit coupled to a data input port and a data output port. The control circuit includes an address register configured to latch a read address in response to a read clock. Each input/output circuit includes: a first data path controlled by a write clock and coupling a data input of the data input port to a write bit line of the memory array; and a second data path controlled by a read clock and coupling a read bit line of the memory array to a data output of the data output port. The second data path in each input/output circuit includes a multiplexer circuit having a first input coupled to the read bit line, a second input coupled to a bypass path, and an output coupled to the data output. The address bit of the read address latched in the address register is applied to the second input of the multiplexer in each input/output circuit. The multiplexer is controlled to select the second input during a test operation.

In an embodiment, an integrated circuit system includes: a memory circuit, an address port, a data input port, and a data output port; an upstream shadow logic circuit coupled to provide address data to the address port of the memory circuit and to provide input data to the data input port of the memory circuit; and a downstream shadow logic circuit coupled to receive output data from the data output port of the memory circuit. The memory circuit includes a bypass path between the address port and the data output port, wherein the bypass path is active during a test operation to pass bits of address data applied by the upstream shadow logic circuit from the address port to the data output port.

According to one aspect of the present disclosure, an integrated circuit system is provided, comprising: a memory circuit having: a memory array, a control circuit coupled to an address port, and an input/output circuit coupled to a data input port and a data output port; wherein the control circuit comprises an address register, which latches a read address in response to a read clock; wherein each input/output circuit comprises: a first data path and a second data path, the first data path being controlled by a write clock and coupling a data input end of the data input port to a write bit line of the memory array, and the second data path being controlled by a read clock and coupling a read bit line of the memory array to a data output end of the data output port; wherein the second data path in each input/output circuit comprises a multiplexer circuit having a first input end coupled to the read bit line, a second input end coupled to a bypass path, and an output end coupled to the data output end; wherein a test bit is applied to the second input end of the multiplexer in each input/output circuit in response to the read clock; and wherein the multiplexer is controlled to select the second input end during a test operation.

According to one or more embodiments, a memory array of a memory circuit includes memory cells having separate read and write ports.

According to one or more embodiments, the second data path in each input/output circuit includes a latch circuit that latches data from a read bit line of the memory array in response to a read clock.

According to one or more embodiments, wherein the test bits are address bits of a read address latched in an address register in response to a read clock.

According to one or more embodiments, the bypass path includes a delay circuit that delays application of address bits of the read address to the second input of the multiplexer in each input/output circuit by a delay time.

According to one or more embodiments, the delay time is set so that the timing of the test signal propagating from the register through the bypass path and the second input terminal of the multiplexer to the data output terminal is equal to the timing of the memory access reading from the memory array through the second data path.

According to one or more embodiments, the integrated circuit system further includes shadow logic upstream of the address port, wherein the shadow logic provides a read address during a test operation.

According to one or more embodiments, the integrated circuit system further includes a scan register for a test operation coupled to the shadow logic upstream of the data input port.

According to one or more embodiments, the integrated circuit system further includes a built-in self-test circuit that supplies a read address during a test operation.

According to one or more embodiments, the built-in self-test circuit is further coupled to the data output port.

According to one or more embodiments, the integrated circuit system further includes shadow logic downstream of the data output port.

According to one or more embodiments, the integrated circuit system further includes a scan register for a test operation coupled to the shadow logic downstream of the data output port.

According to one or more embodiments, the integrated circuit system further includes a shadow logic upstream of the data input port.

According to one or more embodiments, the integrated circuit system further includes a scan register for a test operation coupled to the shadow logic upstream of the data input port.

According to one or more embodiments, the read clock is asynchronous to the write clock.

According to one or more embodiments, the read clock and the write clock have different frequencies.

According to one or more embodiments, wherein the memory array is divided into a plurality of sub-arrays, each sub-array includes a local read bit line, and wherein each input/output circuit includes read logic having an input terminal coupled to the local read bit lines from the plurality of sub-arrays and an output terminal coupled to the second data path.

According to one or more embodiments, each input/output circuit further comprises a plurality of additional data paths, each of the additional data paths coupling one of the plurality of local read bit lines to a corresponding one of the plurality of read data output terminals of the data output port.

According to one or more embodiments, wherein the test bits are address bits of a read address latched in an address register in response to a read clock; wherein each additional data path in each input/output circuit includes an additional multiplexer circuit having a first input coupled to a local read bit line, a second input coupled to a bypass path, and an output coupled to a read data output; wherein the address bits of the read address latched in the address register are applied to the second input of the additional multiplexer in each input/output circuit; and wherein the additional multiplexer is controlled to select the second input during a test operation.

According to one or more embodiments, the second data path in each input/output circuit includes a latch circuit that latches data from a read bit line of the memory array in response to a read clock.

According to one or more embodiments, the bypass path includes a delay circuit that delays application of address bits of the read address to the second input of the further multiplexer in each input/output circuit by a delay time.

According to one or more embodiments, the delay time is set so that the timing of the test signal propagating from the register through the bypass path and the second input terminal of the further multiplexer to the read data output terminal is equal to the timing of the memory access reading from the memory array through the second data path.

According to one or more embodiments, the integrated circuit system further includes shadow logic downstream of the data output port.

According to one or more embodiments, the integrated circuit system further includes a scan register for a test operation coupled to the shadow logic downstream of the data output port.

According to one or more embodiments, the integrated circuit system further includes a shadow logic upstream of the data input port.

According to one or more embodiments, the integrated circuit system further includes a scan register for a test operation coupled to the shadow logic upstream of the data input port.

According to one or more embodiments, the integrated circuit system further includes shadow logic upstream of the address port, wherein the shadow logic provides a read address during a test operation.

According to one or more embodiments, the integrated circuit system further includes a scan register for a test operation coupled to the shadow logic upstream of the data input port.

According to one or more embodiments, the integrated circuit system further includes a built-in self-test circuit that supplies a read address during a test operation.

According to one or more embodiments, the built-in self-test circuit is further coupled to the data output port.

According to one or more embodiments, the read clock is asynchronous to the write clock.

According to another aspect of the present disclosure, an integrated circuit system is provided, comprising: a memory circuit, an address port, a data input port and a data output port; an upstream shadow logic circuit coupled to provide address data to the address port of the memory circuit and to provide input data to the data input port of the memory circuit; and a downstream shadow logic circuit coupled to receive output data from the data output port of the memory circuit; wherein the memory circuit comprises a bypass path between the address port and the data output port, the bypass path being active during a test operation to pass bits of address data applied by the upstream shadow logic circuit from the address port to the data output port.

According to one or more embodiments, the bypass path includes a delay circuit that delays the transfer of bits of address data from the address port to the data output port.

According to one or more embodiments, wherein the delay time is set so that the timing of address bits propagating from the address port through the bypass path to the data output port is equal to the timing of memory access for reading data from the memory circuit for output at the data output port.

According to one or more embodiments, the integrated circuit system further includes a scan register coupled to the downstream shadow logic for a test operation.

According to one or more embodiments, the integrated circuit system further includes a scan register for a test operation coupled to the upstream shadow logic.

According to one or more embodiments, a memory circuit includes a memory array having a read bit line coupled to a data output port through a read path.

According to one or more embodiments, the read path includes: a latch circuit that latches data from a read bit line of a memory array in response to a read clock; and a multiplexer circuit having a first input coupled to an output of the latch circuit, a second input coupled to a bypass path, and an output coupled to a data output port; and wherein the multiplexer is controlled to select the second input during a test operation.

According to one or more embodiments, a memory circuit includes a memory array divided into a plurality of sub-arrays, each sub-array including a local read bit line coupled to a data output portion through a read path.

According to one or more embodiments, each read path includes: a latch circuit that latches data from a local read bit line of a memory array in response to a read clock; and a multiplexer circuit having a first input coupled to an output of the latch circuit, a second input coupled to a bypass path, and an output coupled to a data output port; and wherein the multiplexer is controlled to select the second input during a test operation.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

FIG1 is a block diagram of an integrated circuit system including a memory circuit;

FIG2 is a block diagram of an input/output (I/O) circuit for the memory circuit of FIG1;

FIG3 is a block diagram of a memory circuit;

FIG4 is a circuit diagram of a standard 8T static random access memory (SRAM) cell used in the memory array shown in FIG3 ;

FIG5 is a block diagram of an I/O circuit for the memory circuit of FIG3;

FIG6 illustrates the connection of the I/O circuit shown in FIG5 in a scan chain configuration for supporting test operations;

FIG7 is a block diagram of a memory circuit;

FIG8 is a block diagram of another embodiment of an I/O circuit for the memory circuit of FIG7;

FIG9 is a block diagram of a memory circuit;

FIG10 is a block diagram of another embodiment of an I/O circuit for the memory circuit of FIG9;

FIG11 is a schematic diagram of a memory circuit; and

12 is a block diagram of an embodiment of an I/O circuit for the memory circuit of FIG. 11 .

DETAILED DESCRIPTION

Referring to FIG. 1 , there is shown a block diagram of an integrated circuit system 10 that includes a memory circuit 12, which is shown here by way of example in the form of a random access memory (RAM), surrounded by an upstream (or input) shadow logic 14 and a downstream (or output) shadow logic 16. A memory built-in self-test (BIST) circuit 18 is provided to test the memory circuit 12 (note that the testing of the shadow logics 14, 16 is not performed by the BIST circuit 18). The upstream shadow logic 14 is configured to provide a multi-bit data input 20 to a data input port (data_in) of the memory circuit 12 through a first input of a multiplexer 22. The BIST circuit 18 is configured to provide a multi-bit BIST data input 24 to a data input port (data_in) of the memory circuit 12 through a second input of the multiplexer 22. The upstream shadow logic 14 is also configured to provide a multi-bit address input 26 to an address port (addr_in) of the memory circuit 12 through a first input of a multiplexer 28. The BIST circuit 18 is also configured to provide a multi-bit BIST address input 30 to an address port (addr_in) of the memory circuit 12 through a second input of the multiplexer 28. At a data output port (data_out) of the memory circuit 12, a multi-bit data output 32 is provided to the downstream shadow logic 16 through a first input of a multiplexer 34. The multi-bit data output 32 is also applied to the BIST circuit 18 as feedback. The multi-bit data input 20 from the upstream shadow logic 14 is further applied to the downstream shadow logic 16 through a second input of the multiplexer 34 through a memory bypass 36. An input scan chain register 40 may provide test data 42 to be applied to the upstream shadow logic 14. Test data 46 generated by the downstream shadow logic 16 is received by an output scan chain register 44.

As described above, BIST testing using the BIST circuit 18 is specific to providing testing of the memory circuit 12. Testing of the upstream shadow logic 14 and the downstream shadow logic 16 surrounding the memory circuit 12 is performed using automatic test pattern generation (ATPG) circuitry (not explicitly shown) that loads test data inputs to the input scan chain registers 40 and extracts test data outputs from the output scan chain registers 44. To avoid the complexity of accessing the memory 12 during ATPG-controlled logic testing, the memory bypass 36 is enabled by assertion of the test bypass control signal (Tbypass) to allow the multi-bit data input 20 from the upstream shadow logic 14 to bypass (bypass) the memory circuit 12 and be applied to the downstream shadow logic 16 through the second input of the multiplexer 34.

Multiplexer 34 and memory bypass 36 may alternatively be implemented as part of an input/output (I/O) circuit between a data input port (data_in) and a data output port (data_out) of memory circuit 12. An example of this is shown in FIG. 2 (see multiplexer 34' and bypass path 36'). I/O circuit 50 includes a data input terminal D (as part of memory data input port data_in) and a data output terminal Q (as part of memory data output port data_out). A data output latch 52, for example formed by a flip-flop (FF), is coupled to a memory array of memory circuit 12 to receive data bits read from the memory array by a read logic circuit system via a bit line BL. Data output latch 52 is controlled by a clock signal CLK. The output from data output latch 52 is applied to a first input terminal of multiplexer 34', and the output terminal of multiplexer 34' is coupled to data output terminal Q of I/O circuit 50. The data input latch 54 is coupled to receive the data bit input to the memory circuit 12 at the data input terminal D. The data input latch 54 is controlled by the clock signal CLK. The output from the data input latch 54 is applied by the write logic circuit system to write the data into the memory array through the bit line BL. The output from the data input latch 54 is also applied to the second input terminal of the multiplexer 34' through the bypass path 36', and the output terminal of the multiplexer 34' is coupled to the data output terminal Q of the I/O circuit 50. The select input terminal of the multiplexer 34' receives the test bypass (Tbypass) control signal 56. When the test bypass control signal 56 is asserted (e.g., logic high), the multiplexer 34' selects the data at the second input terminal of the multiplexer 34' to output to the data output terminal Q of the I/O circuit 50.

In a memory bypass operation, data bits input to the memory circuit 12 at the data input terminal D are passed through the bypass path 36' for output from the memory circuit at the data output terminal Q to enable stuck-at fault test coverage for the shadow logic. In addition, the timing of the data transfer from the data input terminal D to the data output terminal Q through the bypass path 36' can be controlled by a self-time delay that matches the normal memory access time delay (for memory array read/write operations) to enable transient fault test coverage.

It will be noted that in this example, the memory array is coupled to the I/O circuit 50 via bit lines BL comprising complementary bit line pairs, wherein the array is formed of memory bit cells of a single-port type. Such testing operations become more complicated where the bit cells of the memory circuit are instead multi-port cells (i.e., having separate read and write ports) and the memory circuit supports different clocks for read and write timing operations on different read/write ports.

Referring now to FIG. 3 , there is shown a block diagram of a memory circuit 110 including a static random access memory (SRAM) array 112 formed of a plurality of SRAM memory cells 114 arranged in a matrix format having N rows and M columns. Each SRAM memory cell is of the well-known dual-port (one read, one write) 8T type (see FIG. 4 ) and includes a write word line WWL, a pair of complementary (write) bit lines BLT and BLC, a read word line RWL, and a read bit line RBL. The SRAM memory cells in a common row of the matrix are connected to each other by a common write word line WWL and by a common read word line RWL. During read and write operations, each word line (WWL and/or RWL) is driven by a word line driver circuit 116 with a word line signal generated by a row decoder circuit 118. The SRAM memory cells in a common column of the matrix across the entire array 112 are connected to each other through a common complementary bit line pair BLT and BLC (corresponding to the write port of each memory cell 114) and through a common read bit line RBL (corresponding to the read port of each memory cell 114). Each of the bit lines (BLT, BLC, and RBL) is coupled to a column input/output (I/O) circuit 120. The data input port (D) of the column I/O circuit 120 (provided as part of the memory data input port data_in) receives input data to be written to the SRAM memory cells 114 in the column through the bit lines BLT, BLC in response to the assertion of the write word line signal timed by the write clock WCK signal. The data output port (Q) of the column I/O circuit 120 (provided as part of the memory data output port data_out) generates output data read from the SRAM memory cells 114 in the column through the read bit line RBL in response to the assertion of the read word line signal timed by the read clock RCK signal. The control circuit 200 controls the operation of the circuit system within the memory. It will be noted that the clock signals WCK and RCK may be asynchronous clocks.Thus, in this configuration, the memory circuit 110 may be referred to as a multi-port (ie, dual port: one read, one write) and multi-clock (read and write) type memory.

Referring now to FIG. 4 , each memory cell 114 includes two cross-coupled CMOS inverters 122 and 124, each inverter including a pair of p-channel and n-channel MOSFET transistors connected in series. The input and output of the inverters 122 and 124 are coupled to form a latch circuit having a true data storage node QT and a complementary data storage node QC, which stores the complementary logic states of the stored data bits. The cell 114 also includes two transmission (transfer gate) transistors 126 and 128, whose gate terminals are driven by the word line WL. The source-drain path of transistor 126 is connected between the true data storage node QT and a node associated with the true bit line BLT. The source-drain path of transistor 128 is connected between the complementary data storage node QC and a node associated with the complementary bit line BLC. The source terminals of p-channel transistors 130 and 132 in each inverter 122 and 124 are coupled to receive a high supply voltage (e.g., Vdd) at a high supply node, while the source terminals of n-channel transistors 134 and 136 in each inverter 122 and 124 are coupled to receive a low supply voltage (e.g., ground (Gnd) reference) at a low supply node. A signal path between the read bit line RBL and the low supply voltage reference is formed by transistors 138 and 140 coupled in series. The gate terminal of (read) transistor 138 is coupled to a complementary storage node QC, and the gate terminal of (pass) transistor 140 is coupled to receive a signal on a read word line RWL. The word line driver circuit 116 is also typically coupled to receive a high supply voltage (Vdd) at a high supply node and referenced to a low supply voltage (Gnd) at a low supply node.

The memory circuit 110 may be used, for example, as the memory circuit 12 in the system 10 shown in FIG. 1 . To support integrated circuit test operations, the input/output (I/O) circuit 120 of the memory circuit 110 may have a circuit configuration such as that shown in FIG. 5 , where M I/O circuits 120 (0) to 120 (M-1) are connected in a scan chain configuration as shown in FIG. 6 . Each I/O circuit 120 includes a data input terminal D (as part of a memory data input port data_in) and a data output terminal Q (as part of a memory data output port data_out). A data output latch 152, for example formed by a flip-flop (FF), is coupled to a memory array of the memory circuit 110 (via a column read bit line RBL) through a first input terminal of a multiplexer 153 to receive data bits read from the memory array by a read logic circuit system. The data output latch 152 is controlled by a read clock signal RCK. The output from the data output latch 152 is coupled to a data output terminal Q of the I/O circuit 120. The data input latch 154 is coupled to receive the data bit input to the memory circuit 110 at the data input terminal D. The data input latch 154 is controlled by the write clock signal WCK. The output from the data input latch 154 is applied by the write logic circuit system to write the data into the memory array (via the column complementary write bit lines BLT, BLC). Each I/O circuit 120 also includes a test input terminal T coupled to receive the test data bit (for example, provided as part of the memory data input port data_in). The test data latch 158 is coupled to receive the test data bit from the test input terminal T. The test data latch 158 is controlled by the read clock signal RCK. The output of the test data latch 158 is coupled to the second input terminal of the multiplexer 153, and the output terminal of the multiplexer 153 is coupled to the data output terminal Q of the I/O circuit 120. The select input terminal of the multiplexer 153 receives the test mode (Tmode) control signal 156. When the test mode control signal 156 is asserted (eg, logic high), the multiplexer 153 selects data at the second input terminal of the multiplexer 153 (as received from the test input terminal T) for output to the data output terminal Q.

For the scan chain configuration of FIG6 , the test input terminal T of the first I/O circuit 120 receives a test data input signal. In the context of the circuit implementation of FIG1 , the test data may be applied to the test input terminal T of the first I/O circuit 120 of the memory circuit from the upstream shadow logic 14 or from the input scan chain register 40 or from the BIST circuit 18. The data output terminal Q of the I/O circuit 120(0) is coupled to the test input terminal T of the second I/O circuit 120(1). This connection configuration providing the scan chain is repeated on the M I/O circuits 120, where the test input terminal T of the last I/O circuit 120(M-1) is coupled to the data output terminal Q of the second to last I/O circuit 120(M-2).

The disadvantage of the aforementioned test scheme is that additional test-related circuitry needs to be provided in each I/O circuit 120. In addition, this solution does not support full-speed testing of shadow logic surrounding the memory. This solution is not satisfactory for providing testing of multi-port and multi-clock memories associated with detecting full-speed switching failures.

Referring now to Figure 7, a block diagram of memory circuit 210 is shown. Like reference numbers in Figures 3 and 7 refer to the same or similar components. Memory circuit 210 may be used, for example, as memory circuit 12 in system 10 shown in Figure 1 .

The memory circuit 210 differs from the memory circuit 110 mainly in the configuration of the I/O circuit 220 as shown in FIG8 . Each I/O circuit 220 includes a data input terminal D (as part of the memory data input port data_in) and a data output terminal Q (as part of the memory data output port data_out). A data output latch 152 formed, for example, by a flip-flop (FF) is coupled to the memory array of the memory circuit 210 to receive data bits read from the memory array by the read logic circuit system through the read bit line RBL. The data output latch 152 is controlled by a read clock signal RCK. The output from the data output latch 152 is applied to a first input terminal of a multiplexer 34 ', and the output terminal of the multiplexer 34 ' is coupled to the data output terminal Q of the I/O circuit 220. The data input latch 154 is coupled to receive the data bit input to the memory circuit 210 at the data input terminal D. The data input latch 154 is controlled by a write clock signal WCK. The output from the data input latch 154 is applied through the write logic circuit system to write data into the memory array through the complementary write bit lines BLT, BLC. The output from the data input latch 154 is also applied to the second input of the multiplexer 34' through the bypass path 36', and the output of the multiplexer 34' is coupled to the data output terminal Q of the I/O circuit 220. The select input of the multiplexer 34' receives the test bypass (Tbypass) control signal 56. When the test bypass control signal 56 is asserted (e.g., logic high), the multiplexer 34' selects the data at the second input of the multiplexer 34' (from the latch 154 and the bypass path 36') to be output to the data output terminal Q.

Advantageously, this test solution supports fixed fault test coverage for memory and shadow logic. However, transient test coverage is not well supported. The reason is that the test path from the second input of the data input latch 154, the bypass path 36' and the multiplexer 34' to the data output terminal Q depends on the write clock signal WCK during the test mode selection. However, the test output signal from the data output terminal Q is captured in the read clock RCK domain, and the difference in clock frequency and clock skew (note that WCK is asynchronous with RCK) hinders the performance of transient fault testing. The problem is that the timing of the test path from the second input of the data input latch 154 and the multiplexer 134 to the data output terminal Q (depending on the write clock WCK) cannot be made equal to the timing of the read signal path from the memory array through the read logic, latch 152, the first input of the multiplexer 34' to the data output terminal Q (depending on the read clock RCK).

Referring now to Figure 9, a block diagram of memory circuit 310 is shown. Like reference numbers in Figures 7 and 9 refer to the same or similar components. Memory circuit 310 may be used, for example, as memory circuit 12 in system 10 shown in Figure 1 .

The memory circuit 310 differs from the memory circuit 210 mainly in the configuration of the I/O circuit 320 as shown in FIG. 10. Each I/O circuit 320 includes a data input terminal D (as part of the memory data input port data_in) and a data output terminal Q (as part of the memory data output port data_out). A data output latch 152 formed, for example, by a flip-flop (FF) is coupled to the memory array of the memory circuit 310 to receive data bits read from the memory array by the read logic circuit system through the read bit line RBL. The data output latch 152 is controlled by the read clock signal RCK. The output from the data output latch 152 is applied to the first input terminal of the multiplexer 34', and the output terminal of the multiplexer 34' is coupled to the data output terminal Q of the I/O circuit 320. The data input latch 154 is coupled to receive the data bit input to the memory circuit 310 at the data input terminal D. The data input latch 154 is controlled by the write clock signal WCK. The output from the data input latch 154 is applied through the write logic circuit system to write data into the memory array through the complementary write bit lines BLT, BLC. The second input of the multiplexer 34' is coupled to receive the test data bit from the output of the delay circuit 304. The input of the delay circuit 304 is coupled to the bypass path 36". It will be noted here that in the context of Figure 1, the bypass path 36" is instead located between the address port (addr_in) of the memory circuit 12 and the memory data output port data_out.

The control circuit 200 of the memory circuit 310 includes a register 202, which is configured to latch a multi-bit read address (Read Address) applied to an address input terminal (addr_in) in response to a read clock signal RCK. The latched read address bits are output from the register 202 during a test operation and supplied to the I/O circuit 320 via a bypass path 36". Each read address has B bits, where B<<M. Using M I/O circuits 320(0) to 320(M-1), the B bits of the received and latched multi-bit read address are distributed to the I/O circuit 320 according to a pattern via a bypass path 36". As an example, M I/O circuits 320 are divided into M/B groups, and each group of B I/O circuits 320 receives corresponding B bits of a multi-bit read address (i.e., the B bits are supplied to corresponding B I/O circuits 320(0) to 320(B-1), to corresponding B I/O circuits 320(B) to 320(2B-1), ..., and to corresponding B I/O circuits 320(M-1-B) to 320(M-1)). At each I/O circuit 320, the delivered bits of the read address are applied to the input of the delay circuit 304, delayed by a delay time Δt (which may be unique in each I/O circuit or the same in multiple I/O circuits in the I/O circuits) and output to the second input of the multiplexer 34'. With the test bypass (Tbypass) control signal 56 asserted (e.g., logic high), the multiplexer 34' selects the delayed read address data bit at the second input of the multiplexer 34' to output to the data output Q of the I/O circuit 320. This delay time Δt may be controlled using a logic delay in each I/O circuit 320 or by an internal self-time delay.

In the context of the circuit implementation of FIG. 1 , the read address may be applied from the upstream shadow logic 14 to the address input (addr_in) of the memory circuit (as multi-bit address data 26) via a first input of the multiplexer 28. Alternatively, the read address may be applied from the BIST circuit 18 to the address input (addr_in) of the memory circuit (as multi-bit address data 30) via a second input of the multiplexer 28. The test output data from the data output Q of the I/O circuit 320 may be passed through to the downstream shadow logic 16 and/or applied to the BIST circuit 18 in a feedback form.

Advantageously, this test solution supports fixed fault test coverage for shadow logic. In addition, transient fault test coverage is also supported. It will be noted that the test path using the read address register 202 through the bypass path 36" and the second input of the multiplexer 34' to the data output terminal Q now depends on the read clock signal RCK (and the applied delay Δt) during the test mode selection. The test output signal from the data output terminal Q is also captured in the read clock RCK domain, so there are no differences in clock frequency and clock skew that would hinder the performance of transient fault testing. By setting the delay time Δt implemented by the delay circuit 304, the timing of the test path from the register 202 through the bypass path 36" and the second input of the multiplexer 34' to the data output terminal Q can be controlled to be equal to the timing of the memory access read path from the read logic through the latch 152 and the first input of the multiplexer 34' to the data output terminal Q.

Referring now to FIG. 11 , a block diagram of a memory circuit 410 is shown. The circuit 410 includes a static random access memory (SRAM) array 112 formed of a plurality of SRAM memory cells 114 arranged in a matrix format having N rows and M columns. Each SRAM memory cell is of the well-known 8T type (see FIG. 4 ) and includes a write word line WWL, a complementary bit line pair BLT and BLC, a read word line RWL, and a read bit line RBL. The SRAM memory cells in a common row of the matrix are connected to each other via a common write word line WWL and via a common read word line RWL. During read and write operations, each of the word lines (WL and/or RWL) is driven by a word line driver circuit 116 using a word line signal generated by a row decoder circuit 118. The SRAM memory cells in a common column of the matrix across the entire array 112 are connected to each other via a common complementary (write) bit line pair BLT and BLC. The array 112 is segmented into P sub-arrays 113 ₀ to 113 _P-1 . Each sub-array 113 includes M columns and N/P rows of memory cells 114. The SRAM memory cells in a common column of each sub-array 113 are connected to each other via local read bit lines RBL. P local read bit lines _RBL0 <x> through RBLP _-1 <x> of sub-array 113 from column x in array 112 are coupled to column input/output (I/O) circuitry 420 along with a common complementary bit line pair BLT<x> and BLC<x> for column x in array 112. A data input port (D) of column I/O circuitry 420 (provided as part of a memory data input port data_in) receives input data to be written to the SRAM memory cells 114 in the column via bit lines BLT, BLC in response to assertion of a write word line signal. The data output port (Q) of the column I/O circuit 420 (provided as part of the memory data output port data_out) generates output data read from the SRAM memory cells 114 in the column through the read bit lines RBL in response to the assertion of the read word line signal in the first read operation mode. In addition, the column I/O circuit 420 also includes P sub-array data output ports _R0 to R _P-1 to generate output data read from the memory cells 114 on the local read bit lines RBL of the corresponding sub-arrays 113 ₀ to 113 _P-1 respectively in response to the simultaneous assertion of multiple read word line signals (one for each sub-array 113) in the second read operation mode. The control circuit 200 controls the operation of the circuit system within the memory.

When the memory circuit 410 operates in the first read operation mode, the row decoder circuit 118 selectively actuates only one read word line RWL of the entire array 112 using a word line signal pulse to access a corresponding single row of the rows of memory cells 114. The logic state stored in a single accessed memory cell of a column is output to the read bit line RBL and input to the column I/O circuit 420 to be output at the data output port Q. In this first operation mode, the memory circuit 410 is configured to operate in the same manner as the memory circuit 310 of FIG. 9 .

When the memory circuit 410 operates in the second read operation mode, the row decoder circuit 118 selectively (and simultaneously) actuates one read word line RWL in each sub-array 113 in the memory array 112 using a word line signal pulse to access a corresponding single one of the rows of memory cells 114 in each sub-array 113. The logic state stored in the single accessed memory cell of the sub-array 113 of each column is output to the read bit lines RBL ₀ to RBL _P-1 and input to the column I/O circuit 420 for output at the corresponding sub-array data output ports R ₀ to R _P-1 .

For example, this second read operation mode can be implemented in conjunction with the operation of the memory to support the performance of in-memory computation (where, for example, the memory cell 114 stores bits of weight data and the word line signal pulses on the read word line convey the characteristic data). In this context, referring to FIG. 1 , the downstream (or output) shadow logic 16 can be configured to implement a multiply-accumulate (MAC) operation on the data output from the sub-array data output ports R ₀ to R _P-1 of each column I/O circuit 420 for the wide vector in-memory computation mode.

A block diagram of an embodiment for column I/O circuit 420 is shown in FIG. 12 . A data output latch 152, for example formed by a flip-flop (FF), is coupled to the memory array of memory circuit 410 in a first read operation mode to receive data bits read from the memory array by a read logic circuit system through read bit lines RBL ₀ to RBL _P-1 . Data output latch 152 is controlled by a read clock signal RCK. The output from data output latch 152 is applied to a first input of multiplexer 34 ', and the output of multiplexer 34 ' is coupled to a data output Q of I/O circuit 420. A data output latch 153 _y, for example formed by a flip-flop (FF), is coupled to the memory array of memory circuit 410 in a second read operation mode to receive data bits read from the memory array by a read logic circuit system through a corresponding one of read bit lines RBL _y . Here, y=0 to P-1. Data output latch 153 _y is controlled by a read clock signal RCK. The output from the data output latch 153 _y is applied to a first input of a multiplexer 135 _y , the output of which is coupled to a subarray data output port _{R y of} the I/O circuit 420. The data input latch 154 is coupled to receive data bits input to the memory circuit 110 at the data input terminal D. The data input latch 254 is controlled by a write clock signal WCK. The output from the data input latch 154 is applied through a write logic circuit system to write data into the memory array through complementary write bit lines BLT, BLC. The second inputs of the multiplexers 34', 135 _y are coupled to receive test data bits from the outputs of the delay circuits 304, 305y, respectively. The input of each delay circuit is coupled to a bypass path 36".

The control circuit 200 of the memory circuit 410 includes a register 202 configured to latch a multi-bit read address (Read Address) applied to an address input terminal (addr_in) in response to a read clock signal RCK. The latched bits of the read address are output from the register 202 during the test operation and supplied to the I/O circuits 420 through the bypass path 36″. Each read address has B bits, where B<<M. With M I/O circuits 420(0) to 420(M-1), the received and latched B bits of the multi-bit read address are distributed to the I/O circuits 420 through the bypass path 36′ according to a pattern. As an example, the M I/O circuits 420 are divided into M/B groups, and the I/O circuits 420 of each group receive the B bits of the multi-bit read address (i.e., the B bits are supplied to the B I/O circuits 420(0) to 420(B-1), to the B I/O circuits 420(B) to 420(2B-1), . . . , and to the B I/O circuits 420(M-2). -1-B) to 420(M-1)). At each I/O circuit 420, the delivered read address bit is applied to the input of the delay circuit 304, delayed by a delay time Δt (which may be unique in each I/O circuit, or the same in multiple I/O circuits in the I/O circuits), and output to the second input of the multiplexer 34'. With the assertion (e.g., logic high) of the test bypass (Tbypass) control signal 56, the multiplexer 34' selects the delayed read address data bit at the second input of the multiplexer 34' to output to the data output Q of the I/O circuit 420. This delay time Δt may be controlled using a logic delay in each I/O circuit 420 or by an internal self-time delay.

In the case of M I/O circuits 420(0) to 420(M-1) and each I/O circuit 420 including P sub-array data output ports R ₀ to R _P-1 , the B bits of the received and latched multi-bit read address are distributed to the I/O circuits 420 through the bypass path 36″ according to the pattern. As an example, the M I/O circuits 420 are divided into M/B groups, and the I/O circuits 420 of each group receive the B bits of the multi-bit read address (i.e., the B bits are supplied to the I/O circuits 420(0) to 420(B-1), to the I/O circuits 420(B) to 420(2B-1), ..., and to the I/O circuits 420(M-1-B) to 420(M-1)). At each I/O circuit 420, the delivered bits of the read address are applied to the P delay circuits 305. The input terminal of each of the multiplexers _{135 y} is delayed by a delay time Δt (which may be unique in each I/O circuit or the same in multiple I/O circuits in the I/O circuits) and output to the second input terminal of the multiplexer 135 _y . With the assertion (e.g., logic high) of the test bypass (Tbypass) control signal 56, the multiplexer 135 _y selects the delayed read address data bit at the second input terminal of the multiplexer 135 _y to output to the corresponding sub-array data output port R _y of the I/O circuit 420. This delay time Δt may be controlled using a logic delay in each I/O circuit 420 or by an internal self-time delay.

In the context of the circuit implementation of FIG. 1 , the read address may be applied from the upstream shadow logic 14 to the address input (addr_in) of the memory circuit (as multi-bit address data 26) via a first input of the multiplexer 28. Alternatively, the read address may be applied from the BIST circuit 18 to the address input (addr_in) of the memory circuit (as multi-bit address data 30) via a second input of the multiplexer 28. Test output data from the data output Q of the I/O circuit 420 and/or the sub-array data output port R _y may be passed through to the downstream shadow logic 16 and/or applied in feedback to the BIST circuit 18.

Advantageously, this test solution supports stuck-at fault test coverage for memory and shadow logic. In addition, transient fault test coverage is also supported. It will be noted that the test path from the second input of the multiplexer 135 _y to the data output R _y using the read address register 202 now depends on the read clock signal RCK (and the applied delay Δt) during the test mode selection. The test output signal from the data output R _y is also captured in the read clock RCK domain, so there are no differences in performance clock frequency and clock skew that would hinder transient fault testing. By setting the delay time Δt implemented by the delay circuit 305 _y , the timing of the test path from the register 202 through the bypass path 36 ″ and the second input of the multiplexer 135 _y to the sub-array data output port R _y can be controlled to be equal to the timing of the memory access read path from the read logic through the latch 153 _y and the first input of the multiplexer 135 _y to the sub-array data output port R _y .

The foregoing description has provided by way of exemplary and non-limiting examples a complete and informative description of exemplary embodiments of the present invention. However, various modifications and adaptations will be apparent to those skilled in the relevant arts in view of the foregoing description when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of the present invention will still fall within the scope of the present invention as defined in the appended claims.

Claims (40)

1. An integrated circuit system, comprising: A memory circuit having: a memory array, a control circuit coupled to an address port, and an input/output circuit coupled to a data input port and a data output port; wherein the control circuit includes an address register that latches a read address in response to a read clock; Each input/output circuit includes: a first data path and a second data path, the first data path is controlled by a write clock and couples a data input end of a data input port to a write bit line of a memory array, and the second data path is controlled by a read clock and couples a read bit line of the memory array to a data output end of a data output port; wherein the second data path in each input/output circuit comprises a multiplexer circuit having a first input coupled to the read bit line, a second input coupled to the bypass path, and an output coupled to the data output; wherein a test bit is applied to a second input of a multiplexer in each input/output circuit in response to a read clock; and The multiplexer is controlled to select the second input terminal during the test operation. 2. The integrated circuit system of claim 1, wherein the memory array of the memory circuit comprises memory cells having separate read ports and write ports. 3. The integrated circuit system of claim 1, wherein the second data path in each input/output circuit comprises a latch circuit that latches data from a read bit line of the memory array in response to a read clock. 4. The integrated circuit system of claim 1, wherein the test bits are address bits of a read address latched in an address register in response to a read clock. 5. The integrated circuit system of claim 3, wherein the bypass path comprises a delay circuit that delays application of the address bits of the read address to the second input terminal of the multiplexer in each input/output circuit by a delay time. 6. The integrated circuit system of claim 5, wherein the delay time is set so that the timing of the test signal propagating from the register through the bypass path and the second input terminal of the multiplexer to the data output terminal is equal to the timing of the memory access read from the memory array through the second data path. 7. The integrated circuit system of claim 4, further comprising shadow logic upstream of the address port, wherein the shadow logic provides a read address during a test operation. 8. The integrated circuit system of claim 7, further comprising a scan register for test operation coupled to the shadow logic upstream of the data input port. 9. The integrated circuit system of claim 4, further comprising a built-in self-test circuit that supplies a read address during a test operation. 10. The integrated circuit system of claim 9, wherein the built-in self-test circuit is further coupled to the data output port. 11. The integrated circuit system of claim 1, further comprising shadow logic downstream of the data output port. 12. The integrated circuit system of claim 11, further comprising a scan register for test operations coupled to the shadow logic downstream of the data output port. 13. The integrated circuit system of claim 1, further comprising shadow logic upstream of the data input port. 14. The integrated circuit system of claim 13, further comprising a scan register for test operation coupled to the shadow logic upstream of the data input port. 15. The integrated circuit system of claim 1, wherein the read clock is asynchronous to the write clock. 16. The integrated circuit system of claim 1, wherein the read clock and the write clock have different frequencies. 17. The integrated circuit system of claim 1, wherein the memory array is divided into a plurality of sub-arrays, each sub-array comprising a local read bit line, and wherein each input/output circuit comprises read logic having an input coupled to the local read bit lines from the plurality of sub-arrays and an output coupled to the second data path. 18. An integrated circuit system as described in claim 17, characterized in that each input/output circuit also includes multiple additional data paths, each additional data path couples a local read bit line of the multiple local read bit lines to a corresponding one of the multiple read data output terminals of the data output port. 19. The integrated circuit system of claim 18, wherein: wherein the test bit is an address bit of a read address latched in an address register in response to a read clock; wherein each additional data path in each input/output circuit comprises an additional multiplexer circuit having a first input coupled to the local read bit line, a second input coupled to the bypass path, and an output coupled to the read data output; wherein the address bits of the read address latched in the address register are applied to the second input of the further multiplexer in each input/output circuit; and Wherein the further multiplexer is controlled to select the second input terminal during a test operation. 20. The integrated circuit system of claim 19, wherein the second data path in each input/output circuit comprises a latch circuit that latches data from a read bit line of the memory array in response to a read clock. 21. The integrated circuit system of claim 19, wherein the bypass path includes a delay circuit that delays application of address bits of the read address to the second input of the additional multiplexer in each input/output circuit by a delay time. 22. An integrated circuit system as described in claim 21, characterized in that the delay time is set so that the timing of the test signal propagating from the register through the bypass path and the second input terminal of the further multiplexer to the read data output terminal is equal to the timing of the memory access read from the memory array through the second data path. 23. The integrated circuit system of claim 19, further comprising shadow logic downstream of the data output port. 24. The integrated circuit system of claim 23, further comprising a scan register for test operations coupled to the shadow logic downstream of the data output port. 25. The integrated circuit system of claim 19, further comprising shadow logic upstream of the data input port. 26. The integrated circuit system of claim 25, further comprising a scan register for test operations coupled to the shadow logic upstream of the data input port. 27. The integrated circuit system of claim 19, further comprising shadow logic upstream of the address port, wherein the shadow logic provides a read address during a test operation. 28. The integrated circuit system of claim 27, further comprising a scan register for test operations coupled to the shadow logic upstream of the data input port. 29. The integrated circuit system of claim 19, further comprising a built-in self-test circuit that supplies a read address during a test operation. 30. The integrated circuit system of claim 29, wherein the built-in self-test circuit is further coupled to the data output port. 31. The integrated circuit system of claim 19, wherein the read clock is asynchronous to the write clock. 32. An integrated circuit system, comprising: a memory circuit, an address port, a data input port, and a data output port; an upstream shadow logic circuit coupled to provide address data to an address port of the memory circuit and to provide input data to a data input port of the memory circuit; and a downstream shadow logic circuit coupled to receive output data from a data output port of the memory circuit; Wherein the memory circuit includes a bypass path between the address port and the data output port, the bypass path being active during the test operation to pass bits of address data applied by the upstream shadow logic circuit from the address port to the data output port. 33. The integrated circuit system of claim 32, wherein the bypass path comprises a delay circuit that delays the transfer of bits of address data from the address port to the data output port. 34. The integrated circuit system of claim 33, wherein the delay time is set so that the timing of the address bits propagating from the address port through the bypass path to the data output port is equal to the timing of the memory access for reading data from the memory circuit for output at the data output port. 35. The integrated circuit system of claim 32, further comprising a scan register coupled to downstream shadow logic for test operations. 36. The integrated circuit system of claim 32, further comprising a scan register coupled to upstream shadow logic for test operations. 37. The integrated circuit system of claim 32, wherein the memory circuit comprises a memory array having a read bit line coupled to the data output port through a read path. 38. The integrated circuit system of claim 37, wherein the read path comprises: a latch circuit that latches data from a read bit line of a memory array in response to a read clock; and a multiplexer circuit having a first input coupled to the output of the latch circuit, a second input coupled to the bypass path, and an output coupled to the data output port; and The multiplexer is controlled to select the second input terminal during the test operation. 39. The integrated circuit system of claim 32, wherein the memory circuit comprises a memory array partitioned into a plurality of subarrays, each subarray comprising a local read bit line coupled to the data output portion via a read path. 40. The integrated circuit system of claim 39, wherein each read path comprises: a latch circuit that latches data from a local read bit line of the memory array in response to a read clock; and a multiplexer circuit having a first input coupled to the output of the latch circuit, a second input coupled to the bypass path, and an output coupled to the data output port; and The multiplexer is controlled to select the second input terminal during the test operation.