CN221709995U - Data acquisition system of matrix MEMS sensor - Google Patents

Abstract

The utility model discloses a data acquisition system for a matrix MEMS sensor, comprising: a computer for generating a data acquisition command; an FPGA chip connected to the computer, generating a data acquisition instruction according to the data acquisition command, and returning the received data of each target sensor to the computer; a matrix MEMS sensor connected to the FPGA chip, synchronously acquiring the data of each target sensor according to the data acquisition instruction; and each level conversion circuit connected to the FPGA chip and the matrix MEMS sensor, performing level conversion on the FPGA chip and the matrix MEMS sensor. The data acquisition system for the matrix MEMS sensor provided by the utility model expands the range of selectable MEMS sensors during data acquisition and improves the accuracy of the collected sensor data.

Description

A data acquisition system for matrix MEMS sensors

Technical Field

The utility model relates to the technical field of sensors, in particular to a data acquisition system of a matrix MEMS sensor.

Background Art

MEMS sensors are increasingly used as a type of sensor that can estimate paths and locate current postures. However, due to the defects of MEMS sensors in terms of accuracy and long-term drift, the accuracy of the collected data is low, so there is an urgent need to adopt some method to evaluate or improve its performance.

In summary, how to effectively solve the problem of low accuracy of collected data caused by defects in MEMS sensors in terms of accuracy and long-term drift is an issue that technicians in this field urgently need to solve.

Utility Model Content

The utility model aims to provide a data acquisition system for a matrix MEMS sensor, which improves the accuracy of the acquired sensor data.

In order to solve the above technical problems, the utility model provides the following technical solutions:

A data acquisition system for a matrix MEMS sensor, comprising:

a computer that generates data acquisition commands;

connected to the computer, generating a data acquisition instruction according to the data acquisition command, and returning the received data of each target sensor to the FPGA chip of the computer;

A matrix MEMS sensor connected to the FPGA chip and synchronously collecting data of each target sensor according to the data collection instruction;

Each level conversion circuit is connected to the FPGA chip and the matrix MEMS sensor and performs level conversion on the FPGA chip and the matrix MEMS sensor.

In a specific implementation of the present utility model, the level conversion circuit is a DCDC conversion circuit.

In a specific implementation of the utility model, it also includes:

A level control switch is arranged between the FPGA chip and each of the level conversion circuits.

In a specific implementation of the present utility model, the level control switch is a field effect transistor.

In a specific implementation of the utility model, it also includes:

A synchronization circuit is arranged between the FPGA chip and the matrix MEMS sensor.

In a specific implementation manner of the present utility model, the FPGA chip is connected to the computer via a Gigabit Ethernet circuit.

In a specific implementation manner of the present utility model, the Gigabit Ethernet circuit is connected to the computer via an RJ45 interface.

In a specific implementation of the present invention, the MEMS sensors included in the matrix MEMS sensor are MEMS sensors of different types or models.

The data acquisition system of the matrix MEMS sensor provided by the utility model comprises: a computer for generating data acquisition commands; an FPGA chip connected to the computer, generating data acquisition instructions according to the data acquisition commands, and returning the received data of each target sensor to the computer; a matrix MEMS sensor connected to the FPGA chip, synchronously acquiring the data of each target sensor according to the data acquisition instructions; and each level conversion circuit connected to the FPGA chip and the matrix MEMS sensor, performing level conversion on the FPGA chip and the matrix MEMS sensor.

It can be seen from the above technical solution that the parallel characteristics of FPGA can be used to realize parallel synchronous real-time data acquisition of multiple MEMS sensors. By setting various level conversion circuits connected to the FPGA chip and the matrix MEMS sensor, MEMS sensors of various levels are supported, expanding the range of MEMS sensors that can be selected during data acquisition. By evaluating and analyzing the collected data of multiple target sensors, the accuracy of the collected sensor data is improved.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a structural block diagram of a data acquisition system of a matrix MEMS sensor in an embodiment of the present utility model;

FIG2 is a basic configuration circuit diagram of an FPGA chip in an embodiment of the present utility model;

FIG3 is a partial interface circuit diagram of an FPGA chip in an embodiment of the present utility model;

FIG4 is a level conversion circuit diagram of an embodiment of the utility model;

FIG5 is a schematic diagram of a FPGA chip that collects data from multiple MEMS sensors in parallel and synchronously in real time in an embodiment of the present utility model;

FIG6 is a schematic diagram of another FPGA chip in parallel and synchronously collecting data from multiple MEMS sensors in real time in an embodiment of the present utility model.

FIG7 is a circuit diagram of an FPGA chip control level selection circuit in an embodiment of the present utility model;

FIG8 is a schematic diagram of an FPGA chip simulating UART timing to collect MEMS sensor data in an embodiment of the present utility model;

FIG9 is a schematic diagram of an FPGA chip simulating I2C timing to collect MEMS sensor data in an embodiment of the present utility model;

FIG. 10 is a schematic diagram of an FPGA chip simulating SPI timing to collect MEMS sensor data in an embodiment of the present utility model.

The following are marked in the accompanying drawings:

1-computer, 2-FPGA chip, 3-matrix MEMS sensor, 4-level conversion circuit.

DETAILED DESCRIPTION

In order to enable those skilled in the art to better understand the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.

Referring to FIG. 1 , FIG. 1 is a structural block diagram of a data acquisition system of a matrix MEMS sensor in an embodiment of the utility model. The data acquisition system of the matrix MEMS sensor includes:

A computer 1 for generating data acquisition commands;

Connected to computer 1, generates data acquisition instructions according to data acquisition commands, and returns the received data of each target sensor to FPGA chip 2 of computer 1;

A matrix MEMS sensor 3 connected to the FPGA chip 2 for synchronously collecting data from each target sensor according to a data collection instruction;

The level conversion circuits 4 are connected to the FPGA chip 2 and the matrix MEMS sensor 3 and perform level conversion on the FPGA chip 2 and the matrix MEMS sensor 3 .

As shown in FIG1 , the data acquisition system of the matrix MEMS sensor provided by the utility model comprises a computer 1, an FPGA (Field Programmable Gate Array, programmable logic device) chip 2, a matrix MEMS sensor 3 and various level conversion circuits 4. When it is necessary to obtain sensor data, the computer 1 generates a data acquisition command and sends the data acquisition command to the FPGA chip 2. The FPGA chip 2 receives the data acquisition command and generates a data acquisition instruction according to the data acquisition command. After performing level conversion on the FPGA chip 2 and the matrix MEMS sensor 3 through the various level conversion circuits 4, the data acquisition instruction is sent to the matrix MEMS sensor 3. The matrix MEMS sensor 3 synchronously acquires the data of each target sensor according to the data acquisition instruction, and returns the acquired data of each target sensor to the FPGA chip 2 after level conversion through the various level conversion circuits 4, so that the FPGA chip 2 completes the control and data acquisition of the matrix MEMS sensor 3. The FPGA chip 2 then returns the received data of each target sensor to the computer 1, thereby realizing the real-time synchronous parallel data acquisition of the matrix MEMS sensor 3 through the parallel characteristics of the FPGA.

By setting each level conversion circuit 4 connected to the FPGA chip 2 and the matrix MEMS sensor 3, various levels of MEMS sensors are supported, and the range of selectable MEMS sensors during data collection is expanded. After collecting the data of each target sensor, the accuracy of the data can be improved by averaging the data of each target sensor.

See Figure 2, which is a basic configuration circuit diagram of an FPGA chip in an embodiment of the utility model. Computer 1 pre-configures FPGA chip 2 through J12 to complete programming of FPGA chip 2. J12 is a JTAG (Joint Test Action Group) download interface, and FPGA_TCK, FPGA_TDO, FPGA_TDI, and FPGA_TMS are JTAG download line interfaces.

See Figure 3, which is a partial interface circuit diagram of an FPGA chip in an embodiment of the utility model. MEMS000, MEMS001, and MEMS002 control the power supply of MEMS00, and each interface can work independently in real time to achieve level matching for real-time synchronous parallel data acquisition. MEMS00-0, MEMS00-1, MEMS00-2, MEMS00-3, and MEMS00-4 control the signal line of MEMS00, and each interface can work independently in real time to achieve real-time synchronous parallel data acquisition, and the same applies to other pin lines. FPGA chip 2 can use XC7A100T2FGG484, which has 250 general IO (input/output), which can fully meet the needs of this system. The IO of FPGA chip 2 works completely in parallel. Under the control of hardware description language programming, various timings can be output synchronously in real time, and a total of 32 MEMS sensors can be supported.

See Figure 4, which is a level conversion circuit diagram in an embodiment of the utility model. The level conversion circuit 4 can use the TXS0108E bidirectional voltage level converter chip, and only the first two of the 32-way level conversion circuit 4 are shown. U72 and U73 are composed of TXS0108E. The signals MEMS00-0, MEMS00-1, MEMS00-2, MEMS00-3, MEMS00-4, MEMS01-0, MEMS01-1, MEMS01-2, MEMS01-3, and MEMS01-4 of the FPGA chip 2 are connected from the A end of the converter chip and connected from the B end. The A end voltage of TXS0108E is fixed at 3.3V and is fixedly connected to the BANK output of FPGA chip 2. The B end voltage of TXS0108E can be adjusted by the respective B end levels (SEL00_VD and SEL01VD in Figure 4). Whatever voltage level SEL00_VD and SEL01VD provide, the B-side input signal supports whatever voltage level, and TXS0108E works independently and does not affect each other. Therefore, various voltage levels of MEMS sensors can be supported by selecting the B-side voltage of each TXS0108E.

Referring to FIG. 5 , FIG. 5 is a schematic diagram of a FPGA chip in parallel and synchronously collecting multiple MEMS sensor data in real time in an embodiment of the utility model. Each MEMS sensor is a matrix MEMS sensor 3. The upper limit of the entire system design is 32 MEMS sensors, arranged as MEMS00, MEMS01, MEMS02, MEMS03, MEMS04, MEMS05, MEMS06, MEMS07, MEMS10, MEMS11, MEMS12 ... MEMS30, MEMS31, MEMS32, MEMS33, MEMS34, MEMS35, MEMS36, MEMS37, wherein the 3 in MEMS37 represents the 3rd column, and the 7 represents the 7th row, for a total of 4 rows and 8 columns. The communication line of each MEMS sensor is connected to the communication IO of the FPGA chip 2 through the corresponding level conversion 00, level conversion 01 ... level conversion 36, level conversion 37. The level of the 32-way level conversion 00 to the level conversion 37 is controlled by the level selection IO of the FPGA chip 2. Make full use of the advantages of array sensors such as high precision, high sensitivity, high reliability, wide application and high data processing efficiency.

See Fig. 6, which is a schematic diagram of another FPGA chip in parallel and synchronously collecting data of multiple MEMS sensors 3 in real time in an embodiment of the utility model. Each MEMS sensor 3 can also be set separately.

It should be noted that the configuration program of the computer 1 for the FPGA chip 2 is already existing, and the embodiment of the utility model does not provide protection for this.

It can be seen from the above technical solution that the parallel characteristics of FPGA can be used to realize parallel synchronous real-time data collection of multiple MEMS sensors. By setting various level conversion circuits connected to the FPGA chip and the matrix MEMS sensor, MEMS sensors of various levels are supported, expanding the range of MEMS sensors that can be selected during data collection. By evaluating and analyzing the collected data of multiple target sensors, the accuracy of the collected sensor data is improved.

In a specific implementation of the present invention, the level conversion circuit 4 is a DCDC conversion circuit.

Referring to FIG. 7, FIG. 7 is a circuit diagram of an FPGA chip control level selection in an embodiment of the utility model. The level conversion circuit 4 selected in the embodiment of the utility model can be a DCDC conversion circuit. The working levels of each MEMS sensor included in the matrix MEMS sensor may be different, but they are roughly 1.8V, 3.3V, and 5V. Therefore, it is necessary to provide a corresponding working level according to the working level of the actual MEMS sensor. The data acquisition system of the matrix MEMS sensor uses a DCDC conversion circuit to convert 12V into 1.8V, 3.3V, and 5V as the power supply to be selected for the MEMS sensor. FIG. 5 only shows the first two of the 32-way level selection. MEMS000, MEMS001, MEMS002, MEMS010, MEMS011, and MEMS012 are from the FPGA chip 2. Through the selection of the corresponding field effect tube, +1.8VD, +3.3VD, and +5.0VD are controlled to supply power to one end of the corresponding level conversion circuit 4 connected to the MEMS sensor, so as to realize the reading and writing of MEMS sensor data supporting different voltages.

In a specific implementation of the present utility model, the data acquisition system of the matrix MEMS sensor further includes:

A level control switch is arranged between the FPGA chip 2 and each level conversion circuit 4.

The data acquisition system of the matrix MEMS sensor provided by the embodiment of the utility model may also include a level control switch arranged between the FPGA chip 2 and each level conversion circuit 4. The FPGA chip 2 can open or close each level control switch by outputting a high or low level through the level selection IO, thereby controlling each level conversion circuit 4.

In a specific implementation of the present utility model, the level control switch is a field effect transistor.

The level control switch in the data acquisition system of the matrix MEMS sensor provided by the embodiment of the utility model can be specifically a field effect tube, which fully utilizes the advantages of the field effect tube such as high input resistance, low noise, and good thermal stability.

In a specific implementation of the present utility model, the data acquisition system of the matrix MEMS sensor further includes:

A synchronization circuit is provided between the FPGA chip 2 and the matrix MEMS sensor.

The data acquisition system of the matrix MEMS sensor provided by the embodiment of the utility model may further include a synchronization circuit arranged between the FPGA chip 2 and the matrix MEMS sensor.

See Figure 8, which is a schematic diagram of an FPGA chip simulating UART timing to collect MEMS sensor data in an embodiment of the utility model. In the figure, a MEMS00 sensor that supports the UART (Universal Asynchronous Receiver/Transmitter) protocol is used as an example. The FPGA chip 2 simulates the TX (transmit) and RX (receive) timing of UART communication through three communication IO pins to realize the data collection of the MEMS00 sensor. The SYNC pin is used to synchronize the data conversion of all MEMS sensors. The level conversion 00 realizes the level matching between the FPGA end and the MEMS00 end.

See Figure 9, which is a schematic diagram of an FPGA chip simulating I2C timing to collect MEMS sensor data in an embodiment of the utility model. The figure takes a MEMS00 sensor that supports the I2C (Inter-Integrated Circuit) protocol as an example. FPGA chip 2 simulates the SCL and SDA timing of I2C communication through 3 communication IO pins to realize the data collection of MEMS00 sensor. Among them, the SYNC pin is used to synchronize the data conversion of all MEMS sensors. Level conversion 00 realizes the level matching between the FPGA end and the MEMS00 end.

See Figure 10, which is a schematic diagram of an FPGA chip simulating SPI timing to collect MEMS sensor data in an embodiment of the utility model. The figure takes a MEMS00 sensor that supports the SPI (Serial Peripheral Interface) protocol as an example. The FPGA chip 2 simulates the CS (chip select), MOSI (Master Output/Slave Input), MISO (Master Input/SlaveOutput), and CLK (Clock) timing of SPI communication through 5 communication IO pins to realize the MEMS00 sensor data collection. Among them, the SYNC pin is used to synchronize the data conversion of all MEMS sensors. The level conversion 00 realizes the level matching between the FPGA end and the MEMS00 end.

MEMS sensors generally have UART, SPI or I2C interfaces. UART has 2 data lines, SPI generally has 4 data lines, and I2C generally has 2 data lines. 32 MEMS sensors require a maximum of 32×5=160 data lines to meet the requirements of most MEMS synchronous real-time communication (the added fifth line is the synchronization signal for all MEMS sensors). The SYNC pin is used to synchronize the data conversion of all MEMS sensors.

It should be noted that the embodiment of the utility model does not protect the software programs involved in the FPGA chip 2 simulating the above three communication protocols.

In a specific implementation of the present utility model, the FPGA chip 2 is connected to the computer 1 via a Gigabit Ethernet circuit.

The FPGA chip 2 is connected to the computer 1 via a Gigabit Ethernet circuit. Gigabit Ethernet is used to realize the communication between the computer 1 and the FPGA chip 2, ensuring that the communication speed meets the requirements of real-time synchronous parallel acquisition of MEMS sensor data.

In a specific implementation of the present invention, the Gigabit Ethernet circuit is connected to the computer 1 via an RJ45 interface.

The Gigabit Ethernet circuit is connected to the computer 1 through an RJ45 interface, making full use of the advantages of the RJ45 interface such as standardization, high transmission rate, strong compatibility, and easy maintenance.

As shown in FIG. 1 , the FPGA chip 2 , the Gigabit Ethernet circuit, the RJ45 interface, various level conversion circuits, and various MEMS sensors can all be arranged in the circuit board. In addition, a power module for power supply can also be arranged in the circuit board.

In a specific implementation of the present invention, the MEMS sensors included in the matrix MEMS sensor 3 are MEMS sensors of different types or models.

The MEMS sensors included in the matrix MEMS sensor 3 can be set to different types or models of MEMS sensors. By expanding the types and models of sensors, the accuracy of data collection is further improved. The FPGA chip 2 realizes multi-channel, multi-level, and parallel communication modes, thereby realizing real-time synchronous parallel data collection of each MEMS sensor.

The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

The above is a detailed introduction to a data acquisition system of a matrix MEMS sensor provided by the utility model. This article uses specific examples to illustrate the principle and implementation method of the utility model. The description of the above embodiment is only used to help understand the method and core idea of the utility model. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the utility model, the utility model can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the claims of the utility model.

It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims (8)

1. A data acquisition system for a matrix MEMS sensor, comprising:

a computer (1) for generating a data acquisition command;

The FPGA chip (2) is connected with the computer (1), generates a data acquisition instruction according to the data acquisition command, and returns the received data of each target sensor to the computer (1);

The matrix MEMS sensor (3) is connected with the FPGA chip (2) and synchronously acquires the data of each target sensor according to the data acquisition instruction;

And each level conversion circuit (4) is connected with the FPGA chip (2) and the matrix MEMS sensor (3) and is used for carrying out level conversion on the FPGA chip (2) and the matrix MEMS sensor (3).

2. The data acquisition system of a matrix MEMS sensor according to claim 1, wherein the level conversion circuit (4) is a DCDC conversion circuit.

3. The data acquisition system of a matrix MEMS sensor according to claim 1 or 2, further comprising:

and the level control switch is arranged between the FPGA chip (2) and each level conversion circuit (4).

4. A data acquisition system for a matrix MEMS sensor according to claim 3, wherein the level control switch is a field effect transistor.

5. The data acquisition system of a matrix MEMS sensor of claim 1, further comprising:

And the synchronous circuit is arranged between the FPGA chip (2) and the matrix MEMS sensor (3).

6. The data acquisition system of a matrix MEMS sensor according to claim 1, wherein the FPGA chip (2) is connected to the computer (1) by a gigabit ethernet circuit.

7. The data acquisition system of a matrix MEMS sensor according to claim 6, wherein the gigabit ethernet circuit is connected to the computer (1) via an RJ45 interface.

8. A data acquisition system of matrix MEMS sensors according to claim 1, characterized in that the matrix MEMS sensors (3) comprise MEMS sensors of different kinds or different models.