CN221708719U - Electronic Devices - Google Patents

Abstract

The present disclosure relates to electronic devices. An electronic device, comprising: a solid body of hexagonal polytype silicon carbide having a first conductivity; at least one injection region extending at the front side of the solid body, the at least one injection region having a second conductivity opposite the first conductivity; a cubic polytype of silicon carbide layer on the front side; a silicon layer on the cubic polytype silicon carbide layer; a carbon-rich layer on the silicon layer; an ohmic contact region passing through the entire thickness of the cubic multi-type silicon carbide layer, the silicon layer and the carbon-rich layer until reaching the implantation region; and a first electrical terminal of electrically conductive material located over and in direct contact with the carbon-rich layer. Embodiments of the present disclosure have lower schottky barrier height values, enabling more efficient schottky diodes to be fabricated.

Description

Electronic Devices

Technical Field

The present disclosure relates to electronic devices formed at least in part with 3C-SiC.

Background Art

As is known, semiconductor materials having a wide bandgap, in particular having a bandgap energy value Eg greater than 1.1 eV, low on-state resistance (RON), high thermal conductivity values, high operating frequencies and high charge carrier saturation velocity are ideal for the production of electronic components, such as diodes or transistors, in particular for power applications. A material having the described properties and designed for the manufacture of electronic components is silicon carbide (SiC). Silicon carbide has different crystal forms, also called polytypes. The most common polytypes are the cubic polytype (polytype 3C-SiC), the hexagonal polytype (polytypes 4H-SiC and 6H-SiC) and the rhombohedral polytype (polytype 15R-SiC).

Electronic devices arranged on silicon carbide substrates have many advantages over similar devices arranged on silicon substrates, such as low output resistance in conduction, low leakage current, high operating temperature and high operating frequency. In particular, SiC Schottky diodes have shown higher switching performance, making SiC electronic devices particularly beneficial for high-frequency applications. Current applications place demands on the electrical performance of the devices as well as long-term reliability.

4H-SiC is often used as a substrate due to its easier fabrication relative to other polytypes. However, the larger band gap of 4H-SiC (3.2 eV) relative to the corresponding band gaps of 3C-SiC (2.3 eV) or silicon (1.12 eV) makes 4H-SiC less attractive for some electronic applications relative to 3C-SiC or relative to silicon. For example, in the case of Schottky barrier diodes, the possibility to control the Schottky barrier height (SBH) value is an important aspect in order to reduce energy consumption and minimize conduction losses. To this end, the implementation of metal/3C-SiC or metal/Si contacts leads to lower SBH values relative to the SBH values of metal/4H-SiC contacts, enabling the fabrication of more efficient Schottky diodes.

In addition, the breakdown voltage of SiC is also greater than that of silicon. This is due to the critical electric field of silicon carbide being approximately ten times greater than that of silicon. Another advantage associated with fabricating devices on a substrate (bulk) of 4H-SiC in general is maintaining the advantages of the breakdown voltage, but having a lower bandgap material (e.g., silicon or 3C-SiC) on the surface, such that the barrier height of, for example, a Schottky contact is reduced. In other words, it is desirable to maintain the advantages of reverse bias and optimize the voltage drop for forward bias.

FIG1 shows a lateral cross-sectional view in a Cartesian (triaxial) reference system of the X, Y, Z axes, of a Junction Barrier Schottky (JBS) device, or a similar Merged PN Schottky (MPS) diode, indicated by reference numeral 1. The device of FIG1 is not necessarily prior art, and reference will be made hereinafter to the JBS device 1 without loss of generality.

The JBS device 1 comprises: a substrate 3 of N-type doped 4H-SiC with a first dopant concentration (for example comprised between 1·10 ¹⁹ and 1·10 ²² atoms/cm ³ ), with a resistivity comprised, for example, between 2 mΩ·cm and 40 mΩ·cm, with a surface 3a opposite to a surface 3b, and a thickness comprised between 50 μm and 350 μm, more particularly between 160 μm and 200 μm, for example equal to 180 μm; a drift layer (epitaxially grown) 2 made of N-type 4H-SiC with a second dopant concentration lower than the first dopant concentration (for example comprised between 10 ¹⁴ and 10 ¹⁶ atoms/cm ³ ), which extends on the surface 3a of the substrate 3 and has a thickness included between 5μm and 15μm; an ohmic contact region 6 (e.g., nickel silicide), which extends on the surface 3b of the substrate 3; a cathode metallization 7, such as Ti/NiV/Ag or Ti/NiV/Au, which extends on the ohmic contact region 6; an anode metallization 8, such as Ti/AlSiCu or Ni/AlSiCu, which extends on the top surface 2a of the drift layer 2; a passivation layer 19 on the anode metallization 8 to protect the anode metallization; a plurality of junction barrier (JB) elements 9 in the drift layer 2, facing the top surface 2a of the drift layer 2, and each junction barrier element 9 includes a corresponding P-type implant region 9' and an ohmic contact 9"; and an edge termination region or guard ring 10 (optional), in particular a P-type implant region, which surrounds (completely or partially, depending on design choice) the JB element 9.

The Schottky diode 12 is formed at the interface between the drift layer 2 and the anode metallization 8. In particular, a Schottky (semiconductor-metal) junction is formed by portions of the drift layer 2 that are in direct electrical contact with corresponding portions of the anode metallization 8.

The region of the JBS device 1 including the JB element 9 and the Schottky diode 12 (ie, the region included in the guard ring 10 ) is the active region 4 of the JBS device 1 .

Referring to FIGS. 2A and 2B , the manufacturing step of the JBS device 1 of FIG. 1 ( FIG. 2A ) provides a step of masking and implanting a dopant substance (e.g., boron or aluminum) having a second conductivity type (P) in the drift layer 2. The implantation is shown by arrow 18 in FIG. 2A . The mask 11 is used for implantation, in particular a hard mask of silicon oxide or TEOS. In an exemplary embodiment, the implantation step includes one or more implantations of a dopant substance having a second conductivity type, with an implantation energy between 30 keV and 400 keV and a dose between 1·10 ¹² atoms/cm ² and 1·10 ¹⁵ atoms/cm ² .

Thereby an implantation region 9' and an edge termination region 10 are formed. The implantation region 9' and the edge termination region 10 have a depth measured from the surface 2a comprised between 0.2 μm and 1 μm.

2B, the mask 11 is removed and a thermal annealing step is performed to activate the doping species implanted in the step of Fig. 2A. The thermal annealing is performed in a furnace at a temperature above 1600°C (eg 1700-1900°C, even higher in some cases), for example.

3A-3C , additional steps are then performed to form an ohmic contact 9 ″. Referring to FIG. 3A , a deposition mask 13 of silicon oxide or TEOS is formed to cover the surface area of the drift layer 2 except for the implantation region 9 ′ (and the surface area of the edge termination 10 , if any). In other words, the mask 13 has a through opening 13 a at the implantation region 9 ′ (and optionally at least a portion of the edge termination 10 ). Then, in FIG. 3B , nickel deposition is performed on the mask 13 and within the through opening 13 a (the metal layer 14 in FIG. 3B ). The nickel thus deposited reaches and contacts the implantation region 9 ′ and the edge termination region 10 through the through opening 13 a.

With reference to FIG. 3C , a subsequent high temperature thermal annealing (between 700° C. and 1200° C., with a time interval ranging from 1 minute to 120 minutes) allows the formation of an ohmic contact 9″ of nickel silicide by a chemical reaction between the nickel deposited at the through opening 13 a and the silicon carbide (4H-SiC) of the drift layer 2 . In practice, the deposited nickel reacts where it is in contact with the surface material of the drift layer 2 , forming Ni ₂ Si (i.e., an ohmic contact). Subsequently, a step of removing the metal extending above the mask 13 and the removal of the mask 13 are performed.

After forming the ohmic contact, the method continues by forming (e.g. by deposition) an anode metallization 8, such as Ti/AlSiCu or Ni/AlSiCu, on the top surface 2a of the drift layer 2 and in direct electrical contact with the ohmic contact 9". Then, a passivation layer 19 is formed on the anode metallization layer 8 to protect the anode metallization. Thus, a corresponding Schottky diode 12 is formed at the interface between the drift layer 2 and the anode metallization 8, laterally to the implantation region 9'. In particular, a Schottky (semiconductor-metal) junction is formed by a portion of the drift layer 2 between the JB elements 9 that is in direct electrical contact with a corresponding portion of the anode metallization 8.

Utility Model Content

The utility model aims to provide an electronic device at least partially formed of 3C-SiC to overcome the disadvantages of the prior art.

One aspect of the present disclosure provides an electronic device, comprising: a hexagonal polytype silicon carbide solid body having a first conductivity; at least one implanted region extending at a front side of the solid body, the at least one implanted region having a second conductivity opposite to the first conductivity; a cubic polytype silicon carbide layer on the front side; a silicon layer on the cubic polytype silicon carbide layer; a carbon-containing layer on the silicon layer; an ohmic contact region extending through the entire thickness of the cubic polytype silicon carbide layer, the silicon layer, and the carbon-containing layer until reaching the implanted region; and a conductive first electrical terminal located above and in direct contact with the carbon-containing layer.

According to one or more embodiments, wherein the solid body is of hexagonal polytype silicon carbide and the carbon-containing layer is graphitic, includes graphite, includes one or more graphite layers, includes graphene, or includes graphite and graphene.

In accordance with one or more embodiments, the first electrical terminal forms a Schottky diode having a carbon-containing layer and a junction barrier diode having an ohmic contact region.

According to one or more embodiments, wherein the first electrical terminal is common to the junction barrier diode and the Schottky diode, the electronic device further includes a second electrical terminal common to the junction barrier diode and the Schottky diode at a rear side opposite to the front side of the solid state body.

According to one or more embodiments, the electronic device is one of: a merged PiN Schottky MPS device; a junction barrier Schottky JBS device; a MOSFET; an IGBT; a JFET; or a DMOS.

Another aspect of the present disclosure provides an electronic device, comprising: a hexagonal polytype silicon carbide solid body having a first conductivity; a first implanted region extending at a front side of the solid body, the first implanted region having a second conductivity opposite to the first conductivity, the first implanted region including a source terminal; a second implanted region having a second conductivity, extending at a distance from the first implanted region at the front side of the solid body, the second implanted region including a drain terminal; a cubic polytype silicon carbide layer on the front side; a gate dielectric of silicon oxide on the cubic polytype silicon carbide layer between the first implanted region and the second implanted region; and a metal electric gate terminal located above the gate dielectric and in direct contact with the gate dielectric.

According to one or more embodiments, the electronic device includes one or more of: a merged PiN Schottky MPS device; a junction barrier Schottky JBS device; a MOSFET; an IGBT; a JFET; or a DMOS.

Embodiments of the present disclosure have lower Schottky barrier height values, enabling the fabrication of more efficient Schottky diodes.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the present disclosure, preferred embodiments thereof will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which:

FIG. 1 illustrates a cross-sectional view of a JBS or MPS device according to one embodiment;

2A and 2B illustrate cross-sectional views of intermediate fabrication steps of the device of FIG. 1 according to an embodiment;

3A-3C illustrate cross-sectional views of steps for forming ohmic contacts for the device of FIG. 1 , following the steps of FIGS. 2A and 2B , according to an embodiment;

FIG4 illustrates a cross-sectional view of a JBS or MPS device according to an embodiment;

5A and 5B illustrate cross-sectional views of intermediate fabrication steps of the device of FIG. 4 according to an embodiment;

6A-6D illustrate cross-sectional views of intermediate fabrication steps of the device of FIG. 4 according to another embodiment, which is an alternative to the embodiment of FIGS. 6A-6B ;

FIG7 illustrates a cross-sectional view of a JBS or MPS device according to another embodiment;

8A-8C illustrate cross-sectional views of intermediate fabrication steps of the device of FIG. 7 according to an embodiment;

FIG9 illustrates a JBS or MPS device in cross-sectional view according to one embodiment;

10A-10D illustrate cross-sectional views of intermediate fabrication steps of the device of FIG. 9 according to one embodiment; and

FIG. 11 shows a cross-sectional view of a planar MOSFET device according to another embodiment.

DETAILED DESCRIPTION

Elements common to the JBS device of FIG. 1 are identified with the same reference numerals and will not be described further.

Figure 4 shows a JBS device 50 according to one embodiment in a cross-sectional view in the Cartesian (three-axis) reference system of the X, Y, Z axes of Figure 1. The view of Figure 4 may be similar to an MPS device (diode) (reference will be made below only to JBS devices without loss of generality).

The JBS device 50 comprises: a substrate 3 of N-type 4H-SiC having a first dopant concentration; an (epitaxial) drift layer 2 of N-type 4H-SiC having a second dopant concentration; a cubic silicon carbide (3C-SiC) layer 52 on a surface 2a; an anode metallization layer 8, such as Ti/AlSiCu or Ni/AlSiCu, extending on the 3C-SiC layer 52; a passivation layer 19 on the anode metallization 8; a plurality of implanted regions 9' in the drift layer 2, facing the top surface 2a of the drift layer 2, in contact with the 3C-SiC layer 52; and a plurality of implanted regions 9' in the drift layer 2, facing the top surface 2a of the drift layer 2. at the interface of the C-SiC layer 52; multiple ohmic contacts 54, extending through the 3C-SiC layer at the corresponding implantation area 9' and forming corresponding JB elements 59 with the latter; an edge termination area or guard ring 10 (optional), in particular a P-type implantation area, completely or partially surrounding the JB element 9; an ohmic contact area or layer 6 (for example, nickel silicide), which extends on the surface 3b of the substrate 3; a cathode metallization 7, for example Ti/NiV/Ag or Ti/NiV/Au, which extends on the ohmic contact area 6.

One or more Schottky diodes 57 extend transversely to the implanted region 9' at the interface between the 3C-SiC layer 52 and the anode metallization 8. In particular, one or more Schottky (semiconductor-metal) junctions are formed by portions of the 3C-SiC layer 52 that are in direct electrical contact with corresponding portions of the anode metallization 8.

The region of the JBS device 50 including the JB element 59 and the Schottky diode 57 (ie, the region included within the guard ring 10 , if any) is the active region 4 of the JBS device 50 .

5A and 5B illustrate intermediate fabrication steps of a JBS device 50 according to an embodiment of the present disclosure in transverse cross-sectional views in the Cartesian (three-axis) reference system of the X, Y, and Z axes of FIGS. 2A-2B , 3A-3C , and 4 .

Specifically, after performing the steps of FIGS. 2A and 2B (not further described here), a step of forming (eg, growing) a cubic silicon carbide (3C-SiC) layer 52 on the surface 2 a of the drift layer 2 is performed, as shown in FIG. 5A .

The growth of 3C-SiC on 4H-SiC substrates/layers is known per se. The method used for this purpose is called the vapor-liquid-solid (VLS) mechanism, as described, for example, by Soueidan M et al., "A Vapor–Liquid–Solid Mechanism for Growing 3C-SiC Single-Domain Layers on 6H-SiC (0001)", advanced functional materials, vol. 16, pages 975-979, 02 May 2006.

Another method is known as sublimation epitaxy (SE), as described, for example, by Valdas Jokubavicius et al. in “Lateral Enlargement Growth Mechanism of 3C-SiC on Off-Oriented 4H-SiC Substrates”, Crystal Growth & Design 2014 14(12), 6514-6520.

Another method is known from Rositsa Yakimova et al., “Growth, Defects and Doping of 3C-SiC on Hexagonal Polytypes”, ECS Journal of Solid State Science and Technology, Vol. 6, No. 10, p. 741, November 2017.

The method then continues, FIG5B , with the step of forming an ohmic contact 54 , using the process already described with reference to FIGS3A-3C , which is applicable to the embodiment of FIG5B . In particular, in this case, the mask 13 is formed on the 3C-SiC layer 52 , and the through opening 13 a extends until reaching the 3C-SiC layer 52 . Thus, the metal layer 14 extends until reaching the 3C-SiC layer 52 .

The formation of the ohmic contact includes depositing nickel in the opening 13a. The nickel thus deposited reaches and contacts the 3C-SiC 52 layer. Subsequent high temperature heat treatment (at a time interval of 1 minute to 120 minutes between 700°C and 1200°C) allows the formation of a nickel silicide ohmic contact 54 by a chemical reaction between the nickel deposited at the opening 13a and the silicon carbide (3C-SiC).

Alternatively, an opening 13a extending to the drift layer 2 may be formed in the implantation region 9'. In this case, the formation of the ohmic contact includes depositing nickel in the opening 13a until it reaches the implantation region 9'.

After the step of FIG. 5B , the method performs the following steps: forming (e.g., by deposition) an anode metallization 8, such as Ti/AlSiCu or Ni/AlSiCu, in direct electrical contact with the ohmic contact 54 on the 3C-SiC layer 52. Then, a passivation layer 19 is formed on the anode metallization layer 8 to protect the anode metallization. Thus, a corresponding Schottky diode 57 is formed at the interface between the 3C-SiC layer 52 and the anode metallization 8, lateral to the ohmic contact 57.

6A-6D illustrate another method for forming the 3C—SiC layer 52 .

In this case, the step of forming a cubic silicon carbide (3C-SiC) layer 52 on the surface 2a of the drift layer 2 can be performed by melting and resolidification (crystallization) of the 4H-SiC material of the drift layer 2, such as described in "Laser-induced phase separation of silicon carbide" by Choi, I., Jeong, H., Shin, H. et al., Nature Communications 7, 13562 (2016).

As shown in FIG6A , the process results in the formation of a stack 60, which includes: a 3C-SiC layer 52 on a drift layer 2 of 4H-SiC; a silicon layer 56 on the 3C-SiC layer 52; and a carbon-rich layer 58 (e.g., graphite or including graphite or including a graphite layer) on the silicon layer 56. In one embodiment, the thickness of the 3C-SiC layer 52 is 10-200 nm, the thickness of the silicon layer 56 is 5-100 nm, and the thickness of the carbon-rich layer is 5-100 nm. Since the process requires a crystalline phase change of a portion of the drift layer 2 at the top surface 2a, the drift layer 2 has a reduced thickness after the stack 60 is formed. From an electrical or functional point of view, the melting and crystallization steps do not damage the implanted region 9'.

The 3C—SiC layer 52 and the silicon layer 56 have substantially the same doping as the drift layer 2 of 4H—SiC, since the melting and crystallization steps do not require a change in the dosage of the dopant already present in the drift layer 2 .

The melting of the 4H-SiC material of the drift layer 2 is performed in particular by laser processing, the configuration and operating parameters of which are as follows:

The wavelength is between 240 and 700 nm, especially 308 nm;

The pulse duration is between 20ns and 500ns, especially 160ns;

The number of pulses is between 1 and 16, especially 4;

energy density between 1.6 and 4 J/cm ² , in particular 2.6 J/cm ² (considered at the level of the top surface 2 a );

The temperature is between 1400° C. and 2600° C., in particular 2200° C. (considered at the level of the surface 2 a ).

The area of the spot of the light beam 102 at the level of the front side 2 a is, for example, comprised between 0.7 and 1.5 cm ² .

After the melting step, crystallization of the melted portion is performed at a temperature of 1600 to 2600° C. for a time of 200 to 600 ns. Thus, the aforementioned stacked layer 60 is formed.

Then, FIG. 6B , an oxidation step of the carbon-rich layer 58 and the underlying silicon layer 56 is performed, thereby forming a corresponding oxide layer. This step is performed by inserting the wafer into a furnace at 800° C. for 60 minutes. This facilitates oxidation of both the carbon-rich layer 58 and the silicon layer 56. Corresponding oxidation of the 3C-SiC layer 52 and the 4H-SiC material of the substrate 3 and the epitaxial layer 2 will not occur.

Then, FIG6C, a subsequent bath in a suitable wet etching solution, such as BOE (buffered oxide etchant), allows the oxide layer to be completely removed in the step of FIG6B, exposing the 3C-SiC layer 52. Since the etching chemical solution selectively removes the material of the layers 56, 58 that have been oxidized, the etching is performed until such oxidized layers are completely removed, without removing the underlying 3C-SiC layer 52.

Then, in accordance with what has been described with reference to FIG. 5B (ie, following the process of FIGS. 3A-3C , with appropriate modifications already discussed), in FIG. 6D , the ohmic contact 54 passes through the 3C-SiC layer 52 at the implanted region 9 ′ (and possibly at the ring 10 , if any).

By using a properly configured laser source, it is possible to simultaneously melt the surface portion of the drift layer 2 (thereby forming the 3C-SiC layer 52 as described above) and activate the dopant species implanted in the region 9'. The relevant laser configuration parameters are as follows:

- an energy density equal to or greater than 2.4 J/cm ² (considered at the level of the top surface 2a),

- the number of pulses is between 1 and 16, for example 4,

- the duration of each pulse is comprised between 20 and 500 ns, for example equal to 160 ns,

The wavelength of the emitted radiation is comprised between 240 and 700 nm, for example equal to 308 nm.

In this embodiment, the step of activating the dopant in the furnace described with reference to FIG. 2B may be omitted.

After the step of FIG. 6D , the method performs the following steps: forming (e.g., by deposition) an anode metallization 8, such as Ti/AlSiCu or Ni/AlSiCu, in direct electrical contact with the ohmic contact 54 on the 3C-SiC layer 52. Then, a passivation layer 19 is formed on the anode metallization layer 8 to protect the anode metallization. Thus, a corresponding Schottky diode 57 is formed at the interface between the 3C-SiC layer 52 and the anode metallization 8, lateral to the ohmic contact 57.

FIG. 7 illustrates a JBS device 80 according to an embodiment of the present disclosure in a side cross-sectional view of the Cartesian (three-axis) reference system of the X, Y, and Z axes of FIGS. 1 and 4 .

Elements common to the JBS device 1 of FIG. 1 or the JBS device 50 of FIG. 4 are identified with the same reference numerals and need not be described again.

The JBS device 80 comprises: a substrate 3 of N-type 4H-SiC having a first dopant concentration; an (epitaxial) drift layer 2 of N-type 4H-SiC having a second dopant concentration; a cubic silicon carbide (3C-SiC) layer 52 on a surface 2a; a silicon layer 56 on the 3C-SiC layer 52; an anode metallization 8, such as Ti/AlSiCu or Ni/AlSiCu, extending on the silicon layer 56; a passivation layer 19 on the anode metallization 8; a plurality of implanted regions 9' in the drift layer 2, facing the top surface 2a of the drift layer 2, in contact with the 3C-SiC layer 52; and a plurality of implanted regions 9' in the drift layer 2, facing the top surface 2a of the drift layer 2. At the interface of the SiC layer 52; multiple ohmic contacts 84, extending through the 3C-SiC layer 52 and through the silicon layer 56 at the corresponding injection area 9', and forming a corresponding JB element 89 together with the injection area; an edge termination area or guard ring 10 (optional), in particular a P-type injection area, which completely or partially surrounds the JB element 9; an ohmic contact area or layer 6 (for example, nickel silicide), which extends on the surface 3b of the substrate 3; a cathode metallization 7, for example Ti/NiV/Ag or Ti/NiV/Au, which extends on the ohmic contact area 6.

One or more Schottky diodes 87 extend transversely to implant region 9' at the interface between silicon layer 56 and anode metallization 8. In particular, one or more Schottky (semiconductor-metal) junctions are formed by portions of silicon layer 56 in direct electrical contact with corresponding portions of anode metallization 8.

The region of the JBS device 80 including the JB element 89 and the Schottky diode 87 (ie, the region included within the guard ring 10 , if any) is the active region 4 of the JBS device 80 .

8A-8C illustrate intermediate fabrication steps of a JBS device 80 according to an embodiment of the present disclosure in transverse cross-sectional views of a Cartesian (three-axis) reference system of X, Y, and Z axes.

In this case, the steps of forming the cubic silicon carbide (3C—SiC) layer 52 and the silicon layer 56 occur by melting and resolidification (crystallization) of the 4H—SiC material of the drift layer 2 , as already discussed with reference to FIGS. 6A-6D .

As shown in Figure 8A (corresponding to Figure 5A), initially the process results in the formation of the same stack already described in Figure 6A, namely a 3C-SiC layer 52 on the drift layer 2 including 4H-SiC, a silicon layer 56 on the 3C-SiC layer 52, and a carbon-rich (e.g., graphite or including graphite or including a graphite layer) layer 58 on the silicon layer 56.

8B , a step is performed to selectively remove the carbon-rich layer 58 without removing the underlying silicon layer 56. This step is performed, for example, by a plasma etching process in an O ₂ environment. Other chemicals or methods for selectively removing graphite may be used.

Then, in FIG8C , an ohmic contact 84 is formed through the silicon layer 56 and the 3C-SiC layer 52 at the implantation region 9 ′ (and possibly at the guard ring 10 , if any). To this end, the process already described with reference to FIGS. 3A-3C is used, appropriately modified to make it suitable for the case discussed here. In particular, in this case, the mask 13 is formed on the silicon layer 56 and the through opening 13 a extends until it reaches the silicon layer 56. Therefore, the metal layer 14 extends until it reaches the silicon layer 56.

The formation of the ohmic contact involves depositing nickel inside the opening 13a. A subsequent high temperature thermal treatment (between 700°C and 1200°C for a time interval of 1 minute to 120 minutes) allows the formation of an ohmic contact 84 of nickel silicide by chemical reaction between the nickel deposited in the layer 52 at the opening 13a and the silicon.

In another form of implementation, the openings 13a extend to the 3C-SiC52 layer or the drift layer 2 at the implantation region 9'. The formation of the ohmic contacts comprises the deposition of nickel in these openings 13a.

By using a properly configured laser source, it is possible to simultaneously melt the surface portion of the drift layer 2 (thereby forming the 3C-SiC layer 52 and the silicon layer 56 as described above) and activate the dopants implanted in the region 9'. The relevant laser configuration parameters are as follows:

- an energy density equal to or greater than 2.4 J/cm ² (considered at the level of the top surface 2a),

- the number of pulses is between 1 and 16, for example 4,

- the duration of each pulse is comprised between 20 and 500 ns, for example equal to 160 ns,

The wavelength of the emitted radiation is comprised between 240 and 700 nm, for example equal to 308 nm.

In this embodiment, the step of activating the dopant in the furnace described with reference to FIG. 2B may be omitted.

After the step of FIG. 8C , the method performs the following steps: forming (e.g., by deposition) an anode metallization 8, such as Ti/AlSiCu or Ni/AlSiCu, in direct electrical contact with the ohmic contact 84 on the silicon layer 56. Then, a passivation layer 19 is formed on the anode metallization layer 8 to protect the anode metallization. Thus, a corresponding Schottky diode 87 is formed at the interface between the silicon layer 56 and the anode metallization 8, lateral to the ohmic contact 84.

FIG. 9 shows an electronic device (specifically a JBS) 100 device according to another embodiment in a side cross-sectional view of the Cartesian (tri-axial) X, Y, Z reference system of FIG. 7 .

Elements common to the JBS80 device of FIG. 7 are denoted by the same reference numerals and need not be described again in detail.

The JBS device 100 includes: a substrate 3 of N-type 4H-SiC having a first dopant concentration; a drift (epitaxial) layer 2 of N-type 4H-SiC having a second dopant concentration; a cubic silicon carbide (3C-SiC) layer 52 on a surface 2a; a silicon layer 56 on the 3C-SiC layer 52; a carbon-rich layer 58 on the silicon layer 56; an anode metallization layer 8 extending on the carbon-rich layer 58, such as Ti/AlSiCu or Ni/AlSiCu; a passivation layer 19 on the anode metallization 8; a plurality of implanted regions 9' in the drift layer 2, facing a top surface 2a of the drift layer 2; a, at the interface with the 3C-SiC layer 52; multiple ohmic contacts 104, extending through the 3C-SiC layer 52, the silicon layer 56 and the carbon-rich layer 58 at the corresponding implantation area 9', and forming a corresponding JB element 89 with the implantation area; an edge termination area or guard ring 10 (optional) completely or partially surrounding the JB element 9, in particular a P-type implantation area; an ohmic contact area or layer 6 (e.g., nickel silicide) extending on the surface 3b of the substrate 3; a cathode metallization 7 such as Ti/NiV/Ag or Ti/NiV/Au extending on the ohmic contact area 6.

One or more Schottky diodes 87 extend transversely to the implanted region 9' at the interface between the carbon rich layer 58 and the anode metallization 8. Specifically, one or more Schottky (semiconductor-metal) junctions are formed by portions of the carbon rich layer 58 that are in direct electrical contact with corresponding portions of the anode metallization 8. Note that the 3C-SiC 52 and silicon 56 layers and the carbon rich layer 58 have the doping (N-type) of the drift layer 2 from which they are formed and are therefore conductive.

The region of the JBS device 100 including the JB element 89 and the Schottky diode 87 (ie, the region contained within the guard ring 10 , when present) is the active region 4 of the JBS device 100 .

The carbon-rich layer 58 between the metallization layer 8 and the silicon layer 56 has the function of preventing metal ions or metal contaminants from diffusing from the metallization layer 8 to the silicon layer 56 , and from the silicon layer to the 3C—SiC layer 52 , and thus to the drift layer 2 .

10A-10D illustrate intermediate fabrication steps of a JBS device 100 according to an embodiment in side cross-sectional views of a Cartesian (three-axis) reference system of X, Y, and Z axes.

In this case, the steps of forming the cubic silicon carbide (3C-SiC) layer 52, the silicon layer 56 and the carbon rich layer 58 occur by melting and resolidification (crystallization) of the 4H-SiC material of the drift layer 2, as discussed above with reference to FIGS. 6A-6D and 8A.

As shown in FIG. 10A (which corresponds to FIG. 6A and FIG. 8A ), initially the process results in the formation of the previously described stack (“stack”), i.e., including a 3C-SiC layer 52 on the 4H-SiC drift layer 2, a silicon layer 56 on the 3C-SiC layer 52, and a carbon-rich layer 58 (e.g., graphite or including graphite or including a graphite layer) on the silicon layer 56.

Then, in FIG. 10B , an ohmic contact 104 is formed across the carbon-rich layer 58, the silicon layer 56, and the 3C-SiC layer 52 at the implanted region 9 ' (and the guard ring 10, if present). The process already described with reference to FIGS. 3A-3C is used for this purpose, appropriately modified to adapt it to the case discussed here. Specifically, in this case, a mask 13 is formed on the carbon-rich layer 58, and a through opening 13a extends to expose the carbon-rich layer 58.

10C , a subsequent high temperature thermal treatment (between 700° C. and 1200° C. for a time interval of 1 to 120 minutes) allows the formation of a nickel silicide ohmic contact 104 by chemical reaction between the deposited nickel and the silicon present in layer 58 .

Alternatively, the through openings 13a extend through the carbon-rich layer 58 until they reach the silicon layer 56; or, the through openings 13a extend through the carbon-rich layer 58 and the silicon layer 56 until they reach the 3C-SiC layer 52; or, the through openings 13a extend through the carbon-rich layer 58, the silicon layer 56 and the 3C-SiC layer 52 until they reach the implantation region 9' in the drift layer 2. In all these possible embodiments, after a high-temperature thermal treatment (at a time interval between 700°C and 1200°C for 1 minute to 120 minutes), the nickel deposited in the through openings 13a forms an ohmic contact 104 of nickel silicide by a chemical reaction between the deposited nickel and the silicon present in the layers 56, 52, 2 (depending on the respective embodiment).

By using a properly configured laser source, it is possible to simultaneously melt the surface portion of the drift layer 2 (in order to form the 3C-SiC layer 52, the silicon layer 56 and the carbon-rich layer 58 as described above) and activate the dopant species implanted in the region 9'. The relevant laser configuration parameters are as follows:

- an energy density of or greater than 2.4 J/cm ² (considered at the level of the upper surface 2a),

- the number of pulses is between 1 and 16, for example 4,

- the duration of each pulse is between 20 and 500 ns, for example, equal to 160 ns,

The wavelength of the emitted radiation is between 240 and 700 nm, for example equal to 308 nm.

In this embodiment, the furnace dopant activation step described with reference to FIG. 2B may be omitted.

After the step in FIG. 10B , a step of forming (e.g., by deposition) an anode metallization 8, for example made of Ti/AlSiCu or Ni/AlSiCu, is performed; the anode metallization layer 8 is formed on the carbon-rich layer 58 and in direct electrical contact with the ohmic contact 104. Then, a passivation layer 19 is formed on the anode metallization layer 8 to protect the anode metallization. Thus, a corresponding Schottky diode 87 is formed at the interface between the carbon-rich layer 58 and the anode metallization 8, transverse to the ohmic contact 104. This produces the device 100 of FIG. 9 .

According to another embodiment shown in FIG. 11 , the formation of a stack of a 3C-SiC layer 52 , a silicon layer 56 , and a carbon-rich layer 58 may be used to fabricate a gate terminal of a transistor (eg, MOSFET).

After forming the stack 3C-SiC52, silicon 56 and carbon-rich layer 58, a step of removing the carbon-rich layer 58 is performed at least at the selected area where the gate terminal of the electronic device is to be formed. For example, the carbon-rich layer 58 is removed in the area between two implanted areas 9', exposing the underlying silicon layer 56.

A step is then performed to oxidize the portion of the silicon layer 56 thus exposed to form silicon oxide (SiO ₂ ), namely, the portion 56 ′ shown in FIG. 11 .

In an alternative embodiment, the carbon rich layer 58 is completely removed, and the silicon layer 56 is patterned, for example by a photolithography process, so that the silicon layer 56 remains only between the two implanted regions 9'. The silicon layer 56 between the two implanted regions 9' is then oxidized to form the portion 56'.

The 3C-SiC layer 52 may also be removed at the sides of the portion 56' and remain underneath the portion 56'.

The oxidized portion 56' of the silicon layer 56 has the function of a gate oxide. The oxidized portion 56' extends between the two implanted regions 9' in a top view on the plane XY, optionally partially overlapping parts of the two implanted regions 9'.

Thus, a metal layer having the function of gate metallization 110 is formed on the oxidized portion 56 ′.

The source region and the drain region of the MOSFET may be formed by performing N-type implantation within the P-type implantation region 9 ′ in a manner that will be apparent to a person skilled in the art.

During use, the 3C-SiC layer 52 below the oxidized portion 56' may participate in the formation of a conductive channel.

By examining the features of the present invention provided in light of this specification, the advantages it provides will become apparent.

In particular, the advantages of the 4H-SiC substrate and the advantages resulting from the reduced band gap value of 3C-SiC or silicon (in various embodiments) can be fully utilized for forming the JB element and the Schottky contact, as described above.

Finally, it is clear that modifications and variations may be carried out in what is described and illustrated herein without departing from the scope of the present invention as defined in the appended claims.

For example, the step of melting 4H-SiC described with reference to Figures 6A and 8A can be performed without the implantation region 9'. Therefore, in this case, the epitaxial layer 2 does not accommodate the implantation region 9', which is formed as follows:

i) after the step of removing the silicon 56 and carbon 58 layers (ie, immediately after the step of FIG. 6C for various embodiments); or

ii) after the step of removing the carbon-rich layer 58 (ie, immediately after the step of FIG. 8B for various embodiments).

Furthermore, the present invention is not limited to the fabrication of 3C-SiC JBS devices, but extends to forming ohmic contacts in common electronic devices such as MOSFET (especially vertical channel MOSFET), IGBT, JFET, DMOS, Merged PN Schottky (MPS) diodes, etc. Due to the different electron mobility between 3C-SiC and 4H-SiC, forming the channel of the vertical MOSFET in the 3C-SiC layer (rather than in other SiC polytypes, such as 4H-SiC) brings considerable advantages in terms of the output resistance of the device.

In one embodiment, a method for manufacturing an electronic device can be summarized as including the following steps: forming at least one implanted region having a second conductivity (P) opposite to the first conductivity (N) on a front side of a 4H-SiC solid body having a first conductivity (N); forming a 3C-SiC layer on the front side; and forming an ohmic contact region in the 3C-SiC layer, the ohmic contact region extending through the entire thickness of the 3C-SiC layer until reaching the implanted region.

Forming the 3C-SiC layer may include performing a step of growing 3C-SiC by a VLS technique or a SE technique.

Forming the 3C-SiC layer may include heating at least a portion of the front side of the solid body by a laser beam, at least to the melting temperature of the 4H-SiC material; and allowing the molten portion of the solid body to cool and crystallize, thereby forming a stack comprising: the 3C-SiC layer in contact with the solid body, a silicon layer on the 3C-SiC layer, and a carbon-rich layer on the silicon layer.

The method may further include the step of completely removing the carbon-rich layer and the silicon layer to expose the 3C-SiC layer.

Completely removing the carbon rich layer and the silicon layer may include performing the steps of oxidizing the silicon layer and the carbon rich layer, and etching the silicon oxide layer and oxidizing the carbon rich layer.

The method may further include the step of completely removing the carbon rich layer to expose the silicon layer.

Completely removing the carbon rich layer may include performing a selective etch to remove the carbon rich layer leaving the silicon layer.

The method may further include the step of forming an ohmic contact region throughout the thickness of the silicon layer until reaching the implantation region.

The method may further include the step of forming a metal layer on the 3C-SiC layer and the ohmic contact region, thereby forming a Schottky diode between the metal layer and the 3C-SiC and simultaneously forming a junction barrier JB diode between the metal layer and the ohmic contact region.

The method may further include the steps of forming a first electrical terminal common to the JB diode and the Schottky diode at the metal layer; and forming a second electrical terminal common to the JB diode and the Schottky diode at a rear side opposite to the front side of the solid state.

The electronic device may be one of: a merged PiN Schottky MPS device; a junction barrier Schottky JBS device; a MOSFET; an IGBT; a JFET; or a DMOS.

The electronic device can be summarized as including a solid body of 4H-SiC having a first conductivity (N); at least one implanted region having a second conductivity (P) opposite to the first conductivity (N); a 3C-SiC layer on the front side; and an ohmic contact region through the entire thickness of the 3C-SiC layer until reaching the implanted region.

The device may further include a silicon layer on the 3C-SiC layer, the ohmic contact region also extending through the entire thickness of the silicon layer until reaching the implantation region.

The solid body may include a 4H-SiC substrate; and a 4H-SiC epitaxial layer on the substrate, wherein the epitaxial layer is a drift layer of the electronic device.

The first conductivity may be N-type and the second conductivity is P-type.

The device may further include a metal layer on the 3C-SiC layer and on the ohmic contact region, so that a Schottky diode is formed between the metal layer and the 3C-SiC layer, and a junction barrier JB diode is formed between the metal layer and the ohmic contact region.

The device may also include a first electrical terminal common to the JB diode and the Schottky diode at the metal layer; and a second electrical terminal common to the JB diode and the Schottky diode at a back side opposite to the front side of the solid state.

The electronic device may be one of: a merged PiN Schottky MPS device; a junction barrier Schottky JBS device; a MOSFET; an IGBT; a JFET; or a DMOS.

One aspect of the present disclosure provides a method for manufacturing an electronic device, the method comprising: forming at least one implantation region having a second conductivity opposite to the first conductivity at a front side of a solid body of 4H-SiC having a first conductivity; heating at least a portion of the front side of the solid body using a laser beam to at least reach the melting temperature of the 4H-SiC material; allowing the melted portion of the solid body to cool and crystallize, thereby forming a stack of superimposed layers, the stack of superimposed layers comprising a 3C-SiC layer in contact with the solid body, a silicon layer on the 3C-SiC layer, and a carbon-rich layer on the silicon layer; forming an ohmic contact region to pass through the stack until reaching the implantation region; and forming a first electrical terminal of a conductive material above the carbon-rich layer and in direct contact with the carbon-rich layer.

According to one or more embodiments, wherein the step of forming the first electrical terminal includes depositing a metal material over and in direct contact with the carbon rich layer and the ohmic contact region.

According to one or more embodiments, forming the first electrical terminal includes simultaneously forming a Schottky diode between the first electrical terminal and the carbon rich layer and a junction barrier diode between the first electrical terminal and the ohmic contact region.

According to one or more embodiments, wherein the first electrical terminal is common to the junction barrier diode and the Schottky diode, the method further includes forming a second electrical terminal common to the junction barrier diode and the Schottky diode at a rear side opposite to the front side of the solid body.

According to one or more embodiments, the method further includes the steps of removing a selective portion of the carbon-rich layer that extends laterally to the implantation region, thereby exposing a corresponding portion of the underlying silicon layer; performing oxidation on the exposed portion of the silicon layer, thereby forming an oxidized portion; and forming metallization over and in contact with the oxidized portion of the silicon layer.

According to one or more embodiments, wherein the oxidized portion of the silicon layer and the metallization form a gate terminal of an electronic device.

According to one or more embodiments, the method also includes: forming an additional implantation region having a second conductivity at the front side of the solid body, the additional implantation region extending at a distance from the implantation region, wherein the removed selective portion of the carbon-rich layer extends between the implantation region and the additional implantation region, and wherein one between the implantation region and the additional implantation region accommodates a conductive source region of the electronic device, and the other between the implantation region and the additional implantation region accommodates a conductive drain region of the electronic device; and before performing the oxidation step, removing a portion of the silicon layer except for the portion of the silicon layer extending between the implantation region and the additional implantation region.

Another aspect of the present disclosure provides a method for manufacturing an electronic device, the method comprising: forming at least one implantation region having a second conductivity opposite to the first conductivity at a front side of a solid body of 4H-SiC having a first conductivity; forming a 3C-SiC layer on the front side; forming an ohmic contact region in the 3C-SiC layer, the ohmic contact region extending through the entire thickness of the 3C-SiC layer until reaching the implantation region, wherein forming the 3C-SiC layer comprises: heating at least a portion of the front side of the solid body by a laser beam to at least reach the melting temperature of the 4H-SiC material; and cooling and crystallizing the melted portion of the solid body to form a stack of superimposed layers, the stack of superimposed layers comprising: a 3C-SiC layer in contact with the solid body, a silicon layer on the 3C-SiC layer, and a carbon-rich layer on the silicon layer, removing the carbon-rich layer comprising one of the following: performing a step of oxidizing the carbon-rich layer, and a subsequent step of etching the oxidized carbon-rich layer, or performing etching to selectively remove the carbon-rich layer.

According to one or more embodiments, the method further includes completely removing the silicon layer, thereby exposing the 3C-SiC layer.

According to one or more embodiments, wherein the carbon-rich layer is graphitic, includes graphite, includes one or more graphite layers, includes graphene, or includes graphite and graphene.

In accordance with one or more embodiments, a method includes a Schottky diode having a carbon rich layer and a junction barrier diode having an ohmic contact region.

According to one or more embodiments, wherein the first electrical terminal is common to the junction barrier diode and the Schottky diode, the electronic device further includes a second electrical terminal common to the junction barrier diode and the Schottky diode at a rear side opposite to the front side of the solid state body.

According to one or more embodiments, the electronic device is one of: a Merged PiN Schottky MPS device; a Junction Barrier Schottky JBS device; a MOSFET; an IGBT; a JFET; or a DMOS.

According to the present invention, there is provided a method for manufacturing an electronic device and an electronic device as defined in the accompanying claims.

In one embodiment, a method for manufacturing an electronic device includes forming at least one implanted region having a second conductivity opposite to the first conductivity on a front side of a 4H-SiC solid body having a first conductivity. The method includes forming a 3C-SiC layer on the front side, and forming an ohmic contact region in the 3C-SiC layer extending through the entire thickness of the 3C-SiC layer until reaching the implanted region.

In one embodiment, an electronic device includes a 4H-SiC solid body having a first conductivity. The electronic device includes at least one implanted region having a second conductivity opposite to the first conductivity extending on a front side of the solid body. The electronic device includes a 3C-SiC layer on the front side and an ohmic contact region through the entire thickness of the 3C-SiC layer until reaching the implanted region.

These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims (10)

1. An electronic device, comprising: A solid body of hexagonal polytype silicon carbide having a first conductivity; at least one implanted region extending at a front side of the solid body, the at least one implanted region having a second conductivity opposite to the first conductivity; a cubic polytype silicon carbide layer on the front side; a silicon layer on the cubic polytype silicon carbide layer; a carbon-containing layer on the silicon layer; an ohmic contact region extending through the entire thickness of the cubic polytype silicon carbide layer, the silicon layer, and the carbon-containing layer until reaching the implantation region; and A conductive first electrical terminal is located above the carbon-containing layer and directly contacts the carbon-containing layer. 2 . The electronic device according to claim 1 , wherein the carbon-containing layer is a carbon-rich layer. 3. The electronic device of claim 2, wherein the solid body is hexagonal polytype silicon carbide and the carbon-rich layer is graphite. 4 . The electronic device according to claim 2 , wherein the carbon-rich layer comprises one or more graphite layers. 5 . The electronic device according to claim 2 , wherein the carbon-rich layer comprises graphene, or comprises graphite and graphene. 6 . The electronic device according to claim 3 , wherein the first electrical terminal forms a Schottky diode having the carbon rich layer and a junction barrier diode having the ohmic contact region. 7. The electronic device according to claim 6 is characterized in that the first electrical terminal is shared by the junction barrier diode and the Schottky diode, and the electronic device also includes a second electrical terminal shared by the junction barrier diode and the Schottky diode at a rear side opposite to the front side of the solid-state body. 8. The electronic device according to any one of claims 3 to 5, characterized in that the electronic device is one of the following: a merged PiN Schottky MPS device; a junction barrier Schottky JBS device; a MOSFET; an IGBT; a JFET; or a DMOS. 9. An electronic device, comprising: A solid body of hexagonal polytype silicon carbide having a first conductivity; a first implant region extending at the front side of the solid body, the first implant region having a second conductivity opposite to the first conductivity, the first implant region comprising a source terminal; a second implant region having the second conductivity extending at a distance from the first implant region at the front side of the solid body, the second implant region comprising a drain terminal; a cubic polytype silicon carbide layer on the front side; a gate dielectric of silicon oxide on the cubic polytype silicon carbide layer between the first implant region and the second implant region; and A metal electrical gate terminal is located above and in direct contact with the gate dielectric. 10. The electronic device according to claim 9, characterized in that it comprises one or more of the following: a merged PiN Schottky MPS device; a junction barrier Schottky JBS device; a MOSFET; an IGBT; a JFET; or a DMOS.