CN221708703U - Package substrate and package substrate assembly - Google Patents

Abstract

A package substrate and a package substrate assembly. The packaging substrate comprises a substrate body and an intermediate layer, wherein the substrate body comprises a dielectric layer, a first outer conductive circuit layer, a second outer conductive circuit layer and an inner conductive circuit layer, the inner conductive circuit layer is embedded in the dielectric layer, the inner conductive circuit layer comprises a first welding pad, the dielectric layer comprises a first surface and a second surface which are oppositely arranged, the first outer conductive circuit layer and the second outer conductive circuit layer are respectively arranged on the first surface and the second surface, the dielectric layer is provided with a groove which penetrates through the second surface and exposes the first welding pad, and the intermediate layer is accommodated in the groove and is electrically connected with the first welding pad.

Description

Package substrate and package substrate assembly

Technical Field

The present application relates to a semiconductor packaging technology, and more particularly to a packaging substrate and a packaging substrate assembly.

Background Art

With the development of electronic technology, users have higher and higher requirements for the performance of electronic devices, which has led to an increase in the number of transistors in electronic devices, which has led to the increasing size of chip packages. However, as electronic devices continue to develop towards integration, chip packages in electronic devices have to develop towards miniaturization. Existing chip packages use the 3D-SiP (System-in-package) packaging process to stack multiple chips on a packaging substrate to achieve miniaturization. However, the thickness of the chip package is relatively thick, which is not conducive to thinning.

Utility Model Content

In view of this, the present application provides a packaging substrate and a packaging substrate assembly that are conducive to thinning.

An embodiment of the present application provides a packaging substrate, including a substrate body and an intermediary layer, the substrate body including a dielectric layer, a first outer conductive circuit layer, a second outer conductive circuit layer and an inner conductive circuit layer, the inner conductive circuit layer is embedded in the dielectric layer, the inner conductive circuit layer includes a first welding pad, the dielectric layer includes a first surface and a second surface arranged opposite to each other, the first outer conductive circuit layer and the second outer conductive circuit layer are arranged on the first surface and the second surface respectively, the dielectric layer is provided with a groove penetrating the second surface and exposing the first welding pad, the intermediary layer is accommodated in the groove and is electrically connected to the first welding pad.

In some embodiments, the groove includes a bottom surface and side surfaces, the bottom surface and the side surfaces surround the groove, and the bottom surface is flush with the surface of the first pad.

In some embodiments, the interposer has no contact with the side surfaces.

In some embodiments, the package substrate further includes a bonding layer, which fills a gap between the interposer and the groove and bonds the interposer and the substrate body.

In some embodiments, a second pad is disposed on a surface of the interposer facing the bottom surface, and the first pad is welded to the second pad.

In some embodiments, the first conductive circuit layer includes a first connection pad, and the package substrate further includes a first solder mask layer, and the first solder mask layer is disposed on the first conductive circuit layer and exposes the first connection pad.

In some embodiments, the second outer conductive circuit layer includes a second connection pad, and the package substrate further includes a second solder mask layer, and the second solder mask layer is disposed on the second outer conductive circuit layer and exposes the second connection pad.

In some embodiments, a third connection pad is disposed on a surface of the interposer exposed outside the groove, and a surface of the second connection pad is flush with a surface of the third connection pad.

In some embodiments, the dielectric layer includes a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer, the inner conductive circuit layer includes a first inner conductive circuit layer, a second inner conductive circuit layer and a third inner conductive circuit layer, and the first dielectric layer, the first inner conductive circuit layer, the second dielectric layer, the second inner conductive circuit layer, the third dielectric layer, the third inner conductive circuit layer and the fourth dielectric layer are stacked in sequence.

The packaging substrate provided in the present application reduces the overall thickness of the packaging substrate assembly by opening a groove in the substrate body and accommodating the intermediate layer in the groove, which is conducive to thinning; and by configuring the second connection pad and the third connection pad, a piece of packaging substrate can carry multiple electronic components, which is conducive to integration.

BRIEF DESCRIPTION OF THE DRAWINGS

1 to 6 are cross-sectional schematic diagrams of a production process of a circuit substrate provided in one embodiment of the present application.

FIG. 7 is a schematic cross-sectional view of the circuit substrate shown in FIG. 6 after a groove is formed.

FIG. 8 is a cross-sectional schematic diagram showing a circuit substrate shown in FIG. 7 after a second outer conductive circuit layer is formed.

FIG. 9 is a schematic cross-sectional view of a substrate body provided in one embodiment of the present application.

FIG. 10 is a cross-sectional schematic diagram showing a substrate body shown in FIG. 9 after an interposer is disposed on the substrate body.

FIG. 11 is a cross-sectional schematic diagram of a packaging substrate assembly provided in accordance with an embodiment of the present application.

Main component symbols

Carrier board 11

Release film 12

Metal layer 13

First outer conductive circuit layer 14

First connection pad 141

First dielectric layer 21

First inner conductive circuit layer 22

First conductive via 23

The second dielectric layer 31

Second inner conductive circuit layer 32

The third dielectric layer 41

The third inner conductive circuit layer 42

First pad 421

Fourth dielectric layer 51

First surface 100a

Second surface 100b

Groove 110

Bottom 111

Side 112

Second outer conductive circuit layer 52

First solder mask 61

Second solder mask 62

Base body 100

Third connection pad 71

Second pad 72

Adhesive layer 80

Package substrate 200

Package Substrate Assembly 300

Electronic components 310

The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings.

DETAILED DESCRIPTION

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined or replaced with each other.

An embodiment of the present application provides a method for manufacturing a packaging substrate, comprising the following steps.

Step S1, providing a circuit substrate.

Referring to FIGS. 1 to 6 , the method for manufacturing a circuit substrate includes the following steps: as shown in FIG. 1 , a release film 12 is attached to the surface of a carrier board 11, and a metal layer 13 is formed on the surface of the release film 12 away from the carrier board 11; as shown in FIG. 2 , a first outer conductive circuit layer 14 is formed by etching the metal layer, and the first outer conductive circuit layer 14 includes a plurality of first connection pads 141; as shown in FIG. 3 , a first dielectric layer 21 is pressed onto the surface of the first outer conductive circuit layer 14, a plurality of first conductive holes 23 are formed in the first dielectric layer 21, and a first inner conductive circuit layer 22 is formed on the surface of the first dielectric layer 21 away from the first outer conductive circuit layer 14, each first conductive hole 23 penetrates the first dielectric layer 21 and electrically connects the first inner conductive circuit layer 22 and the first outer conductive circuit layer 14; as shown in FIG. 4 , a second dielectric layer 31 is pressed onto the surface of the first inner conductive circuit layer 22, and a plurality of first conductive holes 23 are formed in the second dielectric layer 31; A second inner conductive circuit layer 32 is formed on the surface of the second dielectric layer 31 away from the first inner conductive circuit layer 22, each second conductive hole penetrates the second dielectric layer 31 and electrically connects the second inner conductive circuit layer 32 and the first inner conductive circuit layer 22; as shown in FIG. 5 , a third dielectric layer 41 is pressed onto the surface of the second inner conductive circuit layer 32, a plurality of third conductive holes 43 are formed in the third dielectric layer 41, and a third inner conductive circuit layer 42 is formed on the surface of the third dielectric layer 41 away from the second inner conductive circuit layer 32, each third conductive hole 43 penetrates the third dielectric layer 41 and electrically connects the second inner conductive circuit layer 32 and the third inner conductive circuit layer 42, and the third inner conductive circuit layer 42 includes a plurality of first pads 421; please refer to FIG. 6 , a fourth dielectric layer 51 is pressed onto the surface of the third inner conductive circuit layer 42, and the carrier 11 and the release film 12 are removed to form a circuit substrate 101.

Please refer to FIG. 6 , the circuit substrate 101 includes a dielectric layer, an inner conductive circuit layer embedded in the dielectric layer, and a first outer conductive circuit layer 14 disposed on the surface of the dielectric layer. The dielectric layer includes a first surface 100a and a second surface 100b disposed opposite to each other. The first outer conductive circuit layer 14 is disposed on the first surface 100a and includes a plurality of first connection pads 141, and the first connection pads 141 are used to connect to the circuit board (not shown). In this embodiment, the first outer conductive circuit layer 14 is embedded in the dielectric layer and exposed on the first surface 100a, and the surface of the first outer conductive circuit layer 14 facing away from the inner conductive circuit layer is flush with the first surface 100a. In other embodiments, the first outer conductive circuit layer 14 is convexly disposed on the first surface 100a. The inner conductive circuit layer is electrically connected to the first outer conductive circuit layer 14 through a conductive hole. The inner conductive circuit layer includes a plurality of first solder pads 421.

Specifically, the dielectric layer includes a first dielectric layer 21, a second dielectric layer 31, a third dielectric layer 41 and a fourth dielectric layer 51, and the inner conductive circuit layer includes a first inner conductive circuit layer 22, a second inner conductive circuit layer 32 and a third inner conductive circuit layer 42. The third inner conductive circuit layer 42 includes a plurality of first pads 421. The first dielectric layer 21, the first inner conductive circuit layer 22, the second dielectric layer 31, the second inner conductive circuit layer 32, the third dielectric layer 41, the third inner conductive circuit layer 42 and the fourth dielectric layer 51 are stacked in sequence. The surface of the first dielectric layer 21 facing away from the first inner conductive circuit layer 22 is used as the first surface 100a. The surface of the fourth dielectric layer 51 facing away from the third inner conductive circuit layer 42 is used as the second surface 100b. The first inner conductive circuit layer 22 and the first outer conductive circuit layer 14 are electrically connected through a plurality of first conductive holes 23 penetrating the first dielectric layer 21. The first inner conductive circuit layer 22 and the second inner conductive circuit layer 32 are electrically connected through a plurality of second conductive vias penetrating the second dielectric layer 31 . The second inner conductive circuit layer 32 and the third inner conductive circuit layer 42 are electrically connected through a plurality of third conductive vias 43 penetrating the third dielectric layer 41 .

The materials of the first dielectric layer 21, the second dielectric layer 31, the third dielectric layer 41 and the fourth dielectric layer 51 can be selected from at least one of polyimide (PI), polyethylene terephthalate (PET), polytetrafluoroethylene (PTFE), polyamide (PA), polypropylene (PP), polyethylene (PE), liquid crystal polymer (LCP), polyvinyl chloride (PVC), etc. The materials of the first outer conductive circuit layer 14, the first inner conductive circuit layer 22, the second inner conductive circuit layer 32 and the third inner conductive circuit layer 42 can be copper, gold, silver, etc.

Step S2, please refer to FIG. 7, a groove 110 is formed on the dielectric layer, which penetrates the second surface 100b and exposes a plurality of first pads 421. Specifically, the groove 110 penetrates the fourth dielectric layer 51, and a plurality of first pads 421 are exposed in the groove 110. The groove 110 can be formed by laser drilling or mechanical drilling. The groove 110 includes a bottom surface 111 and a side surface 112, and the bottom surface 111 and the side surface 112 surround the groove 110. The surface of the first pad 421 is flush with the bottom surface 111.

Step S3, referring to FIG8 , forms a second outer conductive circuit layer 52 on the second surface 100b of the dielectric layer. Specifically, dry film lamination, exposure and development, and copper electroplating can be performed in sequence on the second surface 100b to form the second outer conductive circuit layer 52. The second outer conductive circuit layer 52 includes a plurality of second connection pads 521.

In step S4 , please refer to FIG. 9 , a first solder mask layer 61 is formed on the first outer conductive circuit layer 14 , and a second solder mask layer 62 is formed on the second outer conductive circuit layer 52 , to obtain the substrate body 100 .

Please refer to FIG. 9 , the substrate body 100 includes a dielectric layer, an inner conductive circuit layer, a first outer conductive circuit layer 14, a second outer conductive circuit layer 52, a first solder mask 61, and a second solder mask 62. The inner conductive circuit layer is embedded in the dielectric layer. The first outer conductive circuit layer 14 is disposed on the first surface 100a of the dielectric layer, the first solder mask 61 is disposed on the surface of the first outer conductive circuit layer 14 away from the dielectric layer, and the first connection pad 141 of the first outer conductive circuit layer 14 is exposed outside the first solder mask 61. The second outer conductive circuit layer 52 is disposed on the second surface 100b of the dielectric layer, the second solder mask 62 is disposed on the surface of the second outer conductive circuit layer 52 away from the dielectric layer, and the second connection pad 521 of the second outer conductive circuit layer 52 is exposed outside the second solder mask 62.

Step S5, referring to FIG. 10 , the interposer 70 is placed in the groove 110, and the interposer 70 is electrically connected to the first pad 421. The interposer 70 is not in contact with the second outer conductive circuit layer 52. In this embodiment, there is a gap between the interposer 70 and the side surface 112 of the groove 110. That is, the interposer 70 is not in contact with the side surface 112 of the groove 110.

In this embodiment, the interposer 70 is a silicon interposer. The silicon interposer has a plurality of conductive through silicon vias (TSVs) and a line redistribution layer (RDL). The surface of the interposer 70 exposed outside the groove 110 has a plurality of third connection pads 71, and the surface of the interposer 70 facing the bottom surface 111 of the groove 110 has a plurality of second pads 72, and the third connection pads 71 and the second pads 72 are electrically connected through the line redistribution layer and the conductive silicon through vias. The surface of the third connection pad 71 is flush with the surface of the second connection pad 521. The second pad 72 is welded to the first pad 421 to realize the electrical connection between the interposer 70 and the substrate body 100.

In step S6 , please refer to FIG. 10 , an adhesive is injected into the gap between the interposer 70 and the groove 110 to form an adhesive layer 80 , thereby obtaining a package substrate 200 .

Please refer to Fig. 10, the package substrate 200 includes a substrate body 100, an interposer 70 and an adhesive layer 80. The substrate body 100 is provided with a groove 110 that penetrates the second surface 100b and the second outer conductive circuit layer 52 and exposes the first pad 421. The interposer 70 is accommodated in the groove 110 of the substrate body 100 and is electrically connected to the first pad 421. The interposer 70 is bonded to the bottom surface 111 and the side surface 112 of the groove 110 through the adhesive layer 80.

Referring to FIG. 11 , an embodiment of the present application provides a package substrate assembly 300, including a package substrate 200 and a plurality of electronic components 310. Each electronic component 310 is connected to a second connection pad 521 and a third connection pad 71 to achieve electrical connection between the electronic component 310 and the substrate body 100 and the interposer 70. The electronic component 310 is an active component, a passive component, or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor.

The packaging substrate 200 provided in the embodiment of the present application reduces the overall thickness of the packaging substrate assembly 300 by opening a groove 110 in the substrate body 100 and accommodating the intermediate layer 70 in the groove 110, which is conducive to thinning; and by configuring the second connection pad 521 and the third connection pad 71, a piece of packaging substrate 200 can carry multiple electronic components 310, which is conducive to integration.

The above is only the preferred implementation mode of the present application, and is not any form of limitation on the present application. Although the present application has been disclosed as the preferred implementation mode as above, it is not used to limit the present application. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent implementation modes without departing from the scope of the technical solution of the present application. However, any simple modification, equivalent change and modification made to the above implementation modes based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims (10)

1. The packaging substrate is characterized by comprising a substrate body and an intermediate layer, wherein the substrate body comprises a dielectric layer, a first outer conductive circuit layer, a second outer conductive circuit layer and an inner conductive circuit layer, the inner conductive circuit layer is embedded in the dielectric layer, the inner conductive circuit layer comprises a first welding pad, the dielectric layer comprises a first surface and a second surface which are oppositely arranged, the first outer conductive circuit layer and the second outer conductive circuit layer are respectively arranged on the first surface and the second surface, the dielectric layer is provided with a groove which penetrates through the second surface and exposes the first welding pad, and the intermediate layer is accommodated in the groove and is electrically connected with the first welding pad.

2. The package substrate of claim 1, wherein the recess comprises a bottom surface and a side surface, the bottom surface and the side surface surrounding to form the recess, the bottom surface being flush with a surface of the first pad.

3. The package substrate of claim 2, wherein the interposer is not in contact with the side.

4. The package substrate of claim 3, further comprising an adhesive layer filling in the gap between the interposer and the recess and bonding the interposer and the substrate body.

5. The package substrate of claim 2, wherein a surface of the interposer facing the bottom surface is provided with a second bonding pad, and the first bonding pad is bonded to the second bonding pad.

6. The package substrate of claim 1, wherein the first outer conductive trace layer comprises a first connection pad, the package substrate further comprising a first solder mask layer disposed on the first outer conductive trace layer and exposing the first connection pad.

7. The package substrate of claim 1, wherein the second outer conductive trace layer comprises a second connection pad, the package substrate further comprising a second solder mask layer disposed on the second outer conductive trace layer and exposing the second connection pad.

8. The package substrate of claim 7, wherein a surface of the interposer exposed outside the recess is provided with a third connection pad, and a surface of the second connection pad is flush with a surface of the third connection pad.

9. The package substrate of claim 1, wherein the dielectric layer comprises a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer, the inner conductive trace layer comprises a first inner conductive trace layer, a second inner conductive trace layer, and a third inner conductive trace layer, and the first dielectric layer, the first inner conductive trace layer, the second dielectric layer, the second inner conductive trace layer, the third dielectric layer, the third inner conductive trace layer, and the fourth dielectric layer are stacked in order.

10. A package substrate assembly comprising a plurality of electronic components and the package substrate of any of claims 1-9, the electronic components being electrically connected to the second outer conductive trace layer and the interposer.