CN221529947U - Chip packaging structure utilizing core particle architecture and electronic equipment - Google Patents

Abstract

The present utility model relates to the field of chip manufacturing, and in particular, to a chip packaging structure using a core particle architecture and an electronic device. The chip packaging structure comprises a main chip, a multiplexer, a core particle and a packaging substrate, wherein the main chip comprises a connecting area, the connecting area comprises a first area and a second area, the first area and the second area of the connecting area are connected through the multiplexer, the core particle is connected with the first area or the second area, and the main chip and the core particle are packaged on the packaging substrate. According to the embodiment, the first area and the second area are connected through the multiplexer, the core particles are connected with the first area or the second area, when the first area is damaged, the good second area and the damaged first area can be mutually replaced through the multiplexer, and then the main chip and the packaging substrate are connected through the core particle framework to realize the interaction function, so that the bad main chip can be partially utilized through the strategy of the connecting area and the multiplexer, and the yield is further improved.

Description

Chip packaging structure utilizing core particle architecture and electronic equipment

Technical Field

The present utility model relates to the field of chip manufacturing, and in particular, to a chip packaging structure using a core particle architecture and an electronic device.

Background

With the development of modern information technology and network communication technology, the bandwidth of a switch chip has a trend of rapid growth, for example, from 3.2T, 6.4T, to 12.8T, 25.6T or even 51.2T. This rapidly increasing bandwidth requires a greater number of transistors to meet the demands of logic circuits. Therefore, the area of the switch chip is also enlarged. However, as the chip area increases, the yield of modern chip manufacturing drops dramatically. This is because on a large area chip, even a small defect may render the entire chip unusable. Therefore, how to improve the yield and the efficiency of large-area chips is a problem to be solved in the field of chip manufacturing and design.

To address this challenge, in recent years, a centromere (chip) technology has developed. In this technique, logic circuits responsible for traffic handling and packet handling are integrated on the main chip, while peripheral high-speed SerDes signal interface circuits are placed separately in the die (as shown in fig. 4). The design strategy effectively reduces the area of each unit and correspondingly improves the yield. Nevertheless, the bandwidth of the main chip is still very large, and the problem of yield is not fundamentally solved due to the large number of transistors contained in the main chip. Most of the connection areas in these chips remain normal, but are eliminated because some small area is defective.

Therefore, a new technology is urgently needed to increase the effective yield of large bandwidth switch chips and to maximize the utilization of those chips that are considered "bad" due to some defects, finding a suitable application scenario for them.

Disclosure of utility model

The object of the present utility model is to solve at least the problem of how to use only a part of good chips. The aim is achieved by the following technical scheme:

a first aspect of the present utility model proposes a chip package structure using a core particle architecture, comprising:

The main chip comprises a connecting region, wherein the connecting region comprises a first region and a second region;

A multiplexer through which the first region and the second region of the connection region are connected;

A core particle, the core particle connecting the first region or the second region;

And the main chip and the core particles are packaged on the packaging substrate.

According to the chip packaging structure utilizing the core particle architecture, the connecting area of the main chip is partitioned and comprises the first area and the second area, the first area and the second area are connected through the multiplexer, the core particle is connected with the first area or the second area, when the first area is damaged, the good second area and the damaged first area can be mutually replaced through the multiplexer, and then the main chip and the packaging substrate are connected through the core particle architecture, so that the interaction function is realized, and therefore, the bad main chip can be partially utilized through the strategy of the connecting area and the multiplexer, the yield is further improved, the overall manufacturing cost is reduced, and the resource utilization rate is improved.

In addition, the chip packaging structure utilizing the core particle architecture according to the utility model can also have the following additional technical characteristics:

in some embodiments of the utility model, the number of the connection regions is 4, the number of the core particles is 4, and each core particle is respectively connected with the first region or the second region of one connection region. When the number of the connection areas is 4, and each core particle is correspondingly connected with the first area or the second area of one connection area, the 4 core particles are connected with one half of the main chip partition, one half of the original interaction function of the main chip is realized, and the chip with one half of the interaction function is formed.

In some embodiments of the utility model, the core particles are all connected to the first region or all connected to the second region.

In some embodiments of the utility model, the core particle includes 64 pairs of SerDes high speed signal lines.

In some embodiments of the utility model, the core particles are connected to the connection region by UCIe interconnection protocol.

In some embodiments of the utility model, the package substrate is an organic substrate.

In some embodiments of the utility model, the primary die is connected to the package substrate through a silicon interposer.

In some embodiments of the utility model, the core particle is connected to the package substrate by a silicon interposer.

A second aspect of the present utility model proposes an electronic device comprising:

a PCB circuit board;

according to the chip packaging structure, the chip packaging structure utilizing the core particle framework is arranged on the PCB.

In some embodiments of the present utility model, the number of the chip package structures using the core structure is plural, and the plural chip package structures using the core structure are disposed on the PCB.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the utility model. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

Fig. 1 schematically illustrates a structural schematic diagram of a first view angle of a chip package structure according to an embodiment of the present utility model;

Fig. 2 schematically illustrates a structural diagram of a second view of a chip package structure according to an embodiment of the present utility model;

fig. 3 schematically shows a schematic structural view of an electronic device according to an embodiment of the present utility model;

Fig. 4 schematically shows a schematic structure of a main chip and a die package in the prior art.

The reference numerals are as follows:

100. a chip packaging structure;

10. A main chip; 11. a first connection region; 111. a first region; 112. a second region; 12. a second connection region; 121. a third region; 122. a fourth region; 13. a third connection region; 131. a fifth region; 132. a sixth region; 14. a fourth connection region; 141. a seventh region; 142. an eighth region;

20. A first core particle; 21. a second core particle; 22. a third core particle; 23. a fourth core particle; 24. a fifth core particle; 25. a sixth core particle; 26. a seventh core particle; 27. eighth core particles;

30. A first multiplex communicator; 31. a second multiplex communicator; 32. a third multiplex communicator; 33. a fourth multiplex communicator;

40. UCIe interconnect protocol; 50. packaging a substrate; 60. a silicon interposer; 61. a through silicon via;

200. An electronic device; 201. and a PCB circuit board.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only, and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," "including," and "having" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order described or illustrated, unless an order of performance is explicitly stated. It should also be appreciated that additional or alternative steps may be used.

Although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as "first," "second," and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.

For ease of description, spatially relative terms, such as "inner," "outer," "lower," "below," "upper," "above," and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Accordingly, the example term "below … …" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or in other directions) and the spatial relative relationship descriptors used herein interpreted accordingly.

As shown in fig. 1 to 2, according to an embodiment of the present utility model, a chip package structure 100 using a chip architecture is provided, the chip package structure 100 including a main chip 10, a multiplexer, a chip, and a package substrate 50, the main chip 10 including a connection region including a first region 111 and a second region 112, wherein the first region 111 and the second region 112 of the connection region are connected through the multiplexer, the chip is connected to the first region 111 or the second region 112, and the main chip 10 and the chip are packaged on the package substrate 50.

In the chip packaging structure 100 using the core structure according to the present embodiment, the chip connection area is partitioned and includes the first area 111 and the second area 112, and the first area 111 and the second area 112 are connected through the multiplexer, so that when the first area 111 is damaged, the good second area 112 and the damaged first area 111 can be replaced by the multiplexer, and then the main chip 10 and the packaging substrate 50 are connected through the core structure, so as to realize the interaction function, therefore, the defective main chip 10 can also be partially utilized through the strategy of the connection area and the multiplexer, further improving the yield, reducing the overall manufacturing cost and improving the resource utilization rate.

It is understood that the chip in this embodiment is a switch chip.

In some embodiments, the number of connection regions of one main chip 10 is 4, the number of core particles is 4, and the number of connection regions of the main chip 10 is the same as the number of core particles, wherein each core particle corresponds to the first region 111 or the second region 112 connected to one connection region, respectively. When the number of the connection areas is 4, and each core particle is correspondingly connected with the first area 111 or the second area 112 of one connection area, which means that the 4 core particles are connected with one half of the partition of the main chip 10, one half of the original interaction functions of the main chip 10 are realized, and a chip with one half of the interaction functions is formed.

It will be appreciated that the core particles are all connected to the first region 111 or all connected to the second region 112. First, the core particles are all connected to the first region 111 or all connected to the second region 112, so that the package is more compact. In addition, connecting the core particles to different regions can help disperse heat, preventing heat from being concentrated in specific regions. This helps to maintain the temperature balance of the chip, thereby improving its reliability and lifetime. Also, different regions may have their own signal propagation characteristics. By decentralized connection, optimization can be performed according to the characteristics of each region, thereby maintaining high signal integrity. Finally, similar to the uniformly dispersed thermal effects, by connecting different areas, more power can be provided in the desired areas, thereby optimizing power management.

It is understood that the core particle includes 64 pairs of SerDes high speed signal lines. In the prior art, a 25.6T switch consists of 512 pairs of 50 Gbps SerDes high speed signal lines, and a 51.2T switch consists of 512 pairs of 100Gbps SerDes high speed signal lines. With this embodiment, the die has 64 pairs of SerDes high speed signal lines, and connecting 4 die to the main chip 10 means having 256 pairs of SerDes high speed signal lines, i.e., a switch chip having half the bandwidth can be realized. In addition, for high performance network switches that require processing of a large number of parallel data streams, 64 is an ideal choice for the core of the SerDes high speed signal lines, 64 provides the necessary high speed data exchange capability for the core of the SerDes high speed signal lines.

It is understood that the core particle is connected to the connection region by UCIe interconnect protocol 40. UCIe interconnect protocol 40 provides for high speed data communication, thereby ensuring high speed data exchange between the core and the primary die 10, improving data throughput. In addition UCIe is designed as a low latency interface, which is critical for high data throughput switches.

It is understood that the package substrate 50 is an organic substrate. The organic substrate is connected to the host chip and the core particle through a silicon interposer 60. The silicon interposer 60 has dense TSVs (i.e., through silicon vias 61, conductive paths perpendicular to the surface of the silicon wafer through which the front and back faces of the wafer are connected.) the silicon interposer 60 serves as a middle level for connecting the main chip 10 to the die, as well as other electronic components. Also, fine wiring on the silicon interposer 60 may accommodate multiplexers for connecting the different connection areas of the host chip 10. In this way, the core particles may be connected to the first region 111 or the second region 112 as desired.

Specifically, the main chip 10 is connected to the package substrate 50 through the silicon interposer 60. The main chip 10 is packaged on an organic substrate through a silicon interposer 60, a sophisticated 3D packaging technology. The silicon interposer 60 allows for vertical connections to be made between multiple silicon wafers enabling them to be vertically stacked together to form an integrated three-dimensional circuit structure. This technique helps reduce the distance between chips, thereby improving performance and reducing power consumption.

Specifically, the core particles are connected to the package substrate 50 through the silicon interposer 60. The core particle is provided with through silicon vias 61 and aligned and connected to corresponding positions of the organic substrate. The present embodiment provides a short circuit connection path, and thus can achieve high signal transmission speed and low power consumption. The packaging area can be saved because the area occupied by the vertical connections is much smaller than the planar connections.

In the prior art, as shown in fig. 4, each core particle corresponds to a region on the main chip 10, and two adjacent regions are not provided with a multiplex connector for communication. For example, the first core particle 20 is connected to the first region 111, the second core particle 21 is connected to the second region 112, the third core particle 22 is connected to the third region 121, the fourth core particle 23 is connected to the fourth region 122, the fifth core particle 24 is connected to the fifth region 131, the sixth core particle 25 is connected to the sixth region 132, the seventh core particle 26 is connected to the seventh region 141, and the eighth core particle 27 is connected to the eighth region 142, wherein the first region 111 to the eighth region 142 are not communicated through a multiplex connector in the prior art.

In the specific example of the present embodiment, as shown in fig. 1, the connection region includes a first connection region 11, a second connection region 12, a third connection region 13, and a fourth connection region 14, each of the first connection region 11 to the fourth connection region 14 includes a first region 111 and a second region 112, but for convenience of distinction, the naming of the first region 111 or the second region 112 of the second connection region 12 to the fourth connection region 14 is replaced in the present embodiment, the second connection region 12 includes a third region 121 and a fourth region 122, the third connection region 13 includes a fifth region 131 and a sixth region 132, and the fourth connection region 14 includes a seventh region 141 and an eighth region 142. The core particles are divided into a first core particle 20, a second core particle 21, a third core particle 22 and a fourth core particle 23. The multiplexers include a first multiplexer 30, a second multiplexer 31, a third multiplexer 32, and a fourth multiplexer 33.

More specifically, the first region 111 and the second region 112 are connected by the first multiplexer 30, the third region 121 and the fourth region 122 are connected by the second multiplexer 31, the fifth region 131 and the sixth region 132 are connected by the third multiplexer 32, and the seventh region 141 and the eighth region 142 are connected by the fourth multiplexer 33. The first core particle 20 is connected to the first region 111 by UCIe interconnection protocol 40, the second core particle 21 is connected to the third region 121 by UCIe interconnection protocol 40, the third core particle 22 is connected to the fifth region 131 by UCIe interconnection protocol 40, and the fourth core particle 23 is connected to the seventh region 141 by UCIe interconnection protocol 40.

As shown in fig. 2, the main chip 10 is encapsulated on the encapsulation substrate 50 through the silicon interposer 60, and the core is encapsulated on the encapsulation substrate 50 through the silicon interposer 60.

The steps for producing the present embodiment are:

First, since the area of the core particle is small, the yield is high, and all core particles can be good by default.

Next, in the defective main chip 10, the probability of the first region 111 and the second region 112 being defective at the same time is extremely low, and similarly, at least one of the third region 121 and the fourth region 122 is good, at least one of the fifth region 131 and the sixth region 132 is good, and at least one of the seventh region 141 and the eighth region 142 is good.

Next, four of the total 8 pieces of pellets, which may be 1/3/5/7 or 2/4/6/8 (i.e., the first to fourth pellets 20 to 23), are selected so that the positions of the other 2/4/6/8 areas are left empty, which are not in contact with the filling actual pellets, by 1/3/5/7 (i.e., the first pellet 20 corresponding to the first area 111, the second pellet 21 corresponding to the third area 121, the third pellet 22 corresponding to the fifth area 131, and the fourth pellet 23 corresponding to the seventh area 141).

Also, it was determined that each pellet had 8×8=64 pairs of SerDes high speed signal lines.

In addition, if the first region 111, the third region 121, the fifth region 131 and the seventh region 141 of the connection core are good, it means that the second region 112, the fourth region 122, the sixth region 132 and the eighth region 142 are also good without any action, but if there is a partial damage of the region of the connection core, it is exchanged with the other half of the chip assuming good portions through the multiplexer. For example, if the first region 111 is poor and the second region 112 is good, the channels of the first region 111 and the second region 112 of the main chip 10 are replaced with each other by a multiplexer, the channels of the second region 112 are connected to the first core particle 20, and so on.

Finally, the main chip 10 and the first, second, third and fourth core particles 20, 21, 22 and 23 are collectively packaged on one package substrate 50, forming a product of the switch chip having half bandwidth.

As shown in fig. 3, this embodiment further proposes an electronic device 200, including:

A PCB circuit board 201;

In the above-mentioned chip package structure 100 using the core structure, the chip package structure 100 is disposed on the PCB 201.

In some embodiments, the number of chip packages 100 using the core structure is plural, and the plural chip packages 100 are disposed on the PCB 201.

Specifically, the electronic device 200 is a switch that includes a PCB circuit board 201 for physical support and electrical connection, containing the basic peripheral components required for operation of the switch, such as power management components, clock sources, auxiliary interfaces, etc., and is designed with high-speed signal tracking and layout to ensure fast and reliable data transfer in the switch. On this PCB circuit board 201, a plurality of chip package structures 100 using a core structure are disposed. The main chip 10 in each chip package structure 100 has a connection area for high-speed data exchange with external components, interfaces, or other chips. Meanwhile, a plurality of core particles, each having a specific function such as data processing, signal conversion, buffering, etc., are connected to the connection region of the main chip 10 through UCIe interconnection protocol 40. These main chips 10 are packaged together with a silicon interposer 60 and connected to the package substrate 50 through the silicon interposer 60, and the core particles are also connected to the package substrate 50 through the silicon interposer 60. The switch also includes other network interfaces (e.g., SFP, QSFP ports) for external network connections, as well as heat dissipation solutions, power supply units, and control management modules. The use of a core architecture allows each core to handle specific functions specifically, improving data processing efficiency and response time, while the deployment of multiple chip package structures 100 allows the switch to easily expand its functionality and performance, meeting different network requirements. The use of UCIe interconnect protocol 40 and silicon interposer 60 ensures high-speed, low-latency data interaction while integrating multiple chips and die into the same package structure, saves space and enhances device reliability. The switch is suitable for use in data centers, enterprise networks, and communication infrastructure.

The present utility model is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present utility model are intended to be included in the scope of the present utility model. Therefore, the protection scope of the utility model is subject to the protection scope of the claims.

Claims (10)

1. A chip package structure using a core particle architecture, comprising:

The main chip comprises a connecting region, wherein the connecting region comprises a first region and a second region;

the first area is connected with the second area through the multiplexer;

A core particle, the core particle connecting the first region or the second region;

And the main chip and the core particles are packaged on the packaging substrate.

2. The chip packaging structure using a die architecture according to claim 1, wherein the number of the connection regions is 4, the number of the die is 4, and each die is respectively connected to the first region or the second region of one of the connection regions.

3. The chip package structure using a die architecture according to claim 2, wherein the die is connected to the first region entirely or connected to the second region entirely.

4. A chip package structure utilizing a core particle architecture according to any one of claims 1 to 3, wherein the core particle comprises 64 pairs of SerDes high speed signal lines.

5. A chip package structure utilizing a core particle architecture according to any of claims 1 to 3, wherein the core particles are connected to the connection regions by UCIe interconnect protocol.

6. A chip package structure using a core structure according to any one of claims 1 to 3, wherein the package substrate is an organic substrate.

7. The chip package structure according to claim 6, wherein the main chip is connected to the package substrate through a silicon interposer.

8. The chip package structure of claim 6, wherein the die is connected to the package substrate by a silicon interposer.

9. An electronic device, comprising:

a PCB circuit board;

The chip package structure using a die architecture according to any one of claims 1 to 8, which is provided on the PCB.

10. The electronic device of claim 9, wherein the number of chip packages using a die structure is plural, and the plural chip packages using a die structure are disposed on the PCB.