CN221305188U - One drags many data lines and charger - Google Patents

Abstract

The utility model relates to the field of charging accessories, in particular to a multi-data line and a charger. The one-to-many data line comprises a first interface, a second interface and a third interface; the first interface is a USBA male head with nine first groups of pins, and the nine first groups of pins are respectively a first GND pin, a first VBUS pin, a first D+ pin, a first D-pin and five first type pins; the second interface comprises a second GND pin, a second VBUS pin, a second CC pin, a second DP pin and a second DM pin; the third interface comprises a third GND pin, a third VBUS pin and a third CC pin; according to the utility model, the charger is connected with the external equipment through more than two interfaces, the charger can also realize the independent quick charge of the external equipment through a single interface, and the charger can also realize the collaborative quick charge of a plurality of external equipment through a plurality of interfaces.

Description

One drags many data lines and charger

Technical Field

The utility model relates to the field of charging accessories, in particular to a multi-data line and a charger.

Background

One data line refers to one data line that can be connected to a plurality of devices or interfaces for data transmission or charging. Such datase:Sub>A lines typically have one master interface (typically USB-ase:Sub>A) and multiple slave interfaces (e.g., type-C, micro-USB or lighting).

Multiple devices may be conveniently connected to a host device or power source using a one-to-many data line, thereby reducing cluttered cable stacks and connector counts, which may be used to charge multiple devices simultaneously or to transfer data between multiple devices.

To achieve fast charging, the following conditions are generally required: the charger itself must support the fast charging technology, the same fast charging protocol needs to be supported between the charger and the charging device in order to negotiate and adjust the charging parameters, and the charged device (e.g. mobile phone, tablet computer, etc.) itself also needs to support the corresponding fast charging technology and protocol.

However, when a plurality of devices are simultaneously cooperated with fast charging, the existing one-to-multiple data line is easy to make mistakes, mainly cables or protocol chips are multiplexed, and the fast charging failure is caused by abnormal charging.

Disclosure of utility model

The utility model aims to solve the technical problems of providing a one-to-many data line and a charger aiming at the defects in the prior art, and solves the problem of quick charging failure caused by the existing charging abnormality.

The technical scheme adopted for solving the technical problems is as follows: providing a one-to-many data line, wherein the one-to-many data line comprises a first interface, a second interface and a third interface;

The first interface is a USBA male head with nine first groups of pins, and the nine first groups of pins are respectively a first GND pin, a first VBUS pin, a first D+ pin, a first D-pin and five first type pins;

The second interface comprises a second GND pin, a second VBUS pin, a second CC pin, a second DP pin and a second DM pin;

The third interface comprises a third GND pin, a third VBUS pin and a third CC pin;

The first GND pin is connected with the second GND pin and the third GND pin respectively, the first D+ pin is connected with one of the second CC pin and the third CC pin, and the first D-pin is connected with the other of the second CC pin and the third CC pin;

Four pins of the five first type pins are respectively connected with a second DP pin, a second DM pin, a second VBUS pin and a third VBUS pin.

Among them, the preferred scheme is: the one-to-multiple data line further comprises a fourth interface, the fourth interface comprises a first four GND pin and a first four VBUS pin, the first four GND pin is connected with the first GND pin, and the first four VBUS pin is connected with the first VBUS pin.

Among them, the preferred scheme is: the fourth interface is a watch charging port.

Among them, the preferred scheme is: the remaining one of the five pins of the first type is also connected to a second VBUS pin.

Among them, the preferred scheme is: the second VBUS pin is respectively connected with the SSR-pin and the first DRAIN pin of the USBA male head.

Among them, the preferred scheme is: and the second DP pin and the second DM pin are respectively connected with an SSR+ pin and an SST-pin of the USBA male head.

Among them, the preferred scheme is: the second interface is tpyec male.

Among them, the preferred scheme is: and the third VBUS pin is connected with an SST+ pin of the USBA male head.

Among them, the preferred scheme is: the third interface is tpyec male or Lightning male.

Among them, the preferred scheme is: the USBA male head is one of USB3.0, USB3.1, USB3.2 and USB 4.0.

The technical scheme adopted for solving the technical problems is as follows: there is provided a charger comprising:

The USBA female seat is matched with the USBA male head of the one-to-many data line and comprises nine fourth groups of pins, wherein the nine fourth groups of pins are a fourth GND pin, a fourth VBUS pin, a fourth D+ pin, a fourth D-pin and five fourth types of pins respectively;

The first quick charge management circuit and the second quick charge management circuit are connected with the USBA master seat; wherein,

The fifth CC end of the first quick charge management circuit is connected with one of a fourth D+ pin or a fourth D-pin, and the sixth CC end of the second quick charge management circuit is connected with the other of the fourth D+ pin or the fourth D-pin; the fourth GND pin is grounded;

And four pins in the fifth type of pins are respectively connected with the fifth electric energy output end of the first quick charge management circuit, the sixth electric energy output end of the second quick charge management circuit, the fifth DP pin of the first quick charge management circuit and the fifth DM pin of the first quick charge management circuit.

Among them, the preferred scheme is: the charger further comprises a third charging management circuit, and a seventh electric energy output end of the third charging management circuit is connected with a fourth VBUS pin.

Among them, the preferred scheme is: the remaining one of the five fourth type pins is also connected with a fifth electric energy output end of the first quick charge management circuit.

Among them, the preferred scheme is: and a fifth electric energy output end of the first quick charge management circuit is respectively connected with a SSTX-pin and a second DRAIN pin of the USBA master batch.

Among them, the preferred scheme is: and a fifth DP pin and a fifth DM pin of the first quick charge management circuit are respectively connected with a SSTX + pin and a SSRX-pin of the USBA master batch.

Among them, the preferred scheme is: and the sixth electric energy output end of the second quick charge management circuit is connected with a SSRX + pin of the USBA master batch.

Among them, the preferred scheme is: the USBA master seat is one of USB3.0, USB3.1, USB3.2 and USB 4.0.

Among them, the preferred scheme is: the charger comprises a first power input end, the first quick charge management circuit comprises a first voltage reduction circuit and a first quick charge protocol circuit, the second quick charge management circuit comprises a second voltage reduction circuit and a second quick charge protocol circuit, the first voltage reduction circuit is respectively connected with the first power input end and the first quick charge protocol circuit, and electric energy of the first power input end passes through after being reduced in voltage and is output from a second interface under the control of the first quick charge protocol circuit; the second voltage reduction circuit is respectively connected with the first power input end and the second fast charge protocol circuit, so that the electric energy of the first power input end is reduced in voltage and then is output from the third interface under the control of the second fast charge protocol circuit.

The technical scheme adopted for solving the technical problems is as follows: providing a charger, wherein the charger comprises a fifth interface, a sixth interface, a fourth quick charge management circuit and a fifth quick charge management circuit;

The fifth interface comprises an eighth GND pin, an eighth VBUS pin, an eighth CC pin, an eighth DP pin and an eighth DM pin;

The sixth interface comprises a ninth GND pin, a ninth VBUS pin and a ninth CC pin;

Wherein the eight GND pins and the nine GND pins are grounded; a tenth CC end of the fourth fast charge management circuit is connected with one of an eighth CC pin and a ninth CC pin, and an eleventh CC end of the fifth fast charge management circuit is connected with the other of the eighth CC pin and the ninth CC pin;

The tenth electric energy output end of the fourth fast charge management circuit is connected with an eighth VBUS pin, the eleventh electric energy output end of the fifth fast charge management circuit is connected with a ninth VBUS pin, and the tenth DP end and the tenth DM end of the fourth fast charge management circuit are respectively connected with an eighth DP pin and an eighth DM pin.

Among them, the preferred scheme is: the charger comprises a main body, wherein the fifth interface and the sixth interface are arranged in the main body, or the fifth interface and the sixth interface are outwards extended through data lines.

Among them, the preferred scheme is: the charger further comprises a seventh interface and a sixth charge management circuit, the seventh interface comprises a twelfth GND pin and a twelfth VBUS pin, a thirteenth power output end of the sixth charge management circuit is connected with the twelfth VBUS pin, and the twelfth GND pin is grounded.

Among them, the preferred scheme is: the charger comprises a second power input end, the fourth fast charge management circuit comprises a fourth voltage reduction circuit and a fourth fast charge protocol circuit, the fifth fast charge management circuit comprises a fifth voltage reduction circuit and a fifth fast charge protocol circuit, the fourth voltage reduction circuit is respectively connected with the second power input end and the fourth fast charge protocol circuit, and the electric energy of the second power input end passes through after being reduced in voltage and is output from a fifth interface under the control of the fourth fast charge protocol circuit; the fifth voltage reducing circuit is respectively connected with the second power input end and the fifth fast charging protocol circuit, so that the electric energy of the second power input end is reduced in voltage and then is output from the sixth interface under the control of the fifth fast charging protocol circuit.

Compared with the prior art, the utility model has the beneficial effects that the charger is connected with the external equipment through more than two interfaces, the charger can also realize the independent quick charge of the external equipment through a single interface, and the charger can also realize the collaborative quick charge of the charger for a plurality of external equipment through a plurality of interfaces.

Drawings

The technical scheme of the utility model will be further described in detail below with reference to the accompanying drawings and examples, wherein:

FIG. 1 is a system block diagram of a plurality of data lines of the present utility model;

FIG. 2 is a system block diagram of the addition of a new connection of FIG. 1;

FIG. 3 is a block diagram of the system of FIG. 1 with the addition of a third interface;

FIG. 4 is a system block diagram of a charger with a USBA master batch of the present utility model;

FIG. 5 is a system block diagram of a fast charge management circuit of the charger of FIG. 4;

FIG. 6 is a block diagram of the add new connection system of FIG. 5;

FIG. 7 is a block diagram of the system of FIG. 5 with the addition of a third interface;

FIG. 8 is a system block diagram of the specific fast charge management circuit of FIG. 5;

FIG. 9 is a circuit diagram of a fourth fast charge protocol circuit of the present utility model;

fig. 10 is a circuit diagram of the present utility model and a fourth step-down circuit;

FIG. 11 is a system block diagram of a charger with a plurality of data lines according to the present utility model;

FIG. 12 is a system block diagram of a quick charge management circuit of the charger of FIG. 11;

FIG. 13 is a system block diagram of the addition of a new connection of FIG. 11;

fig. 14 is a system block diagram of the new connection mode added in fig. 12.

Detailed Description

Preferred embodiments of the present utility model will now be described in detail with reference to the accompanying drawings.

As shown in fig. 1 and 2, the present utility model provides a preferred embodiment of a one-to-many data line.

A plurality of data lines comprising a first interface 1100, a second interface 1200, and a third interface 1300; the first interface 1100 is a USBA male head having nine first groups of pins, which are a first GND pin 11, a first VBUS pin 14, a first d+ pin 12, a first D-pin 13, and five first class pins, respectively; the second interface 1200 includes a second GND pin 21, a second VBUS pin 25, a second CC pin 22, a second DP pin 23, and a second DM pin 24; the third interface 1300 includes a third GND pin 31, a third VBUS pin 33, and a third CC pin 32; wherein the first GND pin 11 is connected to the second GND pin 21 and the third GND pin 31, the first d+ pin 12 is connected to one of the second CC pin 22 and the third CC pin 32, and the first D-pin 13 is connected to the other of the second CC pin 22 and the third CC pin 32; four of the five first type pins are connected to the second DP pin 23, the second DM pin 24, the second VBUS pin 25, and the third VBUS pin 33, respectively.

A multi-drop data line is a data line that can connect multiple devices, the first interface 1100 is used as a master interface, and the second interface 1200 and the third interface 1300 are used as slave interfaces when the charger is connected to the multiple devices, so that the charger can be charged while connecting the multiple devices. A plurality of devices (such as a smart phone, a tablet personal computer, a Bluetooth headset and the like) are simultaneously connected to the charger by using one-to-multiple data lines and a matched charger, and power charging is provided for the devices by the charger, so that the requirement of using a plurality of independent chargers is reduced, the socket space is saved, and the plurality of devices are convenient to manage and charge.

Through the first group of pins of the USBA male head, the second interface 1200 and the third interface 1300 can be charged respectively at the same time, and the quick charging operation of the charger on the second interface 1200 and the third interface 1300 can be realized. The first GND pin 11 and the first VBUS pin 14 of the second interface 1200 are connected with the charger through the USBA male head to achieve electric energy charging of the second interface 1200, and the second CC pin 22 of the second interface 1200 is connected with the charger through the USBA male head to achieve communication interaction between the device connected with the second interface 1200 and the charger, the communication interaction involves identifying the device type, negotiating charging protocol and parameters, etc., and the second DP pin 23 and the second DM pin 24 of the second interface 1200 are connected with the charger through the USBA male head to achieve fast charging operation between the device connected with the second interface 1200 and the charger. The second GND pin 21 and the second VBUS pin 25 of the third interface 1300 are connected with the charger through the USBA male head so as to charge the electric energy of the third interface 1300 by the charger, and the second CC pin 22 of the third interface 1300 is connected with the charger through the USBA male head so as to realize communication interaction and quick charging operation between the device connected with the third interface 1300 and the charger.

Through the connection setting between the USBA male head, the second interface 1200 and the third interface 1300, the charger can charge the external equipment independently and quickly through the first interface 1100 and the second interface 1200, the charger can charge the external equipment independently and quickly through the first interface 1100 and the third interface 1300, and the charger can charge the two external equipment cooperatively and quickly through the first interface 1100, the second interface 1200 and the third interface 1300.

In this embodiment, a structure of the USBA male head with nine first groups of pins is utilized, and preferably, the USBA male head is one of USB3.0, USB3.1, USB3.2 and USB4.0, so as to implement a fast charging operation for two interfaces. The USB standard supports higher data transfer speeds and power transfer capabilities, which may provide faster charging speeds and higher power output, e.g., the USB3.0 standard supports data transfer speeds up to 5Gbps, while the USB3.1, USB3.2, and USB4.0 standards further provide higher speeds and power transfer capabilities. By using any one of these USB standards, communication with the charger and the device and a quick charging operation are realized with its extra pins to ensure compatibility among the charger, the data line and the device.

Nine first group pins are respectively a first GND pin 11, a first VBUS pin 14, a first d+ pin 12, a first D-pin 13 and five first class pins, the first GND pin 11 provides circuit grounding, the first d+ pin 12 and the first D-pin 13 serve as pins for data transmission, the five first class pins are respectively an SSR-pin 15, an ssr+ pin 16, an SST-pin 17, an sst+ pin 18 and a first DRAIN pin 19, and the first DRAIN pin 19, the SSR-pin 15, the ssr+ pin 16, the SST-pin 17 and the sst+ pin 18 not only serve as high-efficiency charging pins, but also serve as high-speed data transmission pins, so that differential transmission of data lines is realized. The design of the pins enables USB 3.0, USB3.1, USB3.2 or USB4.0 to provide higher data transmission speed and greater bandwidth, and

In this embodiment, the second interface 1200 is a tpyec male, and the third interface 1300 is a tpyec male or a lighting male. For tpyec male implementation fast charging is typically dependent on the USB Power Delivery (USB PD) protocol. USB PD is a protocol for providing high power charging through tpyec male heads, which can provide higher power output and faster charging speed. To achieve fast charging of the Type-C interface, it is necessary to ensure that the following conditions are met: the charger supports USB PD; the device accessed to tpyec public head supports USB PD; proper USB PD negotiation when the charger and device are connected, USB PD negotiation is performed between them to determine appropriate charging protocols and parameters, including determining required power output, voltage and current, etc., and the relevant communications between the USBA male and tpyec male are implemented through the second CC pin 22, the second DP pin 23 and the second DM pin 24. If the third interface 1300 is tpyec male, the related communication between the USBA male and the tpyec male is implemented through the third CC pin 32.

The lighting male is a proprietary connector for its devices (e.g., iPhone, iPad, iPod) by apple corporation, and to achieve quick-fill of the lighting interface, the following conditions need to be met: the charger supports a quick-charging protocol, and the quick-charging protocol of apples comprises USB Power Delivery (USB PD) and Apple' sproprietary quick-charging protocol; the device supports a fast charging protocol; the third CC pin 32, e.g., the third interface 1300, enables communication of the fast charge protocol.

In this embodiment, the remaining one of the five pins of the first type is also connected to the second VBUS pin 25. That is, two pins of the five first type pins are connected with the second VBUS pin 25 of the second interface 1200, and a current transmission path is increased, so that a larger current output is supported, and the requirement of the device for higher power charging is met.

Further, the second VBUS pin 25 is connected to the SSR-pin 15 and the first DRAIN pin 19 of the USBA male, the second DP pin 23 and the second DM pin 24 are connected to the ssr+ pin 16 and the SST-pin 17 of the USBA male, respectively, and the third VBUS pin 33 is connected to the sst+ pin 18 of the USBA male. Of course, this connection is not exclusive, and other mating connections are also possible. This way of connection brings the following benefits: by connecting the second VBUS pin 25 with the SSR-pin 15 and the first draw pin 19 of the USBA header, a greater current transfer capability may be provided, facilitating higher power charging or charging requirements for high power devices; supporting data transmission, the second DP pin 23 and the second DM pin 24 are respectively connected with the SSR+ pin 16 and the SST-pin 17 of the USBA male head, so that high-efficiency data transmission can be realized; the current through the connection of the third VBUS pin 33 to the SST + pin 18 of the USBA male is also guaranteed.

As shown in fig. 3, the present utility model provides a preferred embodiment of a fourth interface 1400.

The one-to-multiple data line further includes a fourth interface 1400, where the fourth interface 1400 includes a first fourth GND pin 41 and a first fourth VBUS pin 44, the first fourth GND pin 41 is connected to the first GND pin 11, and the first fourth VBUS pin 44 is connected to the first VBUS pin 14. Since the fourth interface 1400 is connected to the first GND pin 11 and the first VBUS pin 14 of the USBA male head through the first fourth GND pin 41 and the first fourth VBUS pin 44, respectively, the charger can output a stable voltage to the fourth interface 1400, for example, 5V electric energy, to realize charging of the external device of the fourth interface 1400, regardless of the charging conditions of the second interface 1200 and the third structure.

The fourth interface 1400 is a watch charging port, but may be any other interface, such as tpyec male, lighting male, micro USB, etc., and the APPLE WATCH charging port is a specially designed interface for connecting and charging APPLE WATCH, and uses magnetic connection to ensure stable connection between the charger and APPLE WATCH and support wireless charging function, and this charging port is usually located on the back of APPLE WATCH and has a specific shape and pin layout to adapt to APPLE WATCH charger.

As shown in fig. 4-8, the present utility model provides a preferred embodiment of a charger 2000.

A charger 2000 comprising a USBA female socket 2100 mated with the USBA male head of the one-to-many data line, the USBA female socket 2100 comprising nine fourth sets of pins, the nine fourth sets of pins being a fourth GND pin 211, a fourth VBUS pin 214, a fourth d+ pin 213, a fourth D-pin 214, and five fourth class pins, respectively; a first quick charge management circuit 2200 and a second quick charge management circuit 2300, the first quick charge management circuit 2200 and the second quick charge management circuit 2300 being connected to the USBA master batch 2100; wherein the fifth CC terminal 221 of the first fast charge management circuit 2200 is connected to one of the fourth d+ pin 213 or the fourth D-pin 214, and the sixth CC terminal of the second fast charge management circuit 2300 is connected to the other of the fourth d+ pin 213 or the fourth D-pin 214; the fourth GND pin 211 is grounded; four pins of the five fourth types of pins are respectively connected with the fifth power output 224 of the first fast charge management circuit 2200, the sixth power output 232 of the second fast charge management circuit 2300, the fifth DP pin 223 of the first fast charge management circuit 2200, and the fifth DM pin 222 of the first fast charge management circuit 2200.

Specifically, charger 2000 uses a USBA female dock 2100 that mates with the USBA male header of a plurality of data lines, the USBA female dock 2100 containing nine fourth sets of pins, specifically:

fourth GND pin 211: is connected to ground and provides the ground for the circuit.

Fourth VBUS pin 214: the power supply is used for transmitting power supply to supply stable voltage power, can be applied to one-to-many data lines of the utility model, can supply stable voltage power for the fourth interface 1400, and can also charge the data line with the USBA common head.

Fourth D+ pin 213 and fourth D-pin 214: for transmitting USB data signals, when the USB female socket 2100 is inserted into the USB male head of one multi-data line of the present utility model, the USB male head is connected to the first d+ pin 12 and the first D-pin 13 of the USB male head through the fourth d+ pin 213 and the fourth D-pin 214, respectively, so as to be connected to the second CC pin 22 of the second interface 1200 and the third CC pin 32 of the third interface 1300.

Five fourth type pins: when the USBA female socket 2100 is inserted into the USBA male head of one multi-data line of the utility model, the USBA male head is connected with five first type pins of the USBA male head, so that power supply, data transmission and the like are realized.

In this embodiment, the first fast charge management circuit 2200 is connected to the fourth d+ pin 213 or the fourth D-pin 214 through the fifth CC terminal 221, so as to detect whether the charger 2000 is plugged into the device, detect the connection state, and determine whether the fast charge is required by detecting the plugging and unplugging event of the USB connection second interface 1200, and further, the first fast charge management circuit 2200 also communicates with the connected device to identify the charging requirement and compatibility of the device, which involves sending specific commands or protocols to handshake and communicate with the device. Based on the communication with the device and the identification result, the fast charge management circuit determines an applicable charging protocol, which may be a proprietary fast charge protocol of apple, or may be another standard fast charge protocol, such as USB Power Delivery (USB PD), specifically, the connection between the fifth DP pin 223 of the first fast charge management circuit 2200 and the second DP pin 23 and the second DM pin 24 of the second interface 1200 is implemented through the fifth DP pin 222 of the first fast charge management circuit 2200. And the first quick charge management circuit 2200 configures charging parameters, such as voltage and current level, according to the determined charging protocol, once the configuration of the charging parameters is completed, the first quick charge management circuit 2200 controls the power supply output to provide appropriate voltage and current for quick charging of the device, and meanwhile, the first quick charge management circuit 2200 monitors parameters such as current, voltage and temperature in the charging process, adjusts and protects the parameters as required, and when the device reaches the charging completion condition, the first quick charge management circuit 2200 stops charging and cuts off the power supply output.

The fast charging mode of the second fast charging management circuit 2300 is substantially identical to the first fast charging management circuit 2200, but the second fast charging management circuit 2300 communicates with the fourth d+ pin 213 or the fourth D-pin 214 via the sixth CC terminal, and the related fast charging communication can only be implemented via the sixth CC terminal. And, after the second interface 1200 or the third interface 1300 corresponding to the first fast charge management circuit 2200 or the second fast charge management circuit 2300 is connected to the device, if another interface is detected to be connected to the device, the collaborative fast charge is started. The collaborative fast charging means that the second interface 1200 and the third interface 1300 corresponding to the first fast charging management circuit 2200 and the second fast charging management circuit 2300 are connected to the devices at the same time, at this time, the first fast charging management circuit 2200 drops from the original first fast charging power to the second fast charging power, and the second fast charging management circuit 2300 drops from the original third fast charging power to the fourth fast charging power, so that the second fast charging power and the fourth fast charging power meet or approach the maximum fast charging power of the charger 2000.

For example, the single interface fast charge is 100W, while the two interface fast charges are 65W and 30W, although other values are possible, leaving the fourth interface 1400 to be 5W output power, i.e. 5v 1a output power.

In this embodiment, the remaining one of the five fourth pins is further connected to the fifth power output 224 of the first fast charge management circuit 2200, which can provide a larger current transmission capability, which is beneficial for higher power charging or charging requirements of high power devices.

Further, the fifth power output 224 of the first fast charge management circuit 2200 is coupled to the SSTX-pin 218 and the second DRAIN pin 219, respectively, of the USBA bezel 2100. The fifth DP pin 223 and the fifth DM pin 222 of the first fast charge management circuit 2200 are connected to the SSTX + pin 217 and the SSRX-pin 216, respectively, of the USBA bezel 2100. The sixth power output 232 of the second fast charge management circuit 2300 is coupled to the SSRX + pin 215 of the USBA master 2100. Of course, this connection is not exclusive, and other mating connections are also possible. This way of connection brings the following benefits: by connecting the fifth power output 224 with SSTX-pin 218 and second DRAIN pin 219, increased current transfer capability may be provided, facilitating higher power charging or charging requirements for high power devices; supporting data transmission, the fifth DP pin 223 and the fifth DM pin 222 of the first fast charge management circuit 2200 are respectively connected with the SSTX + pin 217 and the SSRX-pin 216 of the USBA master 2100, so that efficient data transmission can be realized; the current through the sixth power output 232 is also guaranteed to be coupled to the SSRX + pin 215 of the USBA female 2100 of the USBA male.

In this embodiment, the USB female socket 2100 is one of USB3.0, USB3.1, USB3.2, and USB 4.0.

In this embodiment, and referring to fig. 8, the charger 2000 includes a first power input terminal 2500, the first fast charge management circuit 2200 includes a first voltage reducing circuit 2220 and a first fast charge protocol circuit 2210, the second fast charge management circuit 2300 includes a second voltage reducing circuit 2320 and a second fast charge protocol circuit 2310, the first voltage reducing circuit 2220 is connected to the first power input terminal 2500 and the first fast charge protocol circuit 2210, so as to realize that the electric energy of the first power input terminal 2500 passes through after being reduced in voltage and is output from the second interface 1200 under the control of the first fast charge protocol circuit 2210; the second step-down circuit 2320 is connected to the first power input terminal 2500 and the second fast charging protocol circuit 2310, so as to realize that the electric energy of the first power input terminal 2500 passes through after being step-down, and is output from the third interface 1300 under the control of the second fast charging protocol circuit 2310.

Specifically, the first step-down circuit 2220 is responsible for reducing the high voltage of the power input by the first power input end 2500 to a voltage level suitable for charging of the device, which can meet the voltage requirement of single quick charging, the voltage requirement of double quick charging and the voltage requirement of common charging, and the first step-down circuit 2220 adopts a switching power supply technology, can efficiently convert electric energy and provides stable output voltage and current. The first fast charge protocol circuit 2210 includes a first fast charge protocol chip for supporting a specific fast charge protocol, such as USB Power Delivery (USB PD), qualcomm Quick Charge, etc., and the first fast charge protocol chip of the first fast charge protocol circuit 2210 has built-in corresponding protocol parsing and communication functions, and can negotiate and communicate with a connected device to determine appropriate charging parameters and power levels. The first fast charge management circuit 2200 further includes a series of supporting circuit elements and functional modules to control, protect and monitor the charging process, and supporting peripheral circuits including over-current protection, over-temperature protection, voltage and current monitoring, feedback loops, etc. to ensure the safety and stability of the charging process.

The operation principle of the second step-down circuit 2320 and the second fast-charge protocol circuit 2310 is similar to that of the first step-down circuit 2220 and the first fast-charge protocol circuit 2210, and will not be described in any sense again.

Wherein the first fast charge protocol circuit 2210 and the second fast charge protocol circuit 2310 are responsible for communicating with connected devices, negotiating charging parameters and power levels, and transmitting specific communication protocol messages, such as USB PD messages or fast charge protocol messages, for handshake and negotiation with the devices. The negotiated charging parameter and power level are transferred to the first step-down circuit 2220 and the second step-down circuit 2320 through control signals, which may include related parameters such as an output voltage, an output current, a switching frequency, and the like. The first step-down circuit 2220 and the second step-down circuit 2320 adjust according to the received control signal to achieve a specified output voltage and current, and adjust parameters such as a switching frequency, a duty cycle, and the like according to a requirement of the control signal to provide a required output voltage level. Through the above control feedback manner, a cooperative work is realized between the fast charge protocol circuit and the voltage reduction circuit, the first fast charge protocol circuit 2210 and the second fast charge protocol circuit 2310 are responsible for communication and negotiation with the device, determine appropriate charging parameters, and then transmit the parameters to the first voltage reduction circuit 2220 and the second voltage reduction circuit 2320 through control signals, so that the output voltage and the current can be adjusted according to requirements.

Meanwhile, the first fast charge protocol circuit 2210 and the second fast charge protocol circuit 2310 are also in communication with each other, when a single fast charge protocol circuit works, the maximum power fast charge can be selected, if two fast charge protocol circuits 2210 and 2310 work simultaneously, the charge power is reduced by the coordination of the first fast charge protocol circuit 2210 and the second fast charge protocol circuit 2310, and the sum of the power reaches the maximum output power.

In this embodiment, referring to fig. 9 and 10, regarding the first fast charge protocol circuit 2210 and the first voltage reduction circuit 2220, the first voltage reduction circuit 2220 includes a first voltage reduction chip, the first fast charge protocol circuit 2210 includes a first fast charge protocol chip, the VIN pin of the first voltage reduction chip is connected with the first power input 2500, after voltage reduction, the VOUT pin of the first voltage reduction chip is output, a MOS transistor Q1 is connected in series between the VOUT pin of the first voltage reduction chip and one or two fourth types of pins of the USBA socket 2100, and the gate of the MOS transistor Q1 is controlled by the first fast charge protocol chip, so as to control the on-off of the MOS transistor Q1, that is, control the on-off between the VOUT pin of the first voltage reduction chip and one or two fourth types of pins of the USBA socket 2100. And, the VOUT pin of the first buck chip is further connected to the VIN pin of the first fast charge protocol chip, the VOUT pin of the first fast charge protocol chip is connected to one or two fourth types of pins of the USBA socket 2100, the feedback pin of the first fast charge protocol chip is connected to the feedback pin of the first buck chip, the DP pin and the DM pin of the first fast charge protocol chip are respectively connected to two fourth types of pins of the USBA socket 2100, and the CC pin of the first fast charge protocol chip is connected to the fourth d+ pin 213 or the fourth D-pin 214 of the USBA socket 2100.

Regarding the second fast charge protocol circuit 2310 and the second voltage step-down circuit 2320, the second voltage step-down circuit 2320 includes a second voltage step-down chip, the second fast charge protocol circuit 2310 includes a second fast charge protocol chip, the second fast charge protocol chip is in communication connection with the first fast charge protocol chip, and is connected through CSN and CSP, and the connection manner between the second voltage step-down chip and the second fast charge protocol chip is similar to that between the first voltage step-down chip and the first fast charge protocol chip, for example, the MOS transistor Q2, and the CC pin of the second fast charge protocol chip is connected with the fourth d+ pin 213 or the fourth D-pin 214 of the USBA socket 2100.

As shown in fig. 7, the present utility model provides a preferred embodiment of a third charge management circuit 2400.

The charger 2000 further includes a third charge management circuit 2400, and a seventh power output 241 of the third charge management circuit 2400 is connected to the fourth VBUS pin 214. The third charge management circuit 2400 includes a third buck circuit to implement stable output of electrical energy, the third buck circuit including a third buck chip having a VIN pin connected to the first power input 2500 and a VOUT pin connected to the fourth VBUS pin 214 of the USBA master 2100.

The VOUT pins of the first fast charge protocol circuit 2210, the second fast charge protocol circuit 2310, and the third fast charge protocol circuit are the fifth power output 224, the sixth power output 232, and the seventh power output 241.

As shown in fig. 11-13, the present utility model provides a preferred embodiment of a charger 3000.

A charger 3000, the charger 3000 comprising a fifth interface 3100 and a sixth interface 3200, and further comprising a fourth fast charge management circuit 3010 and a fifth fast charge management circuit 3020; the fifth interface 3100 includes an eighth GND pin 311, an eighth VBUS pin 315, an eighth CC pin 312, an eighth DP pin 313, and an eighth DM pin 314; the sixth interface 3200 includes a ninth GND pin 321, a ninth VBUS pin 323, and a ninth CC pin 322; wherein the eighth GND pin 312 and the ninth GND pin 321 are grounded; the tenth CC end 303 of the fourth fast charge management circuit 3010 is connected to one of the eighth CC pin 312 and the ninth CC pin 322, and the eleventh CC end 302 of the fifth fast charge management circuit 3020 is connected to the other of the eighth CC pin 312 and the ninth CC pin 322; the tenth power output 308 of the fourth fast charge management circuit 3010 is connected to the eighth VBUS pin 315, the eleventh power output 305 of the fifth fast charge management circuit 3020 is connected to the ninth VBUS pin 323, and the tenth DP terminal 306 and the tenth DM terminal 307 of the fourth fast charge management circuit 3010 are connected to the eighth DP pin 313 and the eighth DM pin 314, respectively.

Specifically, the charger 3000 is connected to an external device through a fifth interface 3100 and a sixth interface 3200, and the external device performs a fast charging service, and pins of the fifth interface 3100 and the sixth interface 3200 are specifically:

eighth GND pin 311 and nine GND pins: is connected to ground and provides the ground for the circuit.

Eighth DP pin 313 and eighth DM pin 314: the data signal is transmitted through the fifth interface 3100, and after the fifth interface 3100 is inserted into the device, the fourth fast charge management circuit 3010 is connected to the external device through the eighth DP pin 313 and the eighth DM pin 314 in a communication manner, so as to implement communication of the fast charge protocol.

The eighth CC pin 312 transmits a data signal through the fifth interface 3100, and after the fifth interface 3100 is inserted into the device, the fourth fast charge management circuit 3010 performs communication connection with an external device through the eighth CC pin 312, so as to implement handshake communication.

Ninth CC pin 322, through sixth interface 3200 transmission data signal, after sixth interface 3200 inserts the equipment, fifth quick charge management circuit 3020 carries out communication connection through ninth CC pin 322 and external equipment, realizes handshake communication, can also realize quick charge protocol's communication.

In this embodiment, the fourth fast charge management circuit 3010 detects whether the charger 3000 is plugged into the device through the eighth CC pin 312, the eighth DP pin 313 and the eighth DM pin 314, detects the connection state, and detects the plugging and unplugging event of the fifth interface 3100 to determine whether fast charge is required, and further, the fourth fast charge management circuit 3010 also communicates with the connected device to identify the charging requirement and compatibility of the device, involving sending specific commands or protocols to handshake and communicate with the device. According to the communication and recognition result with the device, the fast charge management circuit determines an applicable charging protocol, which may be a proprietary fast charge protocol of an apple, or may be another standard fast charge protocol, such as USB Power Delivery (USB PD), and configures charging parameters according to the same communication manner, and according to the determined charging protocol, the fourth fast charge management circuit 3010 configures charging parameters, such as voltage and current level, and once the configuration of the charging parameters is completed, the fourth fast charge management circuit 3010 controls the power supply output to provide appropriate voltage and current for fast charging of the device, and at the same time, the fourth fast charge management circuit 3010 monitors parameters, such as current, voltage and temperature, in the charging process, and adjusts and protects as required, and when the device reaches the charging completion condition, the fourth fast charge management circuit 3010 stops charging and cuts off the power supply output.

The fast charge mode of the fifth fast charge management circuit 3020 is substantially identical to the fourth fast charge management circuit 3010, but the fifth fast charge management circuit 3020 communicates through the ninth CC pin 322. And, after the fifth interface 3100 or the sixth interface 3200 corresponding to the fourth fast charge management circuit 3010 or the fifth fast charge management circuit 3020 is connected to the device, if another interface connection device is detected, the collaborative fast charge is started. The collaborative fast charging means that the fifth interface 3100 or the sixth interface 3200 corresponding to the fourth fast charging management circuit 3010 and the fifth fast charging management circuit 3020 are connected to the device at the same time, at this time, the fourth fast charging management circuit 3010 reduces the original fifth fast charging power to the sixth fast charging power, and the fifth fast charging management circuit 3020 reduces the original seventh fast charging power to the eighth fast charging power, so that the sixth fast charging power and the eighth fast charging power meet or approach the maximum fast charging power of the charger 3000.

For example, the single interface fast charge is 100W, while the two interface fast charges are 65W and 30W, although other values are possible, leaving the fourth interface 1400 to be 5W output power, i.e. 5v 1a output power.

In this embodiment, the charger 3000 includes a second power input end, the fourth fast charge management circuit 3010 includes a fourth voltage reduction circuit 3011 and a fourth fast charge protocol circuit 3012, the fifth fast charge management circuit 3020 includes a fifth voltage reduction circuit 3021 and a fifth fast charge protocol circuit 3022, the fourth voltage reduction circuit 3011 is connected to the second power input end and the fourth fast charge protocol circuit 3012, so that electric energy of the second power input end passes through after being reduced in voltage, and is output from the fifth interface 3100 under the control of the fourth fast charge protocol circuit 3012; the fifth voltage reducing circuit 3021 is connected to the second power input terminal and the fifth fast charging protocol circuit 3022, so as to reduce the voltage of the electric energy of the second power input terminal, and output the electric energy from the sixth interface 3200 under the control of the fifth fast charging protocol circuit 3022.

Regarding the fourth fast charge protocol circuit 3012 and the fourth voltage reduction circuit 3011, the fourth voltage reduction circuit 3011 includes a fourth voltage reduction chip, the fourth fast charge protocol circuit 3012 includes a fourth fast charge protocol chip, the VIN pin of the fourth voltage reduction chip is connected to the second power input end, after voltage reduction, the voltage is output from the VOUT pin of the fourth voltage reduction chip, an MOS transistor Q3 is connected in series between the VOUT pin of the fourth voltage reduction chip and the eighth VBUS pin 315 of the fifth interface 3100, and the gate of the MOS transistor Q3 is controlled by the fourth fast charge protocol chip, so as to control the on-off of the MOS transistor Q3, that is, control the on-off between the VOUT pin of the fourth voltage reduction chip and the eighth VBUS pin 315 of the fifth interface. And, the VOUT pin of the fourth buck chip is further connected to the VIN pin of the fourth fast-charging protocol chip, the VOUT pin of the fourth fast-charging protocol chip is connected to the eighth VBUS pin 315 of the five interfaces, the feedback pin of the fourth fast-charging protocol chip is connected to the feedback pin of the fourth buck chip, the DP pin and the DM pin of the fourth fast-charging protocol chip are respectively connected to the eighth DP pin 313 and the eighth DM pin 314, and the CC pin of the fourth fast-charging protocol chip is connected to the eighth CC pin 312 of the USBA socket 2100.

Regarding the fifth fast charge protocol circuit 3022 and the fifth voltage reduction circuit 3021, the fifth voltage reduction circuit 3021 includes a fifth voltage reduction chip, the fifth fast charge protocol circuit 3022 includes a fifth fast charge protocol chip, the fifth fast charge protocol chip is communicatively connected to the fourth fast charge protocol chip, and is connected to the CSP through the CSN, and the fifth voltage reduction chip and the fifth fast charge protocol chip are similar to the fourth voltage reduction chip and the fourth fast charge protocol chip, for example, the MOS transistor Q4, and the CC pin of the fifth fast charge protocol chip is connected to the ninth CC pin 322.

Further, the DP pin and the DM pin of the fifth fast charge protocol chip are further connected to the ninth DP pin and the ninth DM pin of the sixth interface 3200, so that the fifth fast charge protocol chip can communicate with the ninth DP pin and the ninth DM pin through the ninth CC pin 322, the ninth DP pin, and the ninth DM pin, including insertion detection, fast charge protocol communication, and the like.

The VOUT pins of the fourth fast charge protocol circuit 3012 and the fifth fast charge protocol circuit 3022 are the tenth power output terminal 308 and the eleventh power output terminal 305.

In this embodiment, the charger 3000 includes a main body, and the fifth interface 3100 and the sixth interface 3200 are disposed in the main body, or the fifth interface 3100 and the sixth interface 3200 are disposed to extend outwards through a data line. In the first aspect, the fifth interface 3100 and the sixth interface 3200 are disposed in the main body, and the fifth interface 3100 and the sixth interface 3200 are disposed in the main body of the charger 3000: in this arrangement, the fifth interface 3100 and the sixth interface 3200 are directly embedded in the body of the charger 3000, and a user can connect to these interfaces for charging or data transmission by directly inserting a cable or device.

In the second scheme, the fifth interface 3100 and the sixth interface 3200 are arranged outwards through the data line, and in this arrangement, the fifth interface 3100 and the sixth interface 3200 are not directly embedded in the main body of the charger 3000, but extend outwards through the data line, there may be only one or fewer interfaces on the main body of the charger 3000, and the fifth interface 3100 and the sixth interface 3200 are arranged on the connection head on the data line, so that the user can connect the main body of the charger 3000 with the device through the connection data line, thereby realizing charging or data transmission.

In this embodiment, the charger 3000 further includes a seventh interface 3300 and a sixth charge management circuit 3030, the seventh interface 3300 includes a twelfth GND pin 331 and a twelfth VBUS pin 332, the thirteenth power output 304 of the sixth charge management circuit 3030 is connected to the twelfth VBUS pin 332, and the twelfth GND pin 331 is grounded.

The foregoing description of the preferred embodiments of the present utility model is not intended to limit the scope of the utility model, but rather is intended to cover all modifications and variations within the scope of the present utility model as defined in the appended claims.

Claims (11)

1. A multi-data line, characterized by: the one-to-many data line comprises a first interface, a second interface and a third interface;

The first interface is a USBA male head with nine first groups of pins, and the nine first groups of pins are respectively a first GND pin, a first VBUS pin, a first D+ pin, a first D-pin and five first type pins;

The second interface comprises a second GND pin, a second VBUS pin, a second CC pin, a second DP pin and a second DM pin;

The third interface comprises a third GND pin, a third VBUS pin and a third CC pin;

The first GND pin is connected with the second GND pin and the third GND pin respectively, the first D+ pin is connected with one of the second CC pin and the third CC pin, and the first D-pin is connected with the other of the second CC pin and the third CC pin;

Four pins of the five first type pins are respectively connected with a second DP pin, a second DM pin, a second VBUS pin and a third VBUS pin.

2. A multi-data line as claimed in claim 1, wherein: the one-to-multiple data line further comprises a fourth interface, the fourth interface comprises a first four GND pin and a first four VBUS pin, the first four GND pin is connected with the first GND pin, and the first four VBUS pin is connected with the first VBUS pin.

3. A multi-data line as claimed in claim 2, wherein: the fourth interface is a watch charging port.

4. A multi-data line as claimed in claim 1, wherein: the remaining one of the five pins of the first type is also connected to a second VBUS pin.

5. A plurality of data lines according to claim 4, wherein: the second VBUS pin is respectively connected with the SSR-pin and the first DRAIN pin of the USBA male head.

6. A plurality of data lines according to claim 5, wherein: and the second DP pin and the second DM pin are respectively connected with an SSR+ pin and an SST-pin of the USBA male head.

7. A multi-drop data line according to any one of claims 1, 4 to 6, wherein: the second interface is tpyec male.

8. A multi-drop data line according to any one of claims 1, 4 to 6, wherein: and the third VBUS pin is connected with an SST+ pin of the USBA male head.

9. A plurality of data lines according to claim 8, wherein: the third interface is tpyec male or Lightning male.

10. A multi-data line as claimed in claim 1, wherein: the USBA male head is one of USB3.0, USB3.1, USB3.2 and USB 4.0.

11. A charger, comprising:

A USBA female socket for mating with a USBA male head of a plurality of data lines according to any one of claims 1 to 10, said USBA female socket comprising nine fourth sets of pins, said nine fourth sets of pins being a fourth GND pin, a fourth VBUS pin, a fourth d+ pin, a fourth D-pin and five fourth types of pins, respectively;

The first quick charge management circuit and the second quick charge management circuit are connected with the USBA master seat; wherein,

The fifth CC end of the first quick charge management circuit is connected with one of a fourth D+ pin or a fourth D-pin, and the sixth CC end of the second quick charge management circuit is connected with the other of the fourth D+ pin or the fourth D-pin; the fourth GND pin is grounded;

And four pins in the fifth type of pins are respectively connected with the fifth electric energy output end of the first quick charge management circuit, the sixth electric energy output end of the second quick charge management circuit, the fifth DP pin of the first quick charge management circuit and the fifth DM pin of the first quick charge management circuit.