CN221282126U

CN221282126U - Semiconductor structure

Info

Publication number: CN221282126U
Application number: CN202322968383.9U
Authority: CN
Inventors: 于海龙; 董信国; 孟昭生
Original assignee: GTA Semiconductor Co Ltd
Current assignee: GTA Semiconductor Co Ltd
Priority date: 2023-11-02
Filing date: 2023-11-02
Publication date: 2024-07-05
Anticipated expiration: 2033-11-02

Abstract

The application relates to a semiconductor structure, which comprises a substrate, a buried gate, a channel layer, an isolation layer and a source electrode/drain electrode; a buried gate at least partially buried within the substrate; the channel layer is positioned in the substrate, and is positioned at two opposite sides of the embedded gate along the first direction parallel to the substrate and below the embedded gate; an isolation layer located within the substrate and between the channel layer and the substrate; and the source electrode/drain electrode is positioned on the top surface of the substrate and positioned on two opposite sides of the isolation layer along the first direction. When the area of the device is reduced, the contact area between the grid electrode and the channel is increased, so that the control capability of the grid electrode to the channel is increased, the leakage phenomenon of the device is reduced, and the carrier mobility is improved.

Description

Semiconductor structure

Technical Field

The present application relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure.

Background

With the rapid development of ultra-large-scale integrated circuits, the integration level of chips is higher and the sizes of components are smaller, and the influence of various effects caused by the high density and small size of the components on the manufacturing result of the semiconductor process is more prominent, so that more and higher requirements are put on the semiconductor process.

As the size of the integrated circuit is reduced, the channel length of the field effect transistor is correspondingly shortened, the distance between the source region and the drain region is also shortened, the control capability of the gate electrode to the channel is deteriorated, which means that the difficulty of pinching off the channel by the gate electrode voltage is increased, the leakage phenomenon (short channel effect) is more likely to occur, and various novel structures have been explored in order to reduce the area and reduce the leakage phenomenon.

Disclosure of utility model

In view of the foregoing, it is desirable to provide a semiconductor structure that reduces leakage and improves carrier mobility when the device area is reduced, as in the case of manufacturing a semiconductor device.

To achieve the above and other objects, according to various embodiments of the present application, a first aspect of the present application provides a semiconductor structure including a substrate, a buried gate, a channel layer, an isolation layer, and source/drain electrodes; a buried gate at least partially buried within the substrate; the channel layer is positioned in the substrate, and is positioned at two opposite sides of the embedded gate along the first direction parallel to the substrate and below the embedded gate; an isolation layer located within the substrate and between the channel layer and the substrate; and the source electrode/drain electrode is positioned on the top surface of the substrate and positioned on two opposite sides of the isolation layer along the first direction.

In some embodiments, the channel layer is U-shaped.

In some embodiments, the channel layer comprises a germanium-silicon channel layer.

In some embodiments, the channel layer circumferentially surrounds the buried gate.

In some embodiments, the buried gate includes a gate conductive layer and a gate dielectric layer, and the bottom of the gate conductive layer is buried in the substrate; the gate dielectric layer is positioned between the gate conductive layer and the substrate.

The semiconductor structure increases the capacity of the grid electrode to intercept carriers through the embedded grid at least partially embedded in the substrate; carrier migration is achieved through a channel layer located within the substrate and located on opposite sides of the buried gate along a first direction parallel to the substrate and below the buried gate; the electric leakage phenomenon is reduced through the isolation layer which is positioned in the substrate and between the channel layer and the substrate; carriers are provided through the source/drain. With the improvement of ion implantation, lithography, etching and other technologies in the semiconductor technology, the feature size of the chip of the conventional Metal-Oxide-semiconductor field effect transistor (MOSFET) integrated circuit is gradually reduced, the integration level is gradually increased, and the power consumption problem is also more and more serious along with the improvement of the chip performance. While devices are scaled down, the problem of device short channel effects has severely hampered the development of semiconductor technology. The semiconductor structure of the application is at least partially embedded into the embedded gate in the substrate; carrier migration is achieved through a channel layer located within the substrate and located on opposite sides of the buried gate along a first direction parallel to the substrate and below the buried gate; when the area of the device is reduced, the control capability of the gate to the channel is enhanced, and the leakage phenomenon of the device is reduced.

In some embodiments, the semiconductor structure further includes a ring gate and a conductive portion, wherein the ring gate is located in the substrate and between the isolation layer and the substrate, and the ring gate is located at two opposite sides of the buried gate along the first direction and below the buried gate; the source electrode/drain electrode is positioned on two opposite sides of the ring grid along the first direction; and a conductive portion penetrating the channel layer in an extending direction of the conductive portion, the buried gate being electrically connected to the gate via the conductive portion.

In some embodiments, the conductive portion includes a first conductive portion, a second conductive portion, and a third conductive portion, the first conductive portion being located on a first side of the buried gate along a first direction and configured to electrically connect the buried gate and the ring gate; the second conductive part is positioned on a second side of the buried gate opposite to the first side along the first direction and is used for electrically connecting the buried gate and the ring gate; the third conductive part is arranged right below the buried grid and is used for electrically connecting the buried grid and the ring grid.

In some embodiments, the ring gate includes a gate conductive layer and a gate dielectric layer, the gate conductive layer is located in the substrate and located on two opposite sides of the channel layer along the first direction and below the channel layer; the gate dielectric layer is positioned between the gate conductive layer and the channel layer.

In some embodiments, the ring gate circumferentially surrounds the buried gate.

In some embodiments, the number of at least one of the first conductive portion, the second conductive portion, and the third conductive portion is a plurality.

The semiconductor structure increases the capacity of the grid electrode to intercept carriers through the embedded grid at least partially embedded in the substrate; carrier migration is realized and carrier migration rate is improved through the germanium-silicon channel layer which is positioned in the substrate and positioned on two opposite sides of the buried gate along the first direction parallel to the substrate and below the buried gate; the electric leakage phenomenon is reduced through the isolation layer which is positioned in the substrate and between the channel layer and the substrate; providing carriers through the source/drain; the ring grid structure is arranged in the substrate and between the isolation layer and the substrate, and the ring grid is also arranged on two opposite sides of the buried grid along the first direction and below the buried grid; the source electrode/drain electrode is positioned on two opposite sides of the ring grid along the first direction, the conductive part penetrates through the channel layer along the extending direction of the conductive part, the embedded grid is electrically connected with the ring grid through the conductive part, four-side surrounding of the embedded grid and the ring grid to the channel region is realized, the contact area is increased, the control capability of the grid to the channel is enhanced, and the leakage phenomenon of the device is reduced. With the improvement of ion implantation, lithography, etching and other technologies in the semiconductor technology, the feature size of the chip of the conventional metal-oxide-semiconductor field effect transistor is gradually reduced, the integration level is gradually increased, and the power consumption problem is also more and more serious along with the improvement of the chip performance. While devices are scaled down, the problem of device short channel effects has severely hampered the development of semiconductor technology. The semiconductor structure of the application is at least partially embedded into the embedded gate in the substrate; carrier migration is achieved through a germanium-silicon channel layer located within the substrate and on opposite sides of the buried gate along a first direction parallel to the substrate and below the buried gate; the ring gate structure is arranged in the substrate and between the isolation layer and the substrate, the ring gate is also arranged on two opposite sides of the buried gate along the first direction and below the buried gate, the buried gate is electrically connected with the ring gate through the conductive part, four-side surrounding of the gate conductive layer to the channel region is realized, when the area of the device is reduced, the contact area of the gate and the channel is increased, the control capability of the gate to the channel is enhanced, the carrier migration rate is improved, and the electric leakage phenomenon of the device is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a schematic cross-sectional view of an N-type metal-oxide-semiconductor structure according to an embodiment of the present application;

FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present application;

FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present application;

fig. 4 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present application.

Reference numerals illustrate:

100. A semiconductor structure; 110. a substrate; 120a, buried gates; 121a/121b, a gate conductive layer; 122a/122b, a gate dielectric layer; 120b, a ring grid; 123. a conductive portion; 1231. a first conductive portion; 1232. a second conductive portion; 1233. a third conductive portion; 130. a channel layer; 131. a germanium-silicon channel layer; 140. an isolation layer; 150. source/drain.

Detailed Description

In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that the terms first, second, etc. as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the application. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

Where the terms "comprising," "having," and "including" are used herein, another component may also be added unless a specifically defined term is used, such as "consisting of only," "… …," etc. Unless mentioned to the contrary, singular terms may include plural and are not to be construed as being one in number.

It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.

It is understood that "at least one" means one or more and "a plurality" means two or more. "at least part of an element" means part or all of the element.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.

With the rapid development of ultra-large-scale integrated circuits, the integration level of chips is higher and the sizes of components are smaller, and the influence of various effects caused by the high density and small size of the components on the manufacturing result of the semiconductor process is more prominent, so that more and higher requirements are put on the semiconductor process. The characteristic size of the traditional metal-oxide-semiconductor field effect transistor integrated circuit chip is gradually reduced, the integration level is gradually increased, the channel length is correspondingly shortened, the distance between a source region and a drain region is also shortened, the control capability of a grid electrode on the channel is reduced, the difficulty of pinching off the channel by the grid electrode voltage is increased, the electric leakage phenomenon (short channel effect) is more easy to occur, and the power consumption problem is more serious. In order to reduce the leakage phenomenon while reducing the device area, various novel structures have been explored.

As an example, referring to fig. 1, for an N-type metal-oxide-semiconductor, the source/drain region is N-type, the substrate is P-type, the gate conductive layer and the gate dielectric layer together form a gate, by applying a positive voltage, holes in the P-type substrate are repelled, electrons are attracted to collect under the gate, and when tensile stress acts on the channel region of the N-type metal-oxide-semiconductor, carriers of the N-type metal-oxide-semiconductor migrate to form a current I ₂ and a current I ₆, and currents I ₁、I₂、I₃、I₄ and I ₅ occur due to short channel effects.

Referring to fig. 2, an embodiment of the present application provides a semiconductor structure 100, which increases the control capability of the gate to the channel, reduces the leakage phenomenon, and improves the carrier mobility when the device area is reduced. The semiconductor structure 100 includes a substrate 110, a buried gate 120a, a channel layer 130, an isolation layer 140, and source/drain electrodes 150; buried gate 120a is at least partially buried within substrate 110; the channel layer 130 is located within the substrate 110 and is located on opposite sides of the buried gate 120a along a first direction (e.g., OX direction) parallel to the substrate 110 and below the buried gate 120 a; the isolation layer 140 is located within the substrate 110 and between the channel layer 130 and the substrate 110; the source/drain 150 is located on the top surface of the substrate 110 and on opposite sides of the isolation layer 140 in the first direction.

Illustratively, the substrate 110 may be constructed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 110 may have a single-layer structure or a multi-layer structure. For example, the substrate 110 may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Or also for example, substrate 110 may be a layered substrate comprising a material such as Si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. The type of substrate 110 should not limit the scope of the present disclosure. The substrate 110 may include other electrical components and the like, and is omitted because it is not so much related to the present invention.

In some embodiments, referring to fig. 2, the channel layer 130 is U-shaped, and the channel layer 130 includes a first portion covering a portion of the sidewall of the buried gate 120a and a second portion located under the buried gate 120a, so that the contact area between the channel layer and the buried gate 120a is increased without increasing the length of the gate along the OX direction, thereby enhancing the control capability of the gate to the channel, improving the carrier mobility, and reducing the leakage phenomenon of the device.

In some embodiments, referring to fig. 3, the channel layer 130 includes a sige channel layer 131, and is embedded in the source/drain region by using compressive stress (compressive stress) generated by the difference of lattice constants of germanium and silicon, so as to improve mobility and saturation current of carriers. The lattice constant of silicon isThe lattice constant of germanium isThe mismatch ratio of silicon and germanium is 4.1%, so that the lattice constant of germanium silicon is larger than that of pure silicon, and compressive stress is generated in the source/drain region.

In some embodiments, referring to fig. 2, the channel layer 130 circumferentially surrounds the buried gate 120a, and the channel layer 130 contacts the outer surface of the sidewall of the buried gate 120a and the lower surface of the buried gate 120a by covering the side surface of the first portion of the sidewall of the buried gate 120a and the upper surface of the second portion under the buried gate 120a, so that the channel layer 130 circumferentially surrounds the buried gate 120a, and the contact surface between the channel layer 130 and the buried gate 120a is increased without increasing the length of the gate in the OX direction, thereby enhancing the control capability of the gate to the channel, improving the carrier transfer rate, and reducing the leakage phenomenon of the device.

In some embodiments, referring to fig. 2, the buried gate 120a includes a gate conductive layer 121a and a gate dielectric layer 122a, and the bottom of the gate conductive layer 121a is buried in the substrate 110; gate dielectric layer 122a is located between gate conductive layer 121a and substrate 110.

As an example, please continue to refer to fig. 2, a semiconductor structure includes a substrate 110, a buried gate 120a, a channel layer 131, and source/drain electrodes 150. The ability of the gate to intercept carriers is increased by the buried gate 120a at least partially buried within the substrate 110; carrier mobility is achieved and carrier mobility rate is increased by the sige channel layer 131 being within the substrate 110 and on opposite sides of the buried gate 120a along a first direction (e.g., OX direction) parallel to the substrate 110 and below the buried gate 120a; by the isolation layer 140 positioned in the substrate 110 and between the channel layer 130 and the substrate 110, the leakage phenomenon is reduced; carriers are provided through the source/drain 150. With the improvement of ion implantation, lithography, etching and other technologies in the semiconductor technology, the feature size of the chip of the conventional metal-oxide-semiconductor field effect transistor is gradually reduced, the integration level is gradually increased, and the power consumption problem is also more and more serious along with the improvement of the chip performance. While devices are scaled down, the problem of device short channel effects has severely hampered the development of semiconductor technology. The semiconductor structure 100 of the present application has a buried gate 120a at least partially buried within a substrate; carrier transport is achieved by the silicon germanium channel layer 131 being located within the substrate 110 and on opposite sides of the buried gate 120a in a first direction parallel to the substrate 110 and below the buried gate 120a; when the area of the device is reduced, the control capability of the gate to the channel is enhanced, and the leakage phenomenon of the device is reduced.

In some embodiments, referring to fig. 4, the semiconductor structure further includes a ring gate 120b and a conductive portion 123, wherein the ring gate 120b is located in the substrate 110 and between the isolation layer 140 and the substrate 110, and the ring gate 120b is located on two opposite sides of the buried gate 120a along the first direction (e.g. OX direction) and below the buried gate 120 a; wherein the source/drain electrodes 150 are located on opposite sides of the gate electrode 120b along the first direction; the conductive portion 123 penetrates the channel layer 130 in the extending direction of the conductive portion 123, and the buried gate 120a is electrically connected to the ring gate 120b via the conductive portion 123. By designing the ring gate 120b structure to be located on opposite sides of the buried gate 120a along the first direction (for example, OX direction) and below the buried gate 120a, and electrically connected to the buried gate 120a through the conductive portion 123, the contact area between the gate and the channel is increased, the controllability of the gate to the channel is enhanced, and the carrier mobility is improved.

In some embodiments, referring to fig. 4, the conductive portion 123 includes a first conductive portion 1231, a second conductive portion 1232, and a third conductive portion 1233, wherein the first conductive portion 1231 is located on a first side of the buried gate 120a along a first direction (e.g. OX direction) and is used for electrically connecting the buried gate 120a and the ring gate 120b; the second conductive portion 1232 is located at a second side of the buried gate 120a opposite to the first side in the first direction, for electrically connecting the buried gate 120a and the ring gate 120b; the third conductive portion 1233 is located directly under the buried gate 120a and electrically connects the buried gate 120a and the ring gate 120b. The buried gate 120a and the ring gate 120b are electrically connected through a plurality of conductive portions, so that the connection between the buried gate 120a and the ring gate 120b is enhanced, the control of the gate on the channel is better realized, and the carrier mobility is improved.

In some embodiments, please continue to refer to fig. 4, the gate ring 120b includes a gate conductive layer 121b and a gate dielectric layer 122b, wherein the gate conductive layer 121b is disposed in the substrate 110 and is disposed on two opposite sides of the channel layer 130 along the first direction and below the channel layer 130; the gate dielectric layer 122b is located between the gate conductive layer 121b and the channel layer 130, and the gate conductive layer 121a and the gate conductive layer 121b are prevented from being in direct contact with the channel layer 130 through the gate dielectric layer 122a and the gate dielectric layer 122b, so that better control of the channel by the gate can be achieved, carrier mobility can be improved, and leakage phenomenon of a device can be reduced.

In some embodiments, please continue to refer to fig. 4, the ring gate 120b circumferentially surrounds the buried gate 120a, and the buried gate 120a and the ring gate 120b achieve full wrapping of the gate on the channel, increase the contact area between the gate and the channel, increase the control capability of the gate on the channel, and increase the carrier mobility.

In some embodiments, referring to fig. 4, at least one of the first conductive portion 1231, the second conductive portion 1232, and the third conductive portion 1233 is plural in number. By designing the number of conductive portions in the plurality of conductive portions, the connection between the buried gate 120a and the ring gate 120b is enhanced, thereby better enabling control of the channel by the gate.

In some embodiments, the substrate 110 in the semiconductor structure 100 is of a conductivity type opposite to that of the source/drain 150, thereby forming a P-N junction. For example, if the substrate 110 is P-type, the source/drain 150 is N-type; the substrate 110 is N-type and the source/drain 150 is P-type. Specifically, P-type refers to P-type doping, and ions In performing an ion implantation process include any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF ₂) ions, indium (In) ions, and the like; n-type refers to N-type doping and ions in performing the ion implantation process may include, but are not limited to, any one or more of arsenic (As) ions, phosphorus (P) ions, and nitrogen (N) ions.

As an example, with continued reference to fig. 4, a semiconductor structure 100 includes a substrate 110, a buried gate 120a, a ring gate 120b, a silicon germanium channel layer 131, and source/drain electrodes 150. The ability of the gate to intercept carriers is increased by the buried gate 120a at least partially buried within the substrate 110; carrier mobility is achieved and carrier mobility rate is increased by the sige channel layer 131 being within the substrate 110 and on opposite sides of the buried gate 120a along a first direction (e.g., OX direction) parallel to the substrate 110 and below the buried gate 120a; by the isolation layer 140 positioned in the substrate 110 and between the channel layer 130 and the substrate 110, the leakage phenomenon is reduced; providing carriers through the source/drain 150; providing a ring gate 120b structure, wherein the ring gate 120b structure is positioned in the substrate 110 and between the isolation layer 140 and the substrate 110, and the ring gate 120b is also positioned on two opposite sides of the buried gate 120a along the first direction and below the buried gate 120a; the source/drain electrodes 150 are located at two opposite sides of the gate electrode 120b along the first direction, the conductive portion 123 penetrates through the channel layer 130 along the extending direction of the conductive portion 123, the buried gate 120a is electrically connected with the gate electrode 120b via the conductive portion 123, so that the buried gate 120a and the gate electrode 120b surround the four sides of the channel region 130, and the contact area is increased, thereby enhancing the control capability of the gate electrode to the channel and reducing the leakage phenomenon of the device. With the improvement of ion implantation, lithography, etching and other technologies in the semiconductor technology, the feature size of the chip of the conventional metal-oxide-semiconductor field effect transistor is gradually reduced, the integration level is gradually increased, and the power consumption problem is also more and more serious along with the improvement of the chip performance. While devices are scaled down, the problem of device short channel effects has severely hampered the development of semiconductor technology. The semiconductor structure 100 of the present application has a buried gate 120a at least partially buried within a substrate; carrier transport is achieved by the silicon germanium channel layer 131 being located within the substrate 110 and on opposite sides of the buried gate 120a in a first direction parallel to the substrate 110 and below the buried gate 120a; the structure of the ring gate 120b is designed, the ring gate 120b is located in the substrate 110 and between the isolation layer 140 and the substrate 110, the ring gate 120b is also located at two opposite sides of the buried gate 120a along the first direction and below the buried gate 120a, the buried gate 120a is electrically connected with the ring gate 120b through the conductive part 123, so that the buried gate 120a and the ring gate 120b surround the four sides of the channel region 130, and when the area of the device is reduced, the contact area between the gate and the channel is increased, the control capability of the gate to the channel is enhanced, the carrier migration rate is improved, and the leakage phenomenon of the device is reduced.

Specifically, the gate dielectric layer 122a/122b is an insulating layer between the gate conductive layer and the channel layer, and when the device is in operation, the voltage at the gate will form an electric field in the channel layer, thereby cutting off the current. The gate dielectric layer 122a/122b may be selected from the group consisting of silicon dioxide (SiO ₂), silicon oxynitride (SiON), silicon nitride, aluminum oxide (Al ₂O₃), aluminum oxynitride (AlON), and combinations thereof. The gate dielectric layers 122a/122b may also be a high-k dielectric material (a dielectric material having a dielectric constant greater than or equal to 3.9), or a low-k dielectric material (a dielectric constant greater than or equal to 2.5 and less than 3.9), an ultra-low-k dielectric material (a dielectric constant less than 2.5), a ferroelectric material, an antiferroelectric material, silicon carbide (SiC), or any combination thereof. The material of the gate conductive layer 121a/121b is selected from indium tin oxide, polysilicon, copper, tungsten, aluminum, copper alloy, titanium nitride, nitride buttons, tantalum nitride, and combinations thereof.

In the description of the present specification, reference to the term "some embodiments," "other embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.

Claims

1. A semiconductor structure, comprising:

A substrate;

a buried gate at least partially buried within the substrate;

a channel layer located within the substrate and located on opposite sides of the buried gate along a first direction parallel to the substrate and below the buried gate;

An isolation layer located within the substrate and between the channel layer and the substrate;

And the source electrode/drain electrode is positioned on the top surface of the substrate and positioned on two opposite sides of the isolation layer along the first direction.

2. The semiconductor structure of claim 1, wherein the channel layer is U-shaped.

3. The semiconductor structure of claim 1, wherein the channel layer comprises a silicon germanium channel layer.

4. The semiconductor structure of claim 1, wherein the channel layer circumferentially surrounds the buried gate.

5. The semiconductor structure of any of claims 1-4, wherein the buried gate comprises:

a gate conductive layer with a bottom buried in the substrate;

And the gate dielectric layer is positioned between the gate conducting layer and the substrate.

6. The semiconductor structure of any one of claims 1-4, further comprising:

The ring grid is positioned in the substrate and between the isolation layer and the substrate, and is also positioned on two opposite sides of the embedded grid along the first direction and below the embedded grid; wherein the source/drain electrodes are positioned on opposite sides of the gate-all-around along the first direction;

And a conductive portion penetrating the channel layer in an extending direction of the conductive portion, the buried gate being electrically connected to the gate-all-around via the conductive portion.

7. The semiconductor structure of claim 6, wherein the conductive portion comprises:

A first conductive portion located at a first side of the buried gate along the first direction, for electrically connecting the buried gate and the ring gate;

A second conductive portion located at a second side of the buried gate opposite to the first side in the first direction, for electrically connecting the buried gate and the ring gate;

And the third conductive part is positioned right below the embedded grid and is used for electrically connecting the embedded grid and the ring grid.

8. The semiconductor structure of claim 6, wherein the ring gate comprises:

A gate conductive layer within the substrate and located on opposite sides of the channel layer along the first direction and below the channel layer;

And the gate dielectric layer is positioned between the gate conductive layer and the channel layer.

9. The semiconductor structure of claim 6, wherein the ring gate circumferentially surrounds the buried gate.

10. The semiconductor structure of claim 7, wherein at least one of the first conductive portion, the second conductive portion, and the third conductive portion is plural in number.