CN221201168U

CN221201168U - Packaging structure

Info

Publication number: CN221201168U
Application number: CN202421120154.XU
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Shanghai Bi Ren Technology Co ltd
Current assignee: Shanghai Bi Ren Technology Co ltd
Priority date: 2024-05-22
Filing date: 2024-05-22
Publication date: 2024-06-21
Anticipated expiration: 2034-05-22

Abstract

The utility model provides a packaging structure, comprising: the hybrid substrate comprises a main body substrate and a rewiring structure, wherein the main body substrate comprises a core layer, a first stacking layer and a second stacking layer, the first stacking layer and the second stacking layer are arranged on two opposite sides of the core layer, and the rewiring structure is arranged on one side, far away from the core layer, of the first stacking layer, is in contact with the main body substrate and is electrically connected with the main body substrate; the main chip module and the passive device matrixes are electrically connected through the hybrid substrate and are arranged on one side of the rewiring structure far away from the main substrate side by side, wherein each passive device matrix is provided with a plurality of chip areas and a cutting reserved area and comprises a plurality of passive device chips which are respectively arranged on the plurality of chip areas, the plurality of passive device chips are arranged side by side and are spaced from each other through the cutting reserved area, and the passive device matrixes are provided with substrates which extend continuously in the plurality of chip areas and the cutting reserved area. The package structure has improved device performance and warpage of the package structure can be reduced or avoided.

Description

Packaging structure

Technical Field

Embodiments of the present disclosure relate to the field of semiconductor packaging, and more particularly, to a packaging structure.

Background

Chip-on-substrate (Chip on Wafer on Substrate, coWoS) packaging is an advanced semiconductor packaging technology that can achieve high-density wiring connection of multiple chips and high-rate transmission of data. How to optimize the signal transmission between the conductive elements of the package structure is an important research topic in the art; moreover, in CoWoS packages, warpage problems may exist. How to reduce warpage of a package structure is also an important research topic in the packaging technology field.

Disclosure of utility model

There is provided, in accordance with at least one embodiment of the present disclosure, a package structure including: a hybrid substrate including a main body substrate including a core layer, a first buildup layer and a second buildup layer, wherein the first buildup layer and the second buildup layer are disposed on opposite sides of the core layer in a direction perpendicular to a main surface of the hybrid substrate, and a rerouting structure disposed on a side of the first buildup layer remote from the core layer and in contact with and electrically connected to the main body substrate; a main chip module and at least one passive device matrix electrically connected to each other through the hybrid substrate and disposed side by side on a side of the rewiring structure away from the main substrate in a direction parallel to a main surface of the hybrid substrate, wherein each of the passive device matrices has a plurality of chip regions and a dicing reserved region, and includes a plurality of passive device chips respectively disposed in the plurality of chip regions, the plurality of passive device chips being disposed side by side in a direction parallel to the main surface of the hybrid substrate and spaced apart from each other by the dicing reserved region, wherein the passive device matrix has a substrate continuously extending in the plurality of chip regions and the dicing reserved region.

In the package structure provided according to at least one embodiment of the present disclosure, the core layer includes a core dielectric layer and a conductive member, the first buildup layer includes a first dielectric layer and a first conductive structure, the second buildup layer includes a second dielectric layer and a second conductive structure, the first conductive structure, the conductive member, and the second conductive structure are electrically connected to each other, the rerouting structure includes a third dielectric layer and a rerouting layer, and the third dielectric layer is in contact with the first dielectric layer, and the rerouting layer is in contact with and electrically connected to the first conductive structure.

In a package structure provided in accordance with at least one embodiment of the present disclosure, the core dielectric layer has a stiffness that is greater than one or more of the stiffness of the first dielectric layer, the stiffness of the second dielectric layer, and the stiffness of the third dielectric layer.

In the package structure provided in accordance with at least one embodiment of the present disclosure, the chip in the main chip module includes a chip substrate, and a first stiffness difference between the stiffness of the core dielectric layer and the stiffness of the chip substrate is smaller than a second stiffness difference between the stiffness of the first dielectric layer, the second dielectric layer, or the third dielectric layer and the stiffness of the chip substrate.

In the package structure provided in accordance with at least one embodiment of the present disclosure, the chip in the main chip module includes a chip substrate, and a first thermal expansion coefficient difference between a thermal expansion coefficient of the core dielectric layer and a thermal expansion coefficient of the chip substrate is smaller than a second thermal expansion coefficient difference between a thermal expansion coefficient of the first dielectric layer, the second dielectric layer, or the third dielectric layer and a thermal expansion coefficient of the chip substrate.

In the package structure provided according to at least one embodiment of the present disclosure, the core dielectric layer includes an inorganic material.

In a package structure provided in accordance with at least one embodiment of the present disclosure, the core dielectric layer includes glass.

In the package structure provided according to at least one embodiment of the present disclosure, a line width of the conductive line of the redistribution layer is smaller than a line width of the conductive line in the first conductive structure and/or the second conductive structure.

According to a package structure provided in at least one embodiment of the present disclosure, in the hybrid substrate, a sidewall of the rewiring structure is aligned with a sidewall of the main body substrate in a direction perpendicular to a main surface of the hybrid substrate.

In a package structure provided according to at least one embodiment of the present disclosure, the passive device matrix includes: the substrate comprises a first substrate part positioned in the plurality of chip areas and a second substrate part positioned in the cutting reserved area; and a dielectric structure disposed on one side of the substrate, extending continuously between the plurality of chip regions and the dicing reserved region, and including a first dielectric portion in the plurality of chip regions and a second dielectric portion in the dicing reserved region; wherein each passive device chip includes one or more passive devices disposed in or on at least one of the first substrate portion and the first dielectric portion.

In the package structure provided in accordance with at least one embodiment of the present disclosure, the dicing reserved area includes at least the second substrate portion and the second dielectric portion, and an orthographic projection of the one or more passive devices on the hybrid substrate does not overlap with an orthographic projection of the dicing reserved area on the hybrid substrate.

In the package structure provided according to at least one embodiment of the present disclosure, the dicing reserved area further includes an alignment mark disposed in or on at least one of the second substrate portion and the second dielectric portion.

In the package structure provided in accordance with at least one embodiment of the present disclosure, the passive device matrix is a capacitor matrix, and each passive device chip includes one or more capacitors.

In a package structure provided in accordance with at least one embodiment of the present disclosure, each passive device chip includes a silicon capacitor.

In the package structure provided according to at least one embodiment of the present disclosure, a plurality of capacitors of the plurality of passive device chips are connected in parallel to each other through the hybrid substrate.

In the package structure provided according to at least one embodiment of the present disclosure, further includes: and the encapsulation layer is arranged on one side of the rewiring structure of the hybrid substrate, which is far away from the main substrate, and surrounds and encapsulates the main chip module and the passive device matrix, wherein the encapsulation layer covers the side walls of the main chip module and the passive device matrix and fills a gap between the main chip module and the passive device matrix.

In a package structure provided according to at least one embodiment of the present disclosure, the plurality of passive device chips includes an edge passive device chip located at an edge of the passive device matrix, the edge passive device chip having a first chip side and a second chip side opposite or adjacent to each other; the first chip side of the edge passive device chip faces the main chip module or is close to the edge of the encapsulation layer and is encapsulated by the encapsulation layer, and the second chip side of the edge passive device chip faces other passive device chips in the passive device matrix and is adjacent to the cutting reserved area and separated from the encapsulation layer.

In the package structure provided according to at least one embodiment of the present disclosure, the main chip module includes a first chip and a second chip, and the first chip and the second chip and the plurality of passive device chips in the passive device matrix are electrically connected to each other through the rerouting structure.

In a package structure provided according to at least one embodiment of the present disclosure, the first chip includes a logic chip, and the second chip includes a memory chip.

In a package structure provided in accordance with at least one embodiment of the present disclosure, the logic chip includes a system chip, and the memory chip includes a high bandwidth memory chip.

In accordance with at least one embodiment of the present disclosure, there is provided a package structure wherein the passive device matrix and the main chip module have sides aligned in a direction parallel to a main surface of the hybrid substrate in plan view.

In the package structure provided according to at least one embodiment of the present disclosure, the at least one passive device matrix includes a plurality of passive device matrices, and the plurality of passive device matrices are disposed on the same side or different sides of the main chip module in a direction parallel to the main surface of the hybrid substrate.

The package structure provided according to at least one embodiment of the present disclosure has improved device performance and warpage may be reduced or avoided.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

Fig. 1 shows a schematic cross-section of a package.

Fig. 2 illustrates a schematic cross-sectional view of a package structure according to some embodiments of the present disclosure.

Fig. 3 illustrates a schematic cross-sectional view of a more specific structure of a package structure according to some embodiments of the present disclosure.

Fig. 4 illustrates a schematic plan view of a package structure according to some embodiments of the present disclosure.

Fig. 5 illustrates a schematic enlarged plan view of a passive device matrix according to some embodiments of the present disclosure.

Fig. 6 illustrates a schematic cross-sectional view of a passive device matrix according to some embodiments of the present disclosure.

Fig. 7 illustrates a schematic plan view of a passive device wafer, according to some embodiments of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Generally, coWoS packages include chips, interposers, and substrates (otherwise referred to as package substrates). The interposer is located between the chip and the substrate, provides interconnection between the plurality of chips, and electrically connects the chip to the substrate. CoWoS packages can be divided into three types based on the type of interposer: coWoS-S packages using a silicon substrate as an interposer, coWoS-R packages using an organic interposer including a rerouting structure, coWoS-L packages using a combination including a bridge chip and a rerouting structure as an interposer.

In CoWoS-R and CoWoS-L packages, the interposer includes an organic dielectric layer and a rerouting structure embedded in the organic dielectric layer and used to make electrical connections between the plurality of chips and the substrate. Since the interposer has an organic dielectric layer, such an interposer (i.e., including an organic dielectric layer and a rerouting structure) is also referred to as an organic interposer.

Fig. 1 shows a schematic cross-section of a package.

Referring to fig. 1, the package 50 is CoWoS packages and includes one or more host chips 10, an interposer 25, and a substrate 30. The package 50 may also be referred to as a package structure. For example, the plurality of main chips 10 are disposed on one side of the interposer 25 and electrically connected to the interposer 25. The interposer 25 includes an organic dielectric layer 20 and a re-wiring structure 21 embedded in the organic dielectric layer 20. The substrate 30 is located on a side of the interposer 25 remote from the main chip 10, and is electrically connected to the main chip 10 through the interposer 25. Package 50 is shown here as an example of a CoWoS-R package, it being understood that interposer 25 may be replaced with other types of interposers.

For example, conductive connections 26 are also provided between the interposer 25 and the substrate 30 to provide electrical connection between the interposer 25 and the substrate 30; for example, there is a gap between the interposer 25 and the substrate 30 in a direction perpendicular to the main surface of the substrate, and the interposer 25 is electrically connected to the substrate 30 through the conductive connection 26; in some examples, the package 50 further includes an underfill material layer 27 to fill the gap between the interposer 25 and the substrate 30 and to surround the protective conductive connection 26. In the package 50, the interposer 25 and the substrate 30 are separately formed by different manufacturing processes and are connected to each other by the conductive connection 26. For example, the conductive connections 26 may be or include conductive bumps, such as solder balls, for example, controlled collapse chip connection (Controlled collapsed chip connection, C4) bumps.

In CoWoS packages, the dimensions of the plurality of host chips 10 on the interposer 25 may not be perfectly matched, for example, there may be some empty areas in the chip bonding area of the interposer 25, which are detrimental to stress balance, and thus may lead to warpage of the package structure. The dummy chip 3 may be disposed in the free areas, and although the dummy chip 3 may serve to reduce package warpage, the dummy chip has substantially no other electrical function except for filling the free areas.

In CoWoS packages, passive devices are also typically included that are electrically connected to the main die on the interposer to provide corresponding electrical performance. For example, the passive device may be or include a capacitor and may be used to reduce power supply noise of the package structure. In the package structure, a power distribution network (power delivery network, PDN) provides a constant voltage rail for power/ground pins and the like of the chip, so that normal operation of the device is ensured. The impedance of the power distribution network is a frequency dependent impedance function: z (ƒ); when the ripple current I (ƒ) passes through the power distribution network, voltage noise is generated: v (ƒ) =i (ƒ) ×z (ƒ), therefore, the principle of designing a power distribution network is to reduce the impedance of the power distribution network, thereby reducing voltage noise. The impedance of the power distribution network can be reduced by adding a capacitor to the package structure, and the higher the capacitance of the capacitor, the lower the corresponding capacitance, which is more beneficial to reducing the impedance.

In CoWoS-S packages, the interposer using the silicon substrate may have passive devices embedded therein, but the interposer has limited space for embedded passive devices, for example, when the passive devices are capacitors, the capacity of the capacitors embedded in the interposer of the silicon substrate may be limited, so that its ability to reduce power supply noise is also limited. In CoWoS-R packages or CoWoS-L packages, in general, passive devices such as capacitors may not be embedded in an interposer, or passive devices such as capacitors may be embedded in an interposer of such a package, which is difficult and costly to implement.

The passive device may be mounted on the package substrate, for example, on a side of the package substrate near the interposer, or on a side of the package substrate remote from the interposer and provided with conductive terminals. For example, as shown in fig. 1, the package 50 may further include an electronic device 31, where the electronic device 31 is disposed on a side of the substrate 30 near the interposer 25, and is electrically connected to the interposer 25 through the substrate 30 and the conductive connector 26, and further electrically connected to the main chip 10 through the interposer 25. The electronic device 31 is a passive device such as a ceramic capacitor. In some examples, passive devices (e.g., capacitors) may also be disposed on a side of the substrate 30 away from the interposer 25, and a connector 35 (or conductive terminal) may also be disposed on a side of the substrate 30 away from the interposer 25 for external connection of the package 50; for example, the package 50 may be connected to the power source terminal through a plurality of connectors 35. That is, the passive device may be disposed on the same side of the package substrate as the connection member.

The passive device mounted on the packaging substrate needs to be electrically connected to the main chip positioned on the interposer through the packaging substrate and the interposer, and the connection path between the passive device and the main chip is far, so that the passive device can not provide corresponding electrical performance better; for example, when the passive device is a filter capacitor, a far connecting path may make the filtering effect of the capacitor limited, and thus the power noise cannot be reduced well. In addition, the passive device is mounted on the package substrate (for example, on a side thereof close to the interposer) to occupy an additional area of the package substrate, resulting in a larger overall size of the package structure; if the passive device is mounted on the side of the package substrate remote from the interposer, then a portion of the conductive terminal area is sacrificed to provide the passive device, which may have an adverse effect on the larger power chip.

In view of the foregoing, an embodiment of the present disclosure provides a package structure, including: the hybrid substrate comprises a main body substrate and a rerouting structure, wherein the main body substrate comprises a core layer, a first stacking layer and a second stacking layer, the first stacking layer and the second stacking layer are arranged on two opposite sides of the core layer in the direction perpendicular to the main surface of the hybrid substrate, and the rerouting structure is arranged on one side, far away from the core layer, of the first stacking layer, is in contact with and is electrically connected with the main body substrate; the main chip module and at least one passive device matrix are electrically connected through the hybrid substrate and are arranged side by side on one side of the rewiring structure away from the main substrate in a direction parallel to the main surface of the hybrid substrate, wherein each passive device matrix is provided with a plurality of chip areas and a cutting reserved area and comprises a plurality of passive device chips respectively arranged on the plurality of chip areas, the plurality of passive device chips are arranged side by side in the direction parallel to the main surface of the hybrid substrate and are separated from each other by the cutting reserved area, and the passive device matrix is provided with a substrate continuously extending in the plurality of chip areas and the cutting reserved area.

In the embodiment of the disclosure, the hybrid substrate is configured to include a main body substrate and a rerouting structure, and the rerouting structure and the main body substrate are in direct contact and are electrically connected, and the main chip module and the passive device matrix are electrically connected through the hybrid substrate and are arranged on one side of the rerouting structure side by side; in this way, the hybrid substrate may replace both the interposer and the substrate in the package shown in fig. 1, i.e. the package substrate integrating the interposer and the substrate together, or may be referred to as a hybrid package substrate. Further, the main body substrate and the rewiring structure in the hybrid substrate are electrically connected in direct contact without being connected to each other by an intermediate member such as a solder ball, and thus the connection path between the rewiring structure and the main body substrate, that is, the signal transmission path, is shortened, so that the signal transmission efficiency can be improved, and the signal loss can be reduced. Moreover, compared with the package shown in fig. 1 in which the main chip is mounted on the interposer and the passive devices are mounted on the substrate, the main chip module and the passive device matrix of the present disclosure are disposed side by side on the rewiring structure of the package structure, so that the distance between the main chip module and the passive device matrix is closer, and the connection path between the main chip module and the passive device matrix is shortened, so that the passive device matrix can better provide the corresponding electrical performance for the main chip module. Therefore, the device performance of the package structure is improved.

On the other hand, the main chip module and the passive device matrix are arranged on one side of the mixed substrate side by side, so that the stress of the packaging structure can be balanced, and the warping of the packaging structure is reduced or avoided. Moreover, compared to disposing a plurality of passive device chips independent of each other on a hybrid substrate separately, the plurality of passive device chips of the passive device matrix of the embodiments of the present disclosure are disposed on the hybrid substrate in a matrix form, which can reduce the space occupied by the passive device chips, improve the integration level of the passive device chips, and can be more advantageous to reduce the warpage of the package structure, and can simplify the manufacturing process, and is advantageous to reduce the overall size of the package structure, and there is no need to sacrifice the area of the hybrid substrate on the side away from the main chip module for disposing the conductive terminals, so that the side of the hybrid substrate on the side away from the main chip module can be used to dispose a sufficient number of conductive terminals to provide electrical connection of the package structure with external components (e.g., power terminals).

In addition, compared with the manner of arranging the dummy chip in the package of fig. 1 to reduce warpage, the embodiment of the disclosure not only can reduce or avoid warpage by arranging the passive device matrix, but also can provide corresponding electrical performance; that is, the function of reducing warpage of the dummy chip and the function of the passive device are integrated together, which can also be advantageous in reducing the package size and reducing the package cost.

Referring to fig. 2, in some embodiments, a package structure 500 includes a hybrid substrate 400, a main chip module 110, and at least one passive device matrix 120. For example, the hybrid substrate 400 includes a main body substrate 350 and a rerouting structure 210; the redistribution structure 210 is disposed on the main substrate 350, and is in contact with and electrically connected to the main substrate 350. For example, the body substrate 350 includes a core layer (core layer) 300, a first build-up layer (build-up layer) 310, and a second build-up layer 320 electrically connected to each other; the first and second buildup layers 310 and 320 are disposed on opposite sides of the core layer 300 in a direction perpendicular to the main surface of the hybrid substrate 400, and the rewiring structure 210 is disposed on a side of the first buildup layer 310 remote from the core layer 300, in contact with and electrically connected to the first buildup layer 310. For example, the rewiring structure 210 and the first build-up layer 310 are located on a side of the core layer 300 that is proximate to the main chip module 110 and the passive device matrix 120, while the second build-up layer 320 is located on a side of the core layer 300 that is distal from the main chip module 110 and the passive device matrix 120. In this context, the main surface of the hybrid substrate refers to its surface on the side closer to or farther from the main chip module, and is for example a surface extending in the horizontal direction as shown.

The main chip module 110 and the passive device matrix 120 are electrically connected to the hybrid substrate 400 and to each other through the hybrid substrate 400, and may be disposed side by side on a side of the re-wiring structure 210 of the hybrid substrate 400 away from the main body substrate 350 in a direction parallel to the main surface of the hybrid substrate 400. That is, the rewiring structure 210 is located between the main chip module 110 and the main substrate 350 and between the passive device matrix 120 and the main substrate 350. In some embodiments, each of the passive device matrices 120 has a plurality of chip regions 121 and dicing reserved regions 122, and includes a plurality of passive device chips 120a respectively disposed at the plurality of chip regions 121, the plurality of passive device chips 120a being disposed side by side in a direction parallel to a main surface of the hybrid substrate and being spaced apart from each other by the dicing reserved regions 122, wherein the passive device matrix 120 has a substrate continuously extending at the plurality of chip regions 121 and the dicing reserved regions 122.

In some embodiments, at least portions of the main chip module 110 and the passive device matrix 120 are electrically connected to each other by a rewiring structure 210. For example, the rewiring structure 210 is primarily used to provide electrical connections between one or more chips in the main chip module 110 and a plurality of passive device chips in the passive device matrix 120, and to electrically connect the main chip module 110 and the passive device matrix 120 to the host substrate 350, such as may enable interconnection of signals and power supplies. The host substrate 350 may provide electrical connection between the host chip module 110 and the passive device matrix 120 and the conductive terminals 370. Portions of the host substrate 350 may also be used to provide electrical connections between the host chip module 110 and the passive device matrix 120.

For example, a plurality of conductive terminals 370 may be provided at a side of the hybrid substrate 400 remote from the main chip module 110 (i.e., a side of the second buildup layer 320 remote from the core layer 300). The conductive terminals 370 may be or include solder balls (solder balls), such as Ball Grid Arrays (BGA). However, the disclosure is not limited thereto. For example, the package structure 500 may be further connected to other external components, such as a printed circuit board (printed circuit board, PCB), through the conductive terminals 370.

Fig. 3 illustrates a schematic cross-sectional view of a more specific structure of a package structure 500 according to some embodiments of the present disclosure.

Referring to fig. 3, in some embodiments, a core layer 300 includes a core dielectric layer 301 and a conductive member 302; the first build-up layer 310 includes a first dielectric layer 305 and a first conductive structure 306; the second build-up layer 320 includes a second dielectric layer 307 and a second conductive structure 308; the re-wiring structure 210 may include a third dielectric layer 200 and a re-wiring layer 205.

For example, the conductive members 302 in the core layer 300 may include conductive vias through the core dielectric layer 301 and/or conductive lines on opposite sides of the core dielectric layer, the conductive lines and conductive vias being connected to each other and to conductive layers in the build-up layer. The core dielectric layer 301 may be a single layer or a multi-layer structure, which is not limited by the present disclosure.

For example, the first conductive structure 306 of the first build-up layer 310 may be at least partially embedded in the first dielectric layer 305 and may include one or more layers of conductive lines and/or conductive vias that may be used to provide electrical connections between conductive lines of different layers, electrical connections between the conductive lines and the conductive members 302 of the core layer 300, and/or electrical connections between the conductive lines and the rewiring layer 205.

For example, the second conductive structure 308 of the second build-up layer 320 may be at least partially embedded in the second dielectric layer 307 and may include one or more layers of conductive lines, conductive vias, and/or conductive pads, which may be used to provide electrical connections between conductive lines of different layers, between conductive lines and the conductive members 302 of the core layer 300, and/or between conductive lines and conductive pads; the conductive pad may be used to connect the conductive terminal 370, and may be embedded in the second dielectric layer 307 or may protrude from a surface of the second dielectric layer 307 on a side away from the core layer 300. It should be appreciated that the conductive vias in the first buildup layer and the second buildup layer are not specifically shown for the sake of brevity in the drawings. The first dielectric layer 305 and the second dielectric layer 307 may each be a single-layer or multi-layer structure, and the present disclosure is not limited thereto.

For example, the re-wiring structure 210 may have one or more re-wiring layers (redistribution layer, RDL) 205, and the one or more re-wiring layers 205 may be at least partially embedded in the third dielectric layer 200. The third dielectric layer 200 may be a single-layer or multi-layer structure, and the present disclosure is not limited thereto; each redistribution layer 205 may include conductive lines 201 and/or conductive vias 202. For example, the conductive vias may be used to provide electrical connections between conductive lines located in different layers, electrical connections between the conductive lines and the first conductive structures 306 of the first build-up layer 310, and/or electrical connections between the conductive lines and the main chip module and the matrix of passive devices.

With continued reference to fig. 3, the first conductive structure 306, the conductive member 302, and the second conductive structure 308 of the body substrate 350 are electrically connected to one another. The redistribution layer 205 is electrically connected to the first conductive structure 306, and further connected to other conductive elements of the host substrate through the first conductive structure 306. In the disclosed embodiment, the re-wiring structure 210 is included in the hybrid substrate 400 with the third dielectric layer 200 in contact with the first dielectric layer 305 of the host substrate and the re-wiring layer 205 in contact with the first conductive structure 306 of the host substrate to be electrically connected. In contrast to the package shown in fig. 1, the redistribution structure 210 of the package structure 500 and the main substrate 350 are in direct contact and electrically connected without being connected by an intermediate member such as a conductive connector therebetween. Therefore, the signal transmission path in the packaging structure is shortened, the signal transmission efficiency is improved, and the signal loss or attenuation can be reduced. In some embodiments, the hybrid substrate 400 may facilitate the transmission of high frequency signals.

In the hybrid substrate 400, the conductive member 302, the first conductive structure 306, the second conductive structure 308, and the rewiring layer 205 may each comprise a suitable conductive material, such as a metallic material, e.g., titanium, copper, or the like. The first dielectric layer 305, the second dielectric layer 307, and the third dielectric layer 200 may each comprise an organic dielectric material, and the materials of the dielectric layers may be the same or different from each other. For example, the materials of the first dielectric layer 305, the second dielectric layer 307, and the third dielectric layer 200 may be at least one dielectric material selected from Polyimide (PI), a polyimide film (ABF), a resin (e.g., BT), and the like.

In some embodiments, the material of the core dielectric layer 301 may be different from the material of the first dielectric layer 305, the second dielectric layer 307, and the third dielectric layer 200. For example, the stiffness of the core dielectric layer 301 is greater than one or more of the stiffness of the first dielectric layer 305, the stiffness of the second dielectric layer 307, and the stiffness of the third dielectric layer 200; for example, the first dielectric layer 305, the second dielectric layer 307, and the third dielectric layer 200 may each have a stiffness that is less than the stiffness of the core dielectric layer 301. That is, the Young's modulus (Young's modulus) of the core dielectric layer 301 is greater than the Young's modulus of one or more of the first dielectric layer 305, the second dielectric layer 307, the third dielectric layer 200; for example, the young's modulus of the first dielectric layer 305, the second dielectric layer 307, and the third dielectric layer 200 may each be less than the young's modulus of the core dielectric layer 301.

In some embodiments, the core dielectric layer 301 has a coefficient of thermal expansion that is less than the coefficient of thermal expansion of one or more of the first dielectric layer 305, the second dielectric layer 307, and the third dielectric layer 200; for example, the first dielectric layer 305, the second dielectric layer 307, and the third dielectric layer 200 may each have a coefficient of thermal expansion that is greater than the coefficient of thermal expansion of the core dielectric layer 301.

In some embodiments, the stiffness of the core dielectric layer may be more matched to the stiffness of the chip substrate of the chip in the main chip module than the first through third dielectric layers; for example, a first stiffness difference between the stiffness of the core dielectric layer and the stiffness of the chip substrate is less than a second stiffness difference between the stiffness of the first, second, or third dielectric layers and the stiffness of the chip substrate.

In some embodiments, the core dielectric layer may have a coefficient of thermal expansion that more closely matches the coefficient of thermal expansion of the chip substrate of the chip in the main chip module than the first through third dielectric layers; for example, a first coefficient of thermal expansion difference between the coefficient of thermal expansion of the core dielectric layer and the coefficient of thermal expansion of the chip substrate is less than a second coefficient of thermal expansion difference between the coefficient of thermal expansion of the first dielectric layer, the second dielectric layer, or the third dielectric layer and the coefficient of thermal expansion of the chip substrate.

For example, the main chip module 110 includes one or more chips, and each chip may include a chip substrate S and a device layer D on the chip substrate S. The chip substrate S may be or comprise a semiconductor substrate, for example a silicon substrate, which may alternatively or additionally comprise other suitable semiconductor materials, for example germanium or the like. The device layer D is disposed on one side of the chip substrate S, and may include active devices (e.g., transistors), passive devices (e.g., capacitors, inductors, etc.), or a combination thereof, as well as an interconnection structure through which the devices may be connected. It should be understood that the chip substrates of different chips may comprise the same or different semiconductor materials, and that the device layers of different chips may comprise the same or different devices. The rigidity, thermal expansion coefficient, and the like of the chip substrates of the plurality of chips are not greatly different, and may be substantially the same, for example.

In some embodiments, the stiffness and/or coefficient of thermal expansion of the core dielectric layer 301 may be matched, i.e., have a small difference, with the stiffness and/or coefficient of thermal expansion of the chip substrate S. For example, the difference in stiffness between the core dielectric layer 301 and the chip substrate S is smaller than at least one of the difference in stiffness between the first dielectric layer 305 and the chip substrate S, the difference in stiffness between the second dielectric layer 307 and the chip substrate S, and the difference in stiffness between the third dielectric layer 200 and the chip substrate S. For example, the stiffness difference between the first through third dielectric layers and the chip substrate is greater than the stiffness difference between the core dielectric layer and the chip substrate.

For example, the difference in thermal expansion coefficient between the core dielectric layer 301 and the chip substrate S is smaller than at least one of the difference in thermal expansion coefficient between the first dielectric layer 305 and the chip substrate S, the difference in thermal expansion coefficient between the second dielectric layer 307 and the chip substrate S, and the difference in thermal expansion coefficient between the third dielectric layer 200 and the chip substrate S. For example, the difference in thermal expansion coefficients between the first to third dielectric layers and the chip substrate is greater than the difference in thermal expansion coefficients between the core dielectric layer and the chip substrate.

For example, the core dielectric layer includes an inorganic material. For example, the core dielectric layer comprises glass. The core dielectric layer can have better thermal stability and mechanical strength by adopting the materials. For example, the thermal stability and mechanical strength of the core dielectric layer of embodiments of the present disclosure are superior to those of some substrates using organic materials.

In the embodiments of the present disclosure, by providing the above-described material of the core dielectric layer, i.e., providing the core dielectric layer with a greater stiffness, a smaller coefficient of thermal expansion, and/or providing the stiffness and/or coefficient of thermal expansion of the core dielectric layer, etc. to match the chip substrate, the risk of warpage of the package structure may be reduced.

With continued reference to fig. 3, in some embodiments, the conductive lines of the rewiring layer 205 are finer than the conductive lines in the bulk substrate 350. For example, the linewidth of the conductive lines of the redistribution layer 205 may be less than the linewidth of the conductive lines of the first conductive structure 306 and/or the linewidth of the conductive lines of the second conductive structure 308; for example, the line width of the conductive lines of the re-wiring layer 205 is smaller than the line width of the conductive lines of the first conductive structure 306 and smaller than the line width of the conductive lines of the second conductive structure 308; the line width of the conductive lines in the first conductive structure 306 and the line width of the conductive lines in the second conductive structure 308 may be substantially the same. For example, the wire spacing between the conductive wires of the rewiring layer 205 is less than the wire spacing between the conductive wires in the first conductive structure 306 and/or the wire spacing between the conductive wires in the second conductive structure 308; for example, the wire spacing between the conductive wires in the rewiring layer 205 is less than the wire spacing between the conductive wires in the first conductive structure 306 and less than the wire spacing between the conductive wires in the second conductive structure 308; the spacing between the conductive lines in the first conductive structure 306 and the spacing between the conductive lines in the second conductive structure 308 may be substantially the same.

It should be understood that the line width of the conductive line refers to the width of the conductive line in the width direction thereof, and the width direction of the conductive line is perpendicular to the extending direction of the conductive line; the line pitch between conductive lines refers to the center-to-center distance (pitch) between two adjacent conductive lines, i.e., is approximately equal to the sum of the spacing between two adjacent conductive lines and the width of the conductive lines.

In some embodiments, the number of layers of conductive lines in the first conductive structure 306, the second conductive structure 308, and the rewiring layer 205 may be the same or different from each other; for example, the number of layers of conductive lines in the first conductive structure 306 and the second conductive structure 308 may be the same as each other and may be different from the number of layers of conductive lines in the rewiring layer 205; for example, the number of layers of conductive lines in the rewiring layer 205 may be less than the number of layers of conductive lines in the first conductive structure 306 and/or the number of layers of conductive lines in the second conductive structure 308.

For example, the thicknesses of the first dielectric layer 305, the second dielectric layer 307, and the third dielectric layer 200 may be the same or different from each other; for example, the thicknesses of the first dielectric layer 305 and the second dielectric layer 307 may be substantially the same as each other; for example, the thickness of the third dielectric layer 200 may be less than the thickness of the first dielectric layer 305 and/or the thickness of the second dielectric layer 307. That is, the rerouting structure 210 may have a smaller overall thickness than the first buildup layer 310 and the second buildup layer 320.

In some embodiments, at least portions of the main chip module 110 and the passive device matrix 120 are electrically connected to each other through the rewiring structure 210 of the hybrid substrate 400. For example, at least some of the plurality of chips in the main chip module 110 may be electrically connected to each other through the rewiring structure 210; for example, the plurality of chips of the main chip module 110 and at least some of the plurality of passive device chips of the passive device matrix may be electrically connected to each other by the rewiring structure 210. For example, the plurality of chips of the main chip module 110 and some of the plurality of passive device chips of the passive device matrix may also be electrically connected to each other through the rewiring structure 210 and the conductive elements in the body substrate 350.

In some embodiments, different routing requirements may be met by providing the conductive lines of the bulk substrate and the conductive lines of the rewiring structure in the hybrid substrate 400 with different linewidth pitches.

In some embodiments, the hybrid substrate 400 further includes a solder mask (solder mask) 360. For example, the solder resist layer 360 is disposed on a side of the body substrate 350 away from the re-wiring structure 210, covers a surface of the side of the body substrate 350, and has an opening to expose a portion of a surface (e.g., a surface of a conductive pad) of the second conductive structure in the second buildup layer 320, such that the conductive terminal 370 can be electrically connected with the second conductive structure through the opening of the solder resist layer 360.

In some embodiments, since the body substrate 350 and the rerouting structure 210 are in direct contact, no solder resist layer may be provided on the side of the body substrate 350 proximate to the rerouting structure 210.

With continued reference to fig. 3, in some embodiments, each chip in the master chip module 110 is electrically connected to the hybrid substrate 400 through a first conductive bump 107, and each passive device chip 120a in the passive device matrix 120 is electrically connected to the hybrid substrate 400 through a second conductive bump 108. The first conductive bump 107 is disposed between each chip of the main chip module and the rewiring layer to electrically connect the chip to the rewiring structure; the second conductive bumps 108 are disposed between the passive device matrix and the rewiring layer to electrically connect the passive device chip to the rewiring structure. For example, the first conductive bump 107 and the second conductive bump 108 may each be or include a conductive bump such as a micro-bump (micro-bump).

In some embodiments, the package structure 500 further includes an underfill layer 160 filling the space between the main chip module 110 and the rerouting structure 210 and the space between the passive device matrix 120 and the rerouting structure 210 and surrounding the first conductive bump 107 and the second conductive bump 108 in a direction parallel to the major surface of the hybrid substrate.

In some embodiments, the package structure 500 further includes an encapsulation layer 180 disposed on the hybrid substrate 400, for example, on a side of the rewiring structure 210 remote from the host substrate 350, and surrounding the encapsulated host chip module 110 and the passive device matrix 120. For example, the encapsulation layer 180 covers and contacts the sidewalls of the main chip module 110, the sidewalls of the passive device matrix 120, and fills the gap between the main chip module 110 and the passive device matrix 120. In some embodiments, the encapsulation layer 180 may also cover the surfaces of the main chip module 110 and the passive device matrix 120 on the side away from the hybrid substrate 400, wherein the surfaces of the main chip module 110 and the passive device matrix 120 on the side away from the rewiring structure 210 (i.e., the upper surface shown in fig. 3) may be substantially flush in a direction parallel to the hybrid substrate main surface. In alternative embodiments, the surface of the encapsulation layer 180 on the side away from the hybrid substrate 400, the surface of the main chip module 110 on the side away from the hybrid substrate 400, and the surface of the passive device matrix 120 on the side away from the rewiring structure 210 may be substantially flush in a direction parallel to the hybrid substrate main surface; that is, the surfaces of the main chip module 110 and the passive device matrix 120 on the side away from the hybrid substrate 400 may be exposed without being covered by the encapsulation layer 180.

Fig. 4 illustrates a schematic plan view of a package structure 500 according to some embodiments of the present disclosure. Fig. 3 is, for example, a cross-sectional view taken along line I-I' of fig. 4.

Referring to fig. 3 and 4, in some embodiments, the re-routing structure 210 and the bulk substrate 350 of the hybrid substrate 400 may have substantially the same dimensions (e.g., width, area, etc.) in a direction parallel to the hybrid substrate major surfaces. Orthographic projections of the redistribution structure 210 and the bulk substrate 350 on a major surface of the hybrid substrate (or a reference plane parallel to the major surface) may coincide with each other. For example, as shown in fig. 3, the sidewalls of the redistribution structure 210 and the sidewalls of the bulk substrate 350 may be substantially aligned with each other in a direction perpendicular to the major surfaces of the hybrid substrate.

For example, the re-wiring structure 210 is formed directly on the main body substrate 350, and the re-wiring structure 210 is formed to have substantially the same size as the main body substrate 350. In the embodiment of the present disclosure, the hybrid substrate 400 integrates the re-wiring structure 210 and the main body substrate 350, which can simplify the process flow and reduce the process cost.

In some embodiments, the main chip module 110 includes one or more chips, which may each be a system on chip (SoC), a Digital Signal Processor (DSP) chip, a graphics processor (graphic processing unit, GPU), an Application Specific Integrated Circuit (ASIC) chip, a memory chip, or the like. For example, the main chip module 110 includes a plurality of chips, and the plurality of chips may include the same type or different types of chips therein. The plurality of chips are disposed side by side on the hybrid substrate and may be electrically connected to each other through the hybrid substrate.

For example, the master chip module 110 includes one or more first chips 101 and one or more second chips 102a, 102b, 102c, 102d; the one or more first chips and the one or more second chips are electrically connected to each other through the hybrid substrate. For example, the first chip, the second chip, and the plurality of passive device chips are electrically connected to each other through a rewiring structure in the hybrid substrate. For example, the one or more first chips may include a logic chip, which may include, for example, a system on chip (SoC); the one or more second chips may include memory chips, which may include, for example, high bandwidth memory (high bandwidth memory, HBM) chips.

For example, each chip in the main chip module may include the chip substrate and the device layer shown in fig. 3, and the conductive bumps are disposed on a side of the device layer remote from the chip substrate. The side of the chip with the conductive bumps or near the device layer may be referred to as the front or active side of the chip and the side of the chip where the substrate is located (i.e., the side opposite the front side) may be referred to as the back side. For example, each chip in the main chip module may be flip-chip mounted on the hybrid substrate such that its front side faces the re-wiring structure of the hybrid substrate, and may be electrically connected to the re-wiring structure through conductive connectors such as conductive bumps.

In some embodiments, a plurality of passive device matrices 120 and a plurality of chips in the main chip module 110 are disposed side-by-side on a hybrid substrate, with the passive device matrices being spaced apart from adjacent chips.

Fig. 5 illustrates a schematic enlarged plan view of a passive device matrix 120 and a schematic enlarged view of a passive device chip in the passive device matrix, according to some embodiments of the present disclosure; fig. 6 illustrates a schematic cross-sectional view of a passive device matrix taken along line A-A of fig. 5, according to some embodiments of the present disclosure.

Referring to fig. 3 to 6, the passive device matrix 120 has a plurality of chip regions 121 and a dicing reserved region 122, and includes a plurality of passive device chips 120a respectively located in the plurality of chip regions 121. In each passive device matrix 120, the plurality of chip regions 121 may be disposed side by side in a direction parallel to the main surface of the hybrid substrate, for example, may be arranged in an array including one or more rows and/or one or more columns along the first direction D1, the second direction D2; a dicing reserved area 122 is located around each chip area 121 and separates adjacent chip areas 121. Each chip region 121 corresponds to one passive device chip 120a, i.e., the passive device matrix 120 includes a plurality of passive device chips 120a, the plurality of passive device chips 120a being disposed side by side (e.g., arranged in an array) and spaced apart from each other by dicing the reserved areas 122. The first direction D1 and the second direction D2 intersect each other, for example, perpendicularly to each other.

For example, the plurality of passive device chips 120a may have substantially the same size; the plurality of passive device chips 120a located in the same row may be substantially aligned with each other in the first direction D1, for example, have sidewalls (or referred to as sides) aligned with each other in the first direction D1; the plurality of passive device chips 120a located in the same column may be substantially aligned with each other in the second direction D2, for example, having sidewalls aligned with each other in the second direction D2.

For example, the cut-and-hold region 122 may be in a grid shape; for example, the cut-and-hold region 122 may have a first sub-region 122a extending in the first direction D1 and a second sub-region 122b extending in the second direction D2. For example, the plurality of first sub-regions 122a extend in the first direction D1 in parallel with each other and are arranged in the second direction D2; the plurality of second sub-areas 122b extend in the second direction D2 in parallel with each other and are arranged in the first direction D1; the plurality of first sub-regions 122a and the plurality of second sub-regions 122b intersect each other and define a plurality of chip regions 121. Each chip region 121 may be surrounded by a dicing reserved region 122.

Referring to fig. 5 and 6, in some embodiments, the passive device matrix 120 includes a substrate 100, a dielectric structure 105 disposed on one side of the substrate 100, and a plurality of passive devices 106. The substrate 100 may be a semiconductor substrate, such as a silicon substrate, and the substrate may alternatively or additionally include other suitable semiconductor materials, such as germanium and the like. For example, the material of the dielectric structure 105 may include a silicon-containing material, such as silicon oxide, silicon nitride, silicon oxynitride, the like, combinations thereof, or the like, and may be a single-layer structure or a multi-layer structure, such as a multi-layer structure including a plurality of dielectric layers. A plurality of passive devices 106 are disposed in the chip region 121, and at least a portion of the passive devices 106 may be embedded in at least one of the substrate 100 and the dielectric structure 105.

For example, the substrate 100 continuously extends in the plurality of chip regions 121 and the dicing reserved region 122, and includes a first substrate portion 100a located in the plurality of chip regions 121 and a second substrate portion 100b located in the dicing reserved region 122. The plurality of first substrate portions 100a and the second substrate portions 100b are in contact with and continuous with each other and have the same material. That is, the substrate 100 including the plurality of first and second substrate portions 100a and 100b is a continuous substrate integrally formed, and no other material layer may be interposed between the first and second substrate portions without an interface (interface) therebetween. It should be understood that the boundaries between the chip regions and the dicing reserved regions are shown in dashed lines for ease of illustration only and do not represent interfaces between the chip regions and the dicing reserved regions.

For example, the dielectric structure 105 extends continuously in the plurality of chip regions 121 and the dicing reserved region 122, and includes a first dielectric portion 105a located in the plurality of chip regions 121 and a second dielectric portion 105b located in the dicing reserved region 122. The plurality of first dielectric portions 105a and the second dielectric portion 105b are in contact with each other and continuous, and have the same material. It is understood that the continuous extension of the dielectric structure 105 in the chip region and the dicing reserved region means that one or more dielectric layers in the dielectric structure 105 each extend continuously in these regions, and that portions of the plurality of first dielectric portions and second dielectric portions located in the respective dielectric layers are in contact with each other and continuous without an interface therebetween.

That is, the plurality of passive device chips 120a and the dicing reserved area 122 located in the plurality of chip areas 121 share the same substrate 100 and share the same dielectric structure 105. In some embodiments, each passive device chip 120a includes one or more passive devices 106 disposed in or on at least one of the first substrate portion 100a and the first dielectric portion 105a of the respective chip region 121. It should be understood that the number, location, structure, etc. of passive devices of each chip region 121 shown in the drawings are illustrative, and the disclosure is not limited thereto.

In some embodiments, the cut-and-hold region 122 includes at least the second substrate portion 100b and the second dielectric portion 105b. One or more passive devices 106 of the plurality of passive device chips 120a may not extend into the dicing reserved area 122. The orthographic projection of one or more passive devices 106 of passive device chip 120a onto a reference plane extending in a direction parallel to the major surface of the substrate is offset from the orthographic projection of dicing retention 122 onto the reference plane, such as the major surface of hybrid substrate 400 shown in fig. 3. In this context, staggering of the orthographic projections of a plurality of members on the same reference plane means that the orthographic projections of the plurality of members do not overlap, and includes the case where the orthographic projections of the plurality of members are spaced apart from one another but do not overlap, as well as the case where the orthographic projections of the plurality of members are adjacent to one another but do not overlap.

In some embodiments, the cut-and-hold region 122 is also provided with an alignment mark (ALIGN MARK), which may be disposed in or on at least one of the second substrate portion 100b and the second dielectric portion 105 b. For example, the dicing reserved area 122 has the alignment mark 103 disposed on the second dielectric portion 105 b. It should be understood that the number, shape, and position of the alignment marks 103 are merely illustrative, and the disclosure is not limited thereto, and the alignment marks can be designed according to actual product requirements.

In some embodiments, the passive device matrix 120 is an integrated passive device matrix, and the passive device chips therein include capacitors therein, or may also include other types of passive devices. For example, the passive device matrix 120 is a capacitive matrix and each passive device chip includes one or more capacitances, which may be or include, for example, silicon capacitances. For example, the passive device 106 is a capacitor, such as any suitable type of capacitor, such as a metal-insulator-metal (MIM) capacitor, a deep trench capacitor (DEEP TRENCH capacitor, DTC), or the like. Fig. 6 schematically illustrates an electrode plate embedded in a dielectric structure of a capacitor, but the capacitor structure of the embodiment of the disclosure is not limited thereto.

Referring to fig. 3 to 6, the passive device matrix 120 further includes a plurality of second conductive bumps 108 disposed on the plurality of chip regions 121; the second conductive bump 108 is electrically connected to the passive device 106 of the passive device chip 120a and serves as an external connection point for the passive device chip 120a, for example, for electrical connection between the passive device chip 120a and the rewiring structure. For example, a plurality of second conductive bumps 108 electrically connected to respective electrode plates of one or more capacitors may be provided in each passive device chip 120 a. The second conductive bump 108 may be a single-layer or multi-layer structure, and may include a metallic material such as titanium, copper, nickel, tin, silver, or an alloy thereof, or a combination thereof. For example, in some examples, the second conductive bump 108 may be a multi-layer structure and include a first metal layer, a second metal layer, and a solder layer stacked in sequence over the substrate; for example, the first metal layer may be or include a titanium copper (TiCu) layer, the second metal layer may be or include a nickel layer, and the solder layer may include tin silver (SnAg), but the disclosure is not limited thereto. The type, size (e.g., width, area, spacing) and the like of the plurality of second conductive bumps 108 may be set and adjusted according to product requirements.

In some embodiments, where the passive device matrix 120 is a capacitive matrix, the plurality of capacitances of the plurality of passive device chips 120a in the passive device matrix 120 may be parallel to each other, e.g., may be parallel to each other through a re-wiring structure of the hybrid substrate and/or the host substrate; in the case where the same passive device chip 120a includes a plurality of capacitances, the plurality of capacitances may also be connected in parallel with each other. When a plurality of passive device matrices 120 are provided in the package structure, a plurality of capacitors of the plurality of passive device matrices 120 may also be connected in parallel with each other. The capacitors are connected in parallel, so that the overall capacitance of the passive device matrix can be increased, capacitance resistance and impedance in a circuit of the packaging structure can be reduced, and power supply noise of the packaging structure can be reduced.

Referring to fig. 3-5, in some embodiments, an edge passive device chip may be included in the plurality of passive device chips 120 of the passive device matrix 120, located at an edge of the passive device matrix 120, such as may be adjacent to the main chip module 110 or near an edge of the encapsulation layer 180. For example, the passive device matrix 120 is arranged in an array of n×m (i.e., n rows and m columns, where n≡1, m≡1, and m+n > 2), and the passive device chips 120 located in the 1 st row, n-th row, 1 st column, and m-th column are edge passive device chips. That is, the edge passive device chip is an outermost passive device chip among the plurality of passive device chips of the passive device matrix; the edges of the matrix of passive devices include the sidewalls of the matrix of passive devices and a partial region adjacent to the sidewalls thereof.

For example, one side of the edge passive device chip may be adjacent to (e.g., facing) the main chip module or near the edge of encapsulation layer 180 and be encapsulated (i.e., encapsulated) by encapsulation layer 180, and the other side of the edge passive device chip is adjacent to the other passive device chips, adjacent to cut-and-hold region 122, and separated from encapsulation layer 180.

For example, an edge passive device chip has a first chip side and a second chip side opposite or adjacent to each other; the first chip side surface of the edge passive device chip faces the main chip module or is close to the edge of the encapsulation layer and is encapsulated by the encapsulation layer; the second chip side of the edge passive device chip faces other passive device chips in the passive device matrix and is adjacent to the dicing reserved area and separated from the encapsulation layer.

For example, in the example of the passive device matrix 120 shown in fig. 5 arranged in a 5×8 (i.e., 5 rows and 8 columns) array, the passive device chips 120a located in the 1 st row, 5 th row, 1 st column, and 8 th column are edge passive device chips, in conjunction with fig. 3 to 5. For example, at least one side of the edge passive device chip is facing the main chip module or near the encapsulation layer edge, and at least another side of the edge passive device chip is facing the other passive device chips and abuts the dicing retention 122.

For example, the edge passive device chip may have a first chip side a1 and a second chip side a2 adjacent to each other or opposite in a direction parallel to the main surface of the hybrid substrate (e.g., the first direction D1 or the second direction D2), the first chip side a1 of the edge passive device chip facing the main chip module or the edge near the encapsulation layer and being encapsulated (i.e., encapsulated) by the encapsulation layer; while the second chip side a2 of the edge passive device chip faces the other passive device chips and is adjacent to the dicing reserved area 122 and separated from the encapsulation layer. The dicing reserved area 122 located at the edge passive device chip second chip side a2 is located between the edge passive device chip and the adjacent passive device chip and is separated from the encapsulation layer.

In some embodiments, the first chip side a1 of the edge passive device chip may also be provided with a dicing reserved area 122, or the first chip side a1 of the edge passive device chip may be directly exposed at the side wall of the passive device matrix, while the side may not be provided with a dicing reserved area. The encapsulation of the first chip side a1 of the edge passive device chip by the encapsulation layer may include that a surface of a portion of the edge cut-and-remain region located at the first chip side a1 of the edge passive device chip is covered by and in contact with the encapsulation layer, or that a side surface of the first chip side a1 of the edge passive device chip is covered by and in contact with the encapsulation layer.

Referring to fig. 4, in some embodiments, the rerouting structure 210 of the hybrid substrate 400 has a die bonding region BR for bonding the main chip module 110 and the passive device matrix 120. For example, the die bonding region BR may be centrally disposed on the hybrid substrate 400, i.e., the center of the die bonding region BR may coincide with the center of the hybrid substrate 400 (e.g., the center of the rewiring structure 210, the center of the body substrate 350) in plan view, the die bonding region BR may be a structure symmetrical about a center line extending through the center, and the hybrid substrate 400 may be a structure symmetrical about the center line.

The die bonding region BR has a first bonding region R1 and a second bonding region R2, the first bonding region R1 being for bonding one or more dies in the main die module 110 and may also be referred to as a main die bonding region; the second bonding region R2 is used to bond the matrix of passive devices 120 and may also be referred to as a passive device bonding region. In the die bonding region BR, there may be one or more second bonding regions R2; in the case of having a plurality of second bonding regions R2, the plurality of second bonding regions R2 may be located on the same side or different sides of the first bonding region R1 in a direction parallel to the main surface of the hybrid substrate. For example, all chips in the main chip module 110 are disposed in the first bonding region R1, and each of the second bonding regions R2 may be correspondingly provided with one passive device matrix 120; that is, the passive device matrix 120 may be disposed in one-to-one correspondence with the second bonding regions R2. In the case of having a plurality of passive device matrices 120, the plurality of passive device matrices 120 may be disposed on the same side or different sides of the main chip module 110 in a direction parallel to the main surface of the hybrid substrate.

In some embodiments, the plurality of chips in the main chip module 110 may be substantially uniformly distributed in the first bonding region R1. In some examples, the plurality of chips in the main chip module 110 may have different shapes or sizes, etc., such that the first bonding region R1 may have an irregular shape. The second bonding region R2 is a free region except the first bonding region R1 in the die bonding region BR, and the passive device matrix 120 is disposed in the second bonding region R2 to fill the free region of the die bonding region BR; for example, the die bonding region BR, which is formed by the second bonding region R2 and the first bonding region R1 together, may have a substantially regular-shaped profile and may, for example, be substantially symmetrical in shape.

For example, in the example shown in fig. 4, the plurality of second bonding regions R2 are respectively located at corners of the first bonding regions R1, near edges of the hybrid substrate, the first chip and the plurality of second chips of the main chip module 110 are bonded to the first bonding regions R1 of the rerouting structure 210, and the plurality of passive device matrices 120 are respectively bonded to the plurality of second bonding regions R2 of the rerouting structure 210. The plurality of passive device matrices 120 are disposed at corners of the main chip module 110, near edges of the hybrid substrate.

In some embodiments, as shown in fig. 4, the first chip 101 may be centrally disposed with respect to the rerouting structure 210 in plan view, and the first chip 101 may be an axisymmetric structure; for example, the symmetry axis of the first chip 101 may coincide with an orthographic projection of a centerline of the rerouting structure 210 on the main surface of the hybrid substrate, which centerline of the rerouting structure 210 may extend in the first direction D1 or in the second direction D2, and may also be the symmetry axis of the rerouting structure 210. In some embodiments, the plurality of second chips have substantially the same shape, size, and may be symmetrically disposed with respect to a centerline of the redistribution structure 210 extending in the first direction or the second direction. For example, the first chip 101 has a first side and a second side opposite to each other in the first direction D1, the second chip 102a and the second chip 102b are provided on the first side of the first chip 101, and the second chip 102c and the second chip 102D are provided on the second side of the first chip 101; the second chip 102a and the second chip 102c may be symmetrically disposed about a symmetry axis of the first chip 101 extending in the second direction D2 or a center line of the rerouting structure 210; similarly, the second chip 102b and the second chip 102D may be symmetrically disposed about a symmetry axis of the first chip 101 extending in the second direction D2 or a center line of the rewiring structure 210. The second chip 102a and the second chip 102b may be symmetrically disposed about a symmetry axis of the first chip extending in the first direction D1 or a center line of the rerouting structure; the second chips 102c and 102D may be symmetrically disposed about a symmetry axis of the first chip extending in the first direction D1 or a center line of the rerouting structure.

The passive device matrix 120 may overlap one or more chips in the main chip module in at least one of the first direction D1 and the second direction D2. Herein, overlapping of a plurality of members in a certain direction means that the orthographic projections of the plurality of members overlap on a reference plane perpendicular to the direction; that is, the orthographic projection of the passive device matrix 120 on a reference plane (e.g., an extension plane of a sidewall of the hybrid substrate) perpendicular to the first direction D1 or the second direction D2 overlaps with the orthographic projection of one or more chips in the main chip module on the reference plane.

For example, the passive device matrix 120 may be disposed on one side of the first chip 101 in the first direction D1 and on one side of the second chip in the second direction D2. In the case where a plurality of passive device matrices 120 are provided in a package structure, shapes, sizes, and the like of the plurality of passive device matrices 120 may be the same as or different from each other. In some examples, the passive device matrix 120 may have substantially the same and shape. And may be sized and arranged substantially symmetrically with respect to each other. For example, in the example shown in fig. 4, two passive device matrices located at the upper left and right corners of the die bonding region or two passive device matrices located at the lower left and right corners of the die bonding region may be symmetrically disposed about a symmetry axis of the first chip extending in the second direction D2 or a center line of the rewiring structure; the two passive device matrices located at the upper left corner and the lower left corner of the die bonding region or the two passive device matrices located at the upper right corner and the lower right corner of the die bonding region may be symmetrically disposed with respect to a center line of the rerouting structure or a symmetry axis of the first chip extending in the first direction D1.

In some embodiments, the passive device matrix 120 and the main chip module 110 may have sidewalls (or sides) that are substantially aligned in a direction parallel to the major surfaces of the hybrid substrate from a plan view. For example, one side of the passive device matrix 120 may be aligned with a side of the first chip 101 extending in the first direction D1; for example, one side of the passive device matrix 120 may be aligned with a side of the second chip extending in the second direction D2.

In the embodiment of the disclosure, the passive device matrix is arranged in the vacant area of the chip bonding area of the hybrid substrate, so that the stress of the packaging structure can be balanced, and the warping of the packaging structure is reduced or avoided.

It should be understood that the shapes, sizes, numbers, arrangements, etc. of the chips of the main chip module 110 and the passive device matrix 120 shown in fig. 4 are merely illustrative, and the disclosure is not limited thereto. The size, number, arrangement and the like of the chips of the main chip module 110 and the passive device matrix 120 can be set and adjusted according to the actual product design and requirements, and the main chip module 110 can balance stress by matching the passive device matrix 120, so that the warping of the packaging structure is reduced.

With continued reference to fig. 3-6, in some embodiments, the passive device matrix 120 is disposed on a hybrid substrate, which may provide corresponding electrical performance to the main chip module in addition to reducing or avoiding warpage of the package structure. For example, the passive device matrix 120 may be or include a capacitive matrix, and the passive device chips 120a therein may each be or include silicon capacitors. The provision of the passive device matrix 120 may be advantageous for improving power performance and reliability of the package structure, in addition to reducing warpage of the package structure. For example, compared with the ceramic capacitor mounted on the substrate shown in fig. 1, the silicon capacitor has a higher resonant frequency, which can effectively reduce high-frequency noise, has a lower parasitic resistance and/or lower parasitic inductance, is more beneficial to reducing the impedance of the power supply network, and can greatly reduce the power supply noise, and has higher stability even at high temperature, so that the power supply performance and reliability of the package structure can be improved. On the other hand, compared with the ceramic capacitor, the silicon capacitor has smaller size (such as width, thickness and the like), and more silicon capacitors can be arranged in unit volume, so that the overall capacitance of the capacitor matrix is increased, and the power supply noise is reduced.

In particular, under ideal conditions, a capacitor may be considered as a pure capacitor having only capacitive properties, but in practice the capacitor may also have resistive and inductive properties coupled to it, i.e. may also have parasitic resistance, referred to as Equivalent series resistance (Equivalent SERIES RESISTANCE, ESR), and/or parasitic inductance, referred to as Equivalent series inductance (Equivalent Series Inductance, ESL). That is, not only the capacitance C but also a resistance component (i.e., ESR) and an inductance component (i.e., ESL) exist in the capacitor, and thus the impedance characteristic curve of the capacitor exhibits a "V" shape, and exhibits a capacitive characteristic before the resonance frequency, and as the frequency increases, the impedance decreases, and the impedance of the resonance frequency depends on the ESR; after passing the resonance frequency, the impedance characteristic becomes inductive, and the impedance rises with increasing frequency. The inductive impedance characteristics depend on the ESL. The smaller the ESR, the lower the impedance of the resonant frequency. The smaller the ESL, the lower the impedance of the inductive area, so the smaller the ESR and ESL are, the more favorable for removing high-frequency noise, and the smaller the ESR and/or ESL of the silicon capacitor is, so that the impedance of a power network can be better improved, and the power noise is further reduced.

For example, taking a silicon capacitor and a ceramic capacitor of the same capacitance value (e.g., 180 nf) as examples, the resonance frequency point of the ceramic capacitor may be located near 20MHz, the resonance frequency point of the silicon capacitor may be located near 100MHz, and the ESL of the silicon capacitor may be about 1/10 of the ceramic capacitor. That is, the silicon capacitor has a good suppression effect on high-frequency noise on the package structure, and its ESL is only 1/10 of that of the ceramic capacitor, thus having a better decoupling (i.e., removing noise on the power pins of the chip) effect.

When a plurality of passive device matrixes are provided, the sizes of the plurality of passive device matrixes and the number of passive device chips contained in the plurality of passive device matrixes can be the same or different; in the case where the plurality of passive device matrices are a plurality of capacitance matrices, capacitance values of the plurality of capacitance matrices may be the same or different. For example, a plurality of capacitance matrices having different capacitance values may be used, so that noise at different frequency points may be reduced.

For example, in the example shown in fig. 4, 4 capacitance matrices may use the same capacitance type; for example, the capacitance value of a single capacitor in each capacitor matrix is 1 μf, and the capacitance value of each 5×8 capacitor matrix is 5×8×1 μf=40 μf; the total capacitance of the 4 capacitance matrices is 40 μf×4=160 μf. In other examples, power filtering may also be performed using combinations of capacitive matrices having different capacitance values, e.g., multiple capacitive matrices each having a capacitance value of 1uf, 500nf, 180nf, 140nf, etc., may be employed, each disposed in a different free area. It should be understood that the foregoing description of the capacitance is merely illustrative, and the disclosure is not limited thereto, and the capacitance of the corresponding capacitance matrix may be set according to the product requirement.

In some embodiments, when the passive device matrix 120 is a capacitive matrix, providing the passive device matrix 120 facilitates improving the warpage of the package structure, improving the power performance of the package structure, reducing the overall size of the packaged device, and improving the reliability of the package structure. For example, in some package structures without the capacitor matrix, the passive device embedded in the hybrid substrate 400 may not be implemented or the process difficulty is too great, so that a capacitor such as a ceramic capacitor needs to be disposed on the hybrid substrate 400 to reduce the power noise, but the Equivalent Series Resistance (ESR) and equivalent series inductance (ESL) of the ceramic capacitor are high, so that the high-frequency noise cannot be improved. In addition, the ceramic capacitor has a relatively large size and a large occupied area, and if the ceramic capacitor is disposed on the side of the hybrid substrate close to the main chip module, the ceramic capacitor needs to occupy a large space, so that the overall size of the package structure may be large. If the ceramic capacitor is arranged on one side of the hybrid substrate far away from the main chip module, the distance between the ceramic capacitor and the main chip is far, and the filtering effect of the ceramic capacitor is limited; moreover, if the capacitor is disposed on the same side of the hybrid substrate as the conductive terminals, it is necessary to sacrifice a region of a portion of the conductive terminals to dispose the capacitor, which may have an adverse effect on a chip having a large power consumption.

In the embodiment of the disclosure, since the capacitive matrix having a plurality of capacitive chips is disposed on the hybrid substrate 400, and more capacitive chips can be disposed in a unit area using the capacitive matrix, that is, the capacitive matrix has an increased capacitance, it is more advantageous to reduce the impedance in the circuit of the package structure, and thus to reduce the power noise. The size, capacitance and the like of the passive device matrix of the embodiment of the disclosure can be set and adjusted according to the product requirements.

Furthermore, since the capacitor matrix is arranged, the capacitors such as ceramic capacitors and the like are not required to be arranged on the mixed substrate or the number of the ceramic capacitors arranged on the mixed substrate can be reduced, so that the additional occupation of the area on the mixed substrate or the area on the mixed substrate occupied by the capacitors can be avoided, and the whole size of the packaging structure can be reduced. For example, in some embodiments, ceramic capacitor 220 may optionally be disposed on a side of hybrid substrate 400 remote from conductive terminal 370. In some embodiments, the ceramic capacitor 220 may be omitted, which may be more advantageous in reducing the overall size of the package structure. Ceramic capacitor 220 is shown in phantom, indicating that the ceramic capacitor may be selectively disposed on the hybrid substrate, and may be omitted in some examples. Also, in the embodiments of the present disclosure, since the capacitor matrix is provided, power supply noise can be effectively reduced, and thus, it may be unnecessary to provide a capacitor on a side of the hybrid substrate 400 remote from the main chip module, thereby eliminating the occupation of the area of the conductive terminals 370, and thus, a sufficient number of conductive connectors may be provided to provide electrical connection of the package structure with external members (e.g., power supply terminals).

Fig. 7 illustrates a plan view of a passive device wafer 10 according to some embodiments of the present disclosure. For example, the passive device matrix 120 in the package structure is cut from the passive device wafer.

Referring to fig. 7, in some embodiments, the passive device wafer 10 is provided with a plurality of die areas 121 and dicing areas 12, one passive device die 120a being provided in each die area 121; the plurality of passive device chips 120a are spaced apart from each other by the dicing regions 12. The plurality of passive device chips 120a may be arranged in an array, for example, may be arranged in an array including a plurality of rows and a plurality of columns along the first direction D1 and the second direction D2. The dicing area 12 is located between adjacent passive device chips 120a to space adjacent passive device chips 120a apart. One or more alignment marks, such as alignment during a manufacturing process for passive device chips, a wafer dicing process, etc., may be provided in the dicing area 12.

For example, a matrix region MR is located in the passive device wafer, the matrix region MR including a plurality of passive device chips 120a and a first dicing region 12a located between the plurality of passive device chips 120 a; the matrix region MR is the region in the wafer where the subsequently formed passive device matrix 120 is located prior to the wafer dicing process. The first cutting region 12a is a portion of the cutting region 12 located in the matrix region MR, and the cutting region 12 further includes a second cutting region 12b located around the matrix region MR.

The passive device wafer 10 is subjected to a dicing process by which the portion of the wafer located in the matrix region MR is diced from the wafer and the passive device matrix 120 is formed, i.e., the passive device matrix located in the matrix region MR is separated from other passive device chips in the wafer by the wafer dicing process. For example, the passive device wafer 10 is subjected to a wafer dicing process along dicing paths that extend at least partially along the second dicing regions 12b to separate the passive device matrix from other passive device chips that are located outside the matrix region MR and form a passive device matrix 120 as shown in fig. 5. In some embodiments, the matrix of passive devices located in the matrix area of the wafer prior to the wafer dicing process may be referred to as an initial matrix of passive devices; that is, the wafer dicing process cuts the initial passive device matrix from the wafer to form the passive device matrix.

For example, fig. 7 schematically illustrates a first dicing path CL1, a second dicing path CL2, a third dicing path CL3, and a fourth dicing path CL4 of the wafer dicing process, each of which extends at least partially along a second dicing area 12b around the matrix area. For example, the first and second dicing paths CL1 and CL2 may extend in the first direction D1, and the third and fourth dicing paths CL3 and CL4 may extend in the second direction D2, the dicing paths intersecting each other and defining the boundaries of the passive device matrix. The dicing path of the wafer dicing process does not pass through the first dicing area 12a between the plurality of passive device chips located within the matrix area. The wafer dicing process may be or include a mechanical sawing (MECHANICAL SAW) process, a laser drilling (LASER DRILLING) process, a laser dicing process, or a combination thereof.

After the wafer dicing process, the passive device matrix 120 located in the matrix region MR is separated from other passive device chips of the wafer located outside the matrix region MR; the plurality of passive device chips 120a located in the matrix region MR remain in the formed passive device matrix 120, i.e., at least part of the dicing remain region 122 shown in fig. 5 and 6 is formed, because the dicing regions between the passive device chips 120a are not subjected to dicing process, and the plurality of passive device chips 120a in the passive device matrix still continue to each other, share the same substrate, and are not independent of each other. In some embodiments, the second dicing regions 12b outside the outer sidewalls of the edge passive device chips of the passive device matrix 120 may be partially removed in the dicing process, while partially remaining in the passive device matrix 120 and as part of the dicing reserved region 122; in other embodiments, the second scribe areas 12b of the edge passive device matrix 120 other than the outer sidewalls of the edge passive device chips may be completely removed in the wafer dicing process and such that the sidewalls of the edge passive devices may be exposed at the sidewalls of the passive device matrix.

In some embodiments, the method of manufacturing the package structure 500 includes the steps of: the one or more chips in the main chip module 110 are bonded to the first bonding region R1 of the rerouting structure 210, the first bonding region R1 may also be referred to as a main chip bonding region. Next, a free area of a free region (i.e., a second bonding region R2) of the chip bonding region BR of the rerouting structure 210 other than the first bonding region R1 is calculated. It should be appreciated that there may be one or more free areas, and when there are multiple free areas, the free areas of the multiple free areas are calculated separately. Each empty region corresponds to a matrix of passive devices.

Setting a matrix area of a required passive device matrix based on the spare area; for example, the matrix area may be less than or approximately equal to the free area. Determining the position of a matrix area in the passive device wafer based on the set matrix area; for example, the number and arrangement modes of the passive device chips in the passive device matrix are calculated according to the matrix area; for example, a passive device matrix includes a plurality of passive device chips arranged in an n×m array, and this step may calculate values of n and m. For example, a matrix form meeting the matrix area can be calculated according to the size of a single passive device chip in the passive device wafer, the size of a cutting area and the like, namely, values of n and m are obtained; the locations of the satisfactory matrix areas are then determined in the wafer. And then, the wafer cutting process is carried out to cut the passive device matrix in the matrix area from the passive device wafer, namely, the passive device matrix which is required to be arranged into an n multiplied by m array is cut from the passive device wafer, and the size of the formed passive device matrix is matched with the size of the spare area.

It will be appreciated that when there are a plurality of free areas, the free areas of the plurality of free areas are calculated separately and one or more subsequent steps may be performed to obtain a matrix of passive devices that match each free area. Multiple passive device matrices for different spare areas may be cut from the same passive device wafer or different passive device wafers, and the size of the multiple passive device matrices, etc. may be the same or different. The capacitance values of the multiple passive device matrices may be the same or different.

After the passive device matrix 120 is diced from the wafer, the passive device matrix 120 is bonded to the free area of the rewiring structure 210, i.e., the second bonding region R2.

Therefore, the package structure of the embodiment of the disclosure adopts the passive device matrix, which can simplify the process, for example, the wafer dicing process and the bonding process between a plurality of passive device chips of the passive device matrix and the hybrid substrate, so that the process efficiency can be improved, the chip failure risk can be reduced, the yield can be improved, and the process cost can be reduced.

The following points need to be described:

(1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are referred to, and other structures may refer to the general design.

(2) Features of the same and different embodiments of the disclosure may be combined with each other without conflict.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A package structure, comprising:

A hybrid substrate including a main body substrate including a core layer, a first buildup layer and a second buildup layer, wherein the first buildup layer and the second buildup layer are disposed on opposite sides of the core layer in a direction perpendicular to a main surface of the hybrid substrate, and a rerouting structure disposed on a side of the first buildup layer remote from the core layer and in contact with and electrically connected to the main body substrate;

A main chip module and at least one passive device matrix electrically connected to each other through the hybrid substrate and arranged side by side on a side of the rewiring structure remote from the main body substrate in a direction parallel to a main surface of the hybrid substrate,

Wherein each of the passive device matrices has a plurality of chip regions and dicing reserved regions, and includes a plurality of passive device chips respectively disposed in the plurality of chip regions, the plurality of passive device chips being disposed side by side in a direction parallel to a main surface of the hybrid substrate and being spaced apart from each other by the dicing reserved regions, wherein the passive device matrix has a substrate continuously extending between the plurality of chip regions and the dicing reserved regions.

2. The package structure of claim 1, wherein the core layer comprises a core dielectric layer and a conductive member, the first buildup layer comprises a first dielectric layer and a first conductive structure, the second buildup layer comprises a second dielectric layer and a second conductive structure, the first conductive structure, the conductive member, and the second conductive structure are electrically connected to each other, the redistribution structure comprises a third dielectric layer and a redistribution layer, and the third dielectric layer is in contact with the first dielectric layer, and the redistribution layer is in contact with and electrically connected to the first conductive structure.

3. The package structure of claim 2, wherein the core dielectric layer has a stiffness that is greater than one or more of the stiffness of the first dielectric layer, the stiffness of the second dielectric layer, and the stiffness of the third dielectric layer.

4. The package structure of claim 2, wherein the chip in the main chip module comprises a chip substrate, and a first stiffness difference between a stiffness of the core dielectric layer and a stiffness of the chip substrate is less than a second stiffness difference between a stiffness of the first dielectric layer, the second dielectric layer, or the third dielectric layer and a stiffness of the chip substrate.

5. The package structure of claim 2, wherein the chip in the main chip module comprises a chip substrate, and a first difference in thermal expansion coefficient between the thermal expansion coefficient of the core dielectric layer and the thermal expansion coefficient of the chip substrate is smaller than a second difference in thermal expansion coefficient between the thermal expansion coefficient of the first dielectric layer, the second dielectric layer, or the third dielectric layer and the thermal expansion coefficient of the chip substrate.

6. The package structure of claim 2, wherein the core dielectric layer comprises an inorganic material.

7. The package structure of claim 2, wherein the core dielectric layer comprises glass.

8. The package structure of claim 2, wherein a line width of the conductive lines of the redistribution layer is smaller than a line width of the conductive lines in the first conductive structure and/or the second conductive structure.

9. The package structure according to claim 1, wherein in the hybrid substrate, a sidewall of the rewiring structure is aligned with a sidewall of the main body substrate in a direction perpendicular to a main surface of the hybrid substrate.

10. The package structure of any one of claims 1-9, wherein the passive device matrix comprises:

the substrate comprises a first substrate part positioned in the plurality of chip areas and a second substrate part positioned in the cutting reserved area; and

A dielectric structure disposed on one side of the substrate, extending continuously between the plurality of chip regions and the dicing reserved region, and including a first dielectric portion in the plurality of chip regions and a second dielectric portion in the dicing reserved region;

Wherein each passive device chip includes one or more passive devices disposed in or on at least one of the first substrate portion and the first dielectric portion.

11. The package structure of claim 10, wherein the cut-and-hold region includes at least the second substrate portion and the second dielectric portion, and wherein an orthographic projection of the one or more passive devices on the hybrid substrate does not overlap with an orthographic projection of the cut-and-hold region on the hybrid substrate.

12. The package structure of claim 10, wherein the dicing reserved area further comprises an alignment mark disposed in or on at least one of the second substrate portion and the second dielectric portion.

13. The package structure of any one of claims 1-9, wherein the passive device matrix is a capacitive matrix and each passive device chip includes one or more capacitors.

14. The package structure of claim 13, wherein each passive device chip comprises a silicon capacitor.

15. The package structure of claim 13, wherein a plurality of capacitances of the plurality of passive device chips are connected in parallel with each other through the hybrid substrate.

16. The package structure according to any one of claims 1-9, further comprising:

And the encapsulation layer is arranged on one side of the rewiring structure of the hybrid substrate, which is far away from the main substrate, and surrounds and encapsulates the main chip module and the passive device matrix, wherein the encapsulation layer covers the side walls of the main chip module and the passive device matrix and fills a gap between the main chip module and the passive device matrix.

17. The package structure of claim 16, wherein the plurality of passive device chips includes an edge passive device chip located at an edge of the passive device matrix, the edge passive device chip having a first chip side and a second chip side opposite or adjacent to each other;

The first chip side of the edge passive device chip faces the main chip module or is close to the edge of the encapsulation layer and is encapsulated by the encapsulation layer, and the second chip side of the edge passive device chip faces other passive device chips in the passive device matrix and is adjacent to the cutting reserved area and separated from the encapsulation layer.

18. The package structure of claim 1, wherein the main chip module includes first and second chips, the first and second chips and a plurality of passive device chips in the passive device matrix being electrically connected to each other through the rerouting structure.

19. The package structure of claim 18, wherein the first chip comprises a logic chip and the second chip comprises a memory chip.

20. The package structure of claim 19, wherein the logic chip comprises a system chip and the memory chip comprises a high bandwidth memory chip.

21. The package structure of claim 1, wherein the passive device matrix and the main chip module have sides aligned in a direction parallel to a main surface of the hybrid substrate in plan view.

22. The package structure of claim 1, wherein the at least one passive device matrix comprises a plurality of passive device matrices, and the plurality of passive device matrices are disposed on the same side or different sides of the main chip module in a direction parallel to a major surface of the hybrid substrate.