CN221178002U - Circuit boards and electronic devices - Google Patents

Abstract

Embodiments of the present application provide a circuit board and an electronic device, and relate to the technical field of circuit boards. The circuit board has a plurality of vias. The plurality of vias include a plurality of pairs of differential signal vias and a plurality of ground hole groups, and the plurality of pairs of differential signal vias are arranged along a first direction and a second direction, and the first direction and the second direction are perpendicular. Each ground hole group includes a plurality of ground holes, and a plurality of ground holes in a ground hole group surround a pair of differential signal vias. In the first direction, the center line of at least one pair of differential signal vias is staggered from the center line of the ground hole group surrounding the pair of differential signal vias; and/or, in the second direction, the center line of at least one pair of differential signal vias is staggered from the center line of the ground hole group surrounding the pair of differential signal vias. Such a configuration can increase the distance between the differential signal via and the trace, and reduce the crosstalk of the signal when it is transmitted on the differential signal via.

Description

Circuit boards and electronic devices

Technical Field

The present application relates to the technical field of circuit boards, and in particular to a circuit board and an electronic device.

Background technique

A circuit board generally includes vias, which are used to transmit signals. In the related art, when a signal is transmitted through a via, crosstalk is large, which affects the transmission reliability of the signal.

Utility Model Content

Embodiments of the present application provide a circuit board and an electronic device for reducing crosstalk when a signal is transmitted on a via.

On the one hand, an embodiment of the present application provides a circuit board. The circuit board has a plurality of vias, and the plurality of vias include a plurality of pairs of differential signal vias and a plurality of ground hole groups. The plurality of pairs of differential signal vias are arranged along a first direction and a second direction, and the first direction and the second direction are perpendicular. Each ground hole group includes a plurality of ground holes, and a plurality of ground holes in a ground hole group surround a pair of differential signal vias. In the first direction, the center line of at least one pair of differential signal vias is offset from the center line of the ground hole group surrounding the pair of differential signal vias; and/or, in the second direction, the center line of at least one pair of differential signal vias is offset from the center line of the ground hole group surrounding the pair of differential signal vias.

In an embodiment of the present application, in a first direction, the center lines of at least one pair of differential signal vias and the center lines of the ground hole groups surrounding the pair of differential signal vias are offset, which can increase the distance between the two in the first direction; and/or, in a second direction, the center lines of at least one pair of differential signal vias and the center lines of the ground hole groups surrounding the pair of differential signal vias are offset, which can increase the distance between the two in the second direction.

That is, by adopting the above-mentioned setting method, the distance between a pair of differential signal vias and the ground hole group surrounding the pair of differential signal vias can be increased, thereby increasing the distance between the trace between the two and the differential signal vias, reducing the mutual interference between the signal transmitted on the trace and the signal transmitted on the differential signal via, greatly reducing the crosstalk of signals (especially high-speed signals) during transmission, improving the transmission reliability of signals, and enabling the circuit board to support higher-speed high-speed signal interconnection.

Furthermore, the above-mentioned configuration method is used to reduce crosstalk, which is easy to implement, so that the circuit board can meet the lower crosstalk requirements in higher-speed scenarios and support higher-speed business needs.

In some possible implementations, the plurality of pairs of differential signal vias include a first pair of differential signal vias and a second pair of differential signal vias. Two differential signal vias in the first pair of differential signal vias are arranged along a first direction, and two differential signal vias in the second pair of differential signal vias are arranged along a second direction. The first pair of differential signal vias and the second pair of differential signal vias are arranged alternately. The plurality of ground hole groups include a first ground hole group and a second ground hole group. The plurality of ground holes in the first ground hole group surround the first pair of differential signal vias, and the plurality of ground holes in the second ground hole group surround the second pair of differential signal vias. In the first direction, the center line of at least one second pair of differential signal vias is staggered with the center line of the second ground hole group surrounding the second pair of differential signal vias; and/or, in the second direction, the center line of at least one first pair of differential signal vias is staggered with the center line of the first ground hole group surrounding the first pair of differential signal vias. In this way, the distance between the second pair of differential signal vias and the ground holes in the second ground hole group can be increased, and the crosstalk of the signal when it is transmitted on the second pair of differential signal vias can be reduced. Furthermore, the distance between the first pair of differential signal via holes and the ground via holes in the first ground via hole group can be increased, thereby reducing crosstalk when signals are transmitted through the first pair of differential signal via holes.

In some possible implementations, in the first direction, when the center line of at least one second pair of differential signal vias is offset from the center line of the second ground hole group surrounding the second pair of differential signal vias: the center lines of multiple second pairs of differential signal vias in the same row along the second direction coincide with each other, the center lines of multiple second ground hole groups in the same row along the second direction coincide with each other, and the center lines of multiple second pairs of differential signal vias in the same row along the second direction and the center lines of multiple second ground hole groups in the same row along the second direction are offset. This arrangement can improve the regularity of the arrangement of the second pair of differential signal vias and the second ground hole group. In addition, in the first direction, the center line of the second pair of differential signal vias and the center line of the second ground hole group surrounding the second pair of differential signal vias can be offset to reduce the crosstalk of the signal when it is transmitted on the second pair of differential signal vias.

In some possible implementations, in the second direction, when the center line of at least one first pair of differential signal vias and the center line of the first ground hole group surrounding the first pair of differential signal vias are offset: the center lines of multiple first pairs of differential signal vias in the same row along the first direction in the second direction coincide; the center lines of multiple first ground hole groups in the same row along the first direction in the second direction coincide; and the center lines of multiple first pairs of differential signal vias in the same row along the first direction in the second direction and the center lines of multiple first ground hole groups in the same row along the first direction in the second direction are offset. Such an arrangement can improve the regularity of the arrangement of the first pair of differential signal vias and the first ground hole group. In addition, in the second direction, the center line of the first pair of differential signal vias and the center line of the first ground hole group surrounding the first pair of differential signal vias can be offset, thereby reducing the crosstalk of the signal when it is transmitted on the first pair of differential signal vias.

In some possible implementations, when in the first direction, the center line of at least one second pair of differential signal vias is offset from the center line of the second ground hole group surrounding the second pair of differential signal vias, and in the second direction, the center line of at least one first pair of differential signal vias is offset from the center line of the first ground hole group surrounding the first pair of differential signal vias: the center lines of multiple second pairs of differential signal vias located in the same row along the second direction in the first direction coincide; the center lines of multiple second ground hole groups located in the same row along the second direction in the first direction coincide; and the center lines of multiple second pairs of differential signal vias located in the same row along the second direction in the first direction and the center lines of multiple second ground hole groups located in the same row along the second direction are offset; the center lines of multiple first pairs of differential signal vias located in the same row along the first direction in the second direction coincide; the center lines of multiple first ground hole groups located in the same row along the first direction in the second direction coincide; and the center lines of multiple first pairs of differential signal vias located in the same row along the first direction in the second direction and the center lines of multiple first ground hole groups located in the same row along the first direction in the second direction are offset. Such an arrangement can improve the regularity of the arrangement of the first pair of differential signal vias, the second pair of differential signal vias, the first ground via group, and the second ground via group, and can reduce the crosstalk of signals when they are transmitted on the first pair of differential signal vias and the second pair of differential signal vias.

In some possible implementations, in the first direction, the distance between the center line of at least one pair of differential signal vias and the center line of the ground hole group surrounding the pair of differential signal vias is in the range of 5μm to 15μm; and/or, in the second direction, the distance between the center line of at least one pair of differential signal vias and the center line of the ground hole group surrounding the pair of differential signal vias is in the range of 5μm to 15μm. Such an arrangement can avoid the distance between the center line of the second pair of differential signal vias and the center line of the second ground hole group surrounding the second pair of differential signal vias being too large (for example, greater than 15μm) or too small (for example, less than 5μm) in the first direction. And it can avoid the distance between the center line of the first pair of differential signal vias and the center line of the first ground hole group surrounding the first pair of differential signal vias being too large (for example, greater than 15μm) or too small (for example, less than 5μm) in the second direction. In this way, the distance between the ground hole and the differential signal via can be increased while ensuring the isolation effect of the ground hole on the differential signal via, thereby increasing the distance between the trace and the differential signal via and reducing crosstalk during transmission on the differential signal via.

In some possible implementations, the ground hole group includes four ground holes. The four ground holes surround a pair of differential signal vias along the first direction and the second direction. In this way, the ground hole group can isolate the pair of differential signal vias from other vias (such as other differential signal vias) along the first direction and the second direction, thereby reducing crosstalk between signals and improving signal transmission reliability.

In some possible implementations, multiple pairs of differential signal vias are used to transmit high-speed differential signals. The transmission rate of the high-speed differential signals is greater than 15 megabits per second. This arrangement can reduce crosstalk when the high-speed differential signals are transmitted on the vias, and improve the transmission reliability of the high-speed differential signals.

In some possible implementations, the circuit board has a first area, a second area, and a third area. The first area and the second area are adjacent, and the first area and the second area surround the third area. Multiple pairs of differential signal vias and multiple ground via groups are located in the first area. The multiple vias also include multiple control signal vias and multiple power signal vias, the multiple control signal vias are located in the second area, and the multiple power signal vias are located in the third area. This arrangement improves the convenience of the power supply supplying power to other components through the power vias.

On the other hand, an embodiment of the present application provides an electronic device. The electronic device includes the circuit board and a functional chip as described above. The functional chip has a ball grid array package BGA, and the ball grid array package BGA is electrically connected to multiple vias of the circuit board.

The electronic device provided by the embodiment of the present application includes the circuit board as described above, and thus has all the above-mentioned beneficial effects, which will not be described in detail here.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of an electronic device provided in some embodiments of the present application.

FIG. 2 is a schematic diagram showing the positional relationship between a circuit board and a ball grid array package BGA provided in some embodiments of the present application.

FIG. 3 is a schematic diagram of the structure of a circuit board provided in some embodiments of the present application.

FIG. 4 is a schematic diagram showing the positional relationship between vias and a ball grid array package BGA provided in other embodiments of the present application.

FIG. 5 is a schematic diagram of the positional relationship between differential signal vias and routings provided in some embodiments of the present application.

FIG. 6 is a schematic diagram of the structure of a circuit board provided in some other embodiments of the present application.

FIG. 7 is a schematic diagram of the structure of a circuit board provided in some other embodiments of the present application.

FIG8 is a schematic diagram of the structure of a circuit board provided in some other embodiments of the present application.

FIG. 9 is a schematic diagram of the structure of a circuit board provided in some other embodiments of the present application.

FIG. 10 is a schematic diagram of the structure of a circuit board provided in some other embodiments of the present application.

FIG. 11 is a schematic diagram of the structure of a circuit board provided in some other embodiments of the present application.

FIG. 12 is a schematic diagram of the structure of a circuit board provided in some other embodiments of the present application.

FIG. 13 is a schematic diagram of the positional relationship between differential signal vias and routings provided in other embodiments of the present application.

FIG. 14 is a diagram showing the positional relationship among the first region, the second region, and the third region provided in some embodiments of the present application.

Detailed ways

The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

Unless the context requires otherwise, throughout the specification and claims, the term "including" and its other forms, such as the third person singular form "including" and the present participle form "including", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

“A and/or B” includes the following three combinations: A only, B only, and a combination of A and B.

As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two equalities is less than or equal to 5% of either one.

FIG. 1 is a schematic diagram of the structure of an electronic device provided in some embodiments of the present application. FIG. 2 is a schematic diagram of the positional relationship between a circuit board and a ball grid array package BGA provided in some embodiments of the present application. FIG. 3 is a schematic diagram of the structure of a circuit board provided in some embodiments of the present application. FIG. 4 is a schematic diagram of the positional relationship between a via and a ball grid array package BGA provided in other embodiments of the present application.

As shown in FIG1 , an embodiment of the present application provides an electronic device 200. For example, the electronic device 200 may be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, etc.; or, the electronic device 200 may also be a personal computer (full name: personal computer, English abbreviation: PC), a server, a workstation, etc. It is understandable that the embodiment of the present application does not further limit the type of the electronic device 200.

In some examples, the electronic device 200 may include a circuit board 100 (see FIG. 2 ) and a functional chip (not shown in the figure). As shown in FIG. 2 and FIG. 3 , the functional chip has a ball grid array package BGA (full name in English: ball grid array) 210, and the circuit board 100 has a plurality of vias 120, and the ball grid array package BGA 210 is electrically connected to the plurality of vias 120 of the circuit board 100.

The circuit board 100 may be a printed circuit board (PCB). The functional chip may have a processing function, a computing function, or a storage function. In some examples, the functional chip may be a central processing unit (CPU), a graphics processing unit (GPU), or a storage function chip. For example, the electronic device 200 may include multiple functional chips, and the types of the multiple functional chips may be the same or different.

As shown in Fig. 2, the ball grid array package BGA210 may include a plurality of metal balls 211. For example, the metal balls 211 may be regular spherical, or the metal balls 211 may be ellipsoidal or approximately spherical. The shapes and sizes of the plurality of metal balls 211 may be the same or different.

In some examples, the number of metal balls 211 and the number of vias 120 may be the same, and the metal balls 211 and the vias 120 may be electrically connected in a one-to-one correspondence, so that the functional chip can be electrically connected to the circuit board 100. In this way, by electrically connecting the circuit board 100 to other components, the electrical connection between the functional chip and other components can be achieved.

The embodiments of the present application do not further limit the structure of the functional chip. The circuit board 100 provided in some embodiments of the present application is exemplified below.

In some examples, the size of the circuit board 100 along the first direction X may be 70 mm (unit: millimeter), and the size along the second direction Y may be 70 mm. The first direction X is perpendicular to the second direction Y. In other examples, the circuit board 100 may also have other sizes.

In some examples, the circuit board 100 includes multiple insulating layers and multiple conductive layers, which are alternately stacked so that the insulating layer can be located between two adjacent conductive layers to play an electrical isolation role.

For example, the material of the conductive layer may include a metal or an alloy, such as at least one of gold, silver or copper. The materials of the multiple conductive layers may be the same or different. The material of the insulating layer may include at least one of phenolic resin, polyimide or epoxy resin. The materials of the multiple insulating layers may be the same or different.

For example, a trace 1121 is provided on the conductive layer (see FIG3 ). The via 120 extends along the stacking direction of the multi-layer insulating layer and the multi-layer conductive layer, and is electrically connected to the trace 1121. It can be understood that the stacking direction of the multi-layer insulating layer and the multi-layer conductive layer intersects with the plane where the first direction X and the second direction Y are located. It can be understood that in the drawings of the specification of the present application, taking FIG3 as an example, only a part of the trace 1121 is shown, and the length, path, etc. of the trace 1121 are not further limited.

It can be understood that the via 120 can play a role in conducting electricity, and a plurality of vias 120 can be arranged at intervals. The routing 1121 is located between any two adjacent vias 120, and the routing 1121 avoids other vias 120 except the via 120 electrically connected to the routing 1121.

For example, the lengths of any two vias 120 extending along the stacking direction of the multi-layer insulating layer and the multi-layer conductive layer may be the same or different. Any two vias 120 may be electrically connected to the same trace 1121, or any two vias 120 may be electrically connected to different traces 1121. The diameters of any two vias 120 may be the same or different.

In some examples, the via 120 may include an opening and a conductive portion, the opening extending along the stacking direction of the multiple insulating layers and the multiple conductive layers, and exposing the trace 1121. The conductive portion is located in the opening, so that the conductive portion can be electrically connected to the trace 1121 exposed by the opening. For example, the conductive portion may be located on the side wall of the opening; or, the conductive portion may also be a cylindrical structure and located in the opening.

For example, the circuit board 100 may include a plurality of pads (not shown in the figure), and the plurality of vias 120 may be electrically connected to the plurality of pads in a one-to-one correspondence. The plurality of metal balls 211 may be electrically connected to the plurality of pads in a one-to-one correspondence, so that the plurality of metal balls 211 may be electrically connected to the plurality of vias 120 in a one-to-one correspondence.

In some examples, the pad is disposed at a position corresponding to the via 120, and the pad can be directly electrically connected to the via 120. In other examples, the pad can also be offset relative to the via 120, and the pad can be electrically connected to the via 120 through a wire.

In some examples, as shown in FIG3 , the plurality of vias 120 of the circuit board 100 may include a plurality of pairs of differential signal vias 1211 and a plurality of ground via groups 122. The plurality of pairs of differential signal vias 1211 are arranged along the first direction X and the second direction Y. Each ground via group 122 includes a plurality of ground vias 1221, and the plurality of ground vias 1221 in one ground via group 122 surround a pair of differential signal vias 1211.

It can be understood that the plurality of pairs of differential signal vias 1211 are used to transmit differential signals. A pair of differential signal vias 1211 includes two differential signal vias 1211, and the two differential signal vias 1211 in a pair of differential signal vias 1211 can be arranged along the first direction X or the second direction Y.

In some examples, multiple pairs of differential signal vias 1211 can be used to transmit high-speed differential signals, wherein the transmission rate of the high-speed differential signals is greater than 15 megabits per second (GigaBit Per Second, Gbps).

In some other examples, at least one pair of differential signal vias 1211 among the plurality of pairs of differential signal vias 1211 may also be used to transmit a low-speed differential signal.

For example, as shown in FIG. 3 , multiple pairs of differential signal vias 1211 can be spaced apart along the first direction X and the second direction Y, so that the multiple pairs of differential signal vias 1211 can be arranged along the first direction X and the second direction Y. The ground hole group 122 may include multiple ground holes 1221, and the ground holes 1221 can be grounded. The number of ground holes 1221 in different ground hole groups 122 can be the same or different. The multiple ground holes 1221 in a ground hole group 122 can surround a pair of differential signal vias 1211 to reduce the crosstalk between two adjacent pairs of differential signal vias 1211 (two pairs of differential signal vias 1211 adjacent along the first direction X, or two pairs of differential signal vias 1211 adjacent along the second direction Y).

In some examples, as shown in FIG. 3 , the ground hole group 122 may include four ground holes 1221 , and the four ground holes 1221 surround a pair of differential signal vias 1211 along the first direction X and the second direction Y.

Such an arrangement enables the ground hole group 122 to isolate a pair of differential signal vias 1211 from other vias 120 (eg, other differential signal vias 1211 ) along the first direction X and the second direction Y, thereby reducing crosstalk between signals and improving signal transmission reliability.

In some examples, the multiple metal balls 211 may include multiple signal metal balls and multiple ground metal balls (see Figure 2), the multiple signal metal balls are electrically connected to the multiple differential signal vias 1211 in a one-to-one correspondence, and the multiple ground metal balls are electrically connected to the multiple ground holes 1221 in a one-to-one correspondence.

In some examples, the metal ball 211 may be staggered from the via 120. For example, as shown in FIG4 , the ground via 1221 may be closer to the pair of differential signal vias 1211 surrounding it relative to the ground metal ball electrically connected thereto, so as to reduce the distance between the ground via 1221 and the pair of differential signal vias 1211 surrounding it, thereby shortening the return path of the signal and reducing the signal loss.

It can be understood that crosstalk (English: Crosstalk) refers to the noise caused by coupling, mutual inductance and mutual capacitance between two components that transmit signals (such as two pairs of differential signal vias 1211, or a pair of differential signal vias 1211 and a trace 1121). For example, when the location where the crosstalk occurs is close to the location of the signal source, it can be called near-end crosstalk, and when the location where the crosstalk occurs is far from the location of the signal source, it can be called far-end crosstalk. For example, the crosstalk between a pair of differential signal vias 1211 and the trace 1121 can be called near-end crosstalk.

As the rate of signals increases, the crosstalk between signals becomes more and more serious. Since the distances between the plurality of vias 120 are relatively close, the crosstalk is relatively serious.

Taking the ground hole group 122 including four ground holes 1221 as an example, in some implementations, as shown in FIG3 , in the first direction X, the center line Q1 of any pair of differential signal vias 1211 coincides with the center line M1 of the ground hole group 122 surrounding the pair of differential signal vias 1211. In addition, in the second direction Y, the center line Q2 of any pair of differential signal vias 1211 coincides with the center line M2 of the ground hole group 122 surrounding the pair of differential signal vias 1211. For example, the above-mentioned setting method can be called a symmetrical via method.

It can be understood that, taking a pair of differential signal vias 1211 as an example, the center line of a pair of differential signal vias 1211 in the first direction X is the center line of the pair of differential signal vias 1211 along the first direction X; the center line of a pair of differential signal vias 1211 in the second direction Y is the center line of the pair of differential signal vias 1211 along the second direction Y.

The inventor of the present application has found that the above arrangement will reduce the distance between a pair of differential signal vias 1211 and the ground vias 1221 in the ground via group 122 surrounding the pair of differential signal vias 1211. As shown in FIG3 , since the wiring 1121 is located between two adjacent vias 120, the above arrangement will reduce the distance between the wiring 1121 and the differential signal vias 1211, resulting in greater crosstalk between signals and affecting the transmission reliability of signals (especially high-speed signals).

FIG. 5 is a schematic diagram of the positional relationship between differential signal vias and routings provided in some embodiments of the present application.

For example, as shown in FIG. 5 , the distance D1 between the trace 1121 and the differential signal via 1211 is 9.6 mil (unit: one thousandth of an inch). At this time, the crosstalk of the signal transmitted on the differential signal via 1211 is 0.467 db, which affects the transmission reliability of the signal.

Fig. 6 is a schematic diagram of the structure of a circuit board provided in some other embodiments of the present application. Fig. 7 is a schematic diagram of the structure of a circuit board provided in some other embodiments of the present application. Fig. 8 is a schematic diagram of the structure of a circuit board provided in some other embodiments of the present application. Fig. 9 is a schematic diagram of the structure of a circuit board provided in some other embodiments of the present application. Fig. 10 is a schematic diagram of the structure of a circuit board provided in some other embodiments of the present application. Fig. 11 is a schematic diagram of the structure of a circuit board provided in some other embodiments of the present application. Fig. 12 is a schematic diagram of the structure of a circuit board provided in some other embodiments of the present application.

Based on this, an embodiment of the present application provides a circuit board 100. The circuit board 100 has a plurality of vias 120, and the plurality of vias 120 include a plurality of pairs of differential signal vias 1211 and a plurality of ground hole groups 122. The plurality of pairs of differential signal vias 121 are arranged along a first direction X and a second direction Y. Each ground hole group 122 includes a plurality of ground holes 1221, and the plurality of ground holes 1221 in a ground hole group 122 surround a pair of differential signal vias 1211.

The above embodiments of the present application have illustrated the circuit board 100, the differential signal via 1211 and the ground via 1221, which will not be described again.

In some examples, as shown in FIG. 6 and FIG. 7 , in the first direction X, a center line Q1 of at least one pair of differential signal vias 1211 and a center line M1 of the ground via group 122 surrounding the pair of differential signal vias 1211 are offset.

In some other examples, as shown in FIGS. 8 to 10 , in the second direction Y, a center line Q2 of at least one pair of differential signal vias 1211 and a center line M2 of the ground hole group 122 surrounding the pair of differential signal vias 1211 are offset.

In some other examples, as shown in FIGS. 11 and 12 , in the first direction X, a center line Q1 of at least one pair of differential signal vias 1211 and a center line M1 of the ground hole group 122 surrounding the pair of differential signal vias 1211 are offset; and in the second direction Y, a center line Q2 of at least one pair of differential signal vias 1211 and a center line M2 of the ground hole group 122 surrounding the pair of differential signal vias 1211 are offset.

It can be understood that the first direction X includes a first sub-direction X1 and a second sub-direction X2, which are opposite to each other. The second direction Y includes a third sub-direction Y1 and a fourth sub-direction Y2, which are opposite to each other.

For example, in the first direction X, when the center line Q1 of at least one pair of differential signal vias 1211 and the center line M1 of the ground hole group 122 surrounding the pair of differential signal vias 1211 are offset, as shown in FIG6 , in the first direction X, the center line Q1 of at least one pair of differential signal vias 1211 can be located on one side of the center line M1 of the ground hole group 122 surrounding the pair of differential signal vias 1211 along the second sub-direction X2, that is, the differential signal via 1211 can be offset relative to the ground hole group 122 along the second sub-direction X2.

At this time, compared with setting the center line Q1 of a pair of differential signal vias 1211 and the center line M1 of the ground hole group 122 surrounding the differential signal via 1211 to coincide with each other, the distance between the differential signal via 1211 and the ground hole 1221 in the first sub-direction X1 can be increased.

For example, in the first direction X, when the center line Q1 of at least one pair of differential signal vias 1211 and the center line M1 of the ground hole group 122 surrounding the pair of differential signal vias 1211 are offset, as shown in FIG. 7 , the center line Q1 of at least one pair of differential signal vias 1211 may be located on one side of the center line M1 of the ground hole group 122 surrounding the pair of differential signal vias 1211 along the first sub-direction X1, that is, the differential signal vias 1211 may be offset relative to the ground hole group 122 along the first sub-direction X1.

At this time, compared with the case where the center line Q1 of a pair of differential signal vias 1211 coincides with the center line M1 of the ground hole group 122 surrounding the pair of differential signal vias 1211 , the distance between the differential signal vias 1211 and the ground holes 1221 in the second sub-direction X2 can be increased.

That is, in the first direction X, the center line Q1 of at least one pair of differential signal vias 1211 and the center line M1 of the ground hole group 122 surrounding the pair of differential signal vias 1211 are staggered, which can increase the distance between the pair of differential signal vias 1211 and the ground hole group 122 surrounding the pair of differential signal vias 1211 in the first sub-direction X1 or the second sub-direction X2, thereby increasing the distance between the wiring 1121 located between the pair of differential signal vias 1211 and the ground hole 122 and the pair of differential signal vias 1211 (see Figure 7), reducing the interference between the signal transmitted on the wiring 1121 and the signal transmitted on the differential signal via 1211, greatly reducing the crosstalk of the signal (especially the high-speed signal), improving the performance of the signal, and enabling the circuit board 100 to support higher-speed high-speed signal interconnection.

It can be understood that the directions (e.g., the first sub-direction X1 or the second sub-direction X2) in which different pairs of differential signal vias 1211 are offset relative to the ground hole group 122 surrounding the pair of differential signal vias 1211 can be the same or different. The distances between the center lines of different pairs of differential signal vias 1211 in the first direction X and the center line M1 of the ground hole group 122 surrounding the pair of differential signal vias 1211 in the first direction X can be the same or different.

For example, in the second direction Y, when the center line Q2 of at least one pair of differential signal vias 1211 and the center line M2 of the ground hole group 122 surrounding the pair of differential signal vias 1211 are offset, as shown in Figures 8 and 9, the center line Q2 of at least one pair of differential signal vias 1211 can be located on one side of the center line M2 of the ground hole group 122 surrounding the pair of differential signal vias 1211 along the fourth sub-direction Y2, that is, the differential signal via 1211 can be offset relative to the ground hole group 122 along the fourth sub-direction Y2.

At this time, compared with the case where the center line Q2 of a pair of differential signal vias 1211 coincides with the center line M2 of the ground hole group 122 surrounding the pair of differential signal vias 1211, the distance between the differential signal via 1211 and the ground hole 1221 in the third sub-direction Y1 can be increased.

For example, in the second direction Y, when the center line Q2 of at least one pair of differential signal vias 1211 and the center line M2 of the ground hole group 122 surrounding the pair of differential signal vias 1211 are offset, as shown in FIG. 10, the center line Q2 of at least one pair of differential signal vias 1211 can be located on one side of the center line M2 of the ground hole group 122 surrounding the pair of differential signal vias 1211 along the third sub-direction Y1, that is, the differential signal via 1211 can be offset relative to the ground hole group 122 along the third sub-direction Y1.

At this time, compared with the case where the center line Q2 of a pair of differential signal vias 1211 coincides with the center line M2 of the ground hole group 122 surrounding the pair of differential signal vias 1211, the distance between the differential signal via 1211 and the ground hole 1221 in the fourth sub-direction Y2 can be increased.

That is, in the second direction Y, the center line Q2 of at least one pair of differential signal vias 1211 and the center line M2 of the ground hole group 122 surrounding the pair of differential signal vias 1211 are staggered, which can increase the distance between the pair of differential signal vias 1211 and the ground hole group 122 surrounding the pair of differential signal vias 1211 in the third sub-direction Y1 or the fourth sub-direction Y2, thereby increasing the distance between the wiring 1121 located between the pair of differential signal vias 1211 and the ground hole 1221 and the pair of differential signal vias 1211 (see Figure 10), reducing the interference between the signal transmitted on the wiring 1121 and the signal transmitted on the differential signal via 1211, greatly reducing the crosstalk of the signal (especially the high-speed signal), improving the performance of the signal, and enabling the circuit board 100 to support higher-speed high-speed signal interconnection.

It can be understood that the directions (e.g., the third sub-direction Y1 or the fourth sub-direction Y2) in which different pairs of differential signal vias 1211 are offset relative to the ground hole group 122 surrounding the pair of differential signal vias 1211 can be the same or different. The distances between the center lines of different pairs of differential signal vias 1211 in the second direction Y and the center line M1 of the ground hole group 122 surrounding the pair of differential signal vias 1211 in the second direction Y can be the same or different.

For example, as shown in FIG. 11 and FIG. 12, when in the first direction X, the center line Q1 of at least one pair of differential signal vias 1211 and the center line M1 of the ground hole group 122 surrounding the pair of differential signal vias 1211 are offset, and in the second direction Y, the center line Q2 of at least one pair of differential signal vias 1211 and the center line M2 of the ground hole group 122 surrounding the pair of differential signal vias 1211 are offset, the distance between the pair of differential signal vias 1211 and the ground hole group 122 surrounding the pair of differential signal vias 1211 in the first direction X (the first sub-direction X1 or the second sub-direction X2) is greater than the distance between the pair of differential signal vias 1211 and the ground hole group 122 surrounding the pair of differential signal vias 1211. The distance in the first direction X2) and the second direction Y (the third sub-direction Y1 or the fourth sub-direction Y2) can be increased, thereby increasing the distance between the trace 1121 located between a pair of differential signal vias 1211 and the ground hole 1221 and the pair of differential signal vias 1211 (see FIG. 12), reducing the interference between the signal transmitted on the trace 1121 and the signal transmitted on the differential signal via 1211, greatly reducing the crosstalk of the signal (especially the high-speed signal), improving the performance of the signal, and enabling the circuit board 100 to support higher-speed high-speed signal interconnection.

In some examples, the arrangement in which the center line Q1 of at least one pair of differential signal vias 1211 and the center line M1 of the ground hole group 122 surrounding the pair of differential signal vias 1211 are staggered in the first direction X; and/or the center line Q2 of at least one pair of differential signal vias 1211 and the center line M2 of the ground hole group 122 surrounding the pair of differential signal vias 1211 are staggered in the second direction Y is referred to as an asymmetric via arrangement.

FIG. 13 is a schematic diagram of the positional relationship between differential signal vias and routings provided in other embodiments of the present application.

For example, as shown in FIG. 13 , by adopting the above configuration, the distance D1 between the trace 1121 and the differential signal via 1211 can be increased to 17.7 mil, and the crosstalk on the differential signal via 1211 can be reduced to 0.289 db, thereby improving the transmission reliability of the signal.

In the embodiments of the present application, in the first direction X, the center line Q1 of at least one pair of differential signal vias 1211 and the center line M1 of the ground hole group 122 surrounding the pair of differential signal vias 1211 are staggered, which can increase the distance between the two in the first direction X; and/or, in the second direction Y, the center line Q2 of at least one pair of differential signal vias 1211 and the center line M2 of the ground hole group 122 surrounding the pair of differential signal vias 1211 are staggered, which can increase the distance between the two in the second direction Y.

That is, by adopting the above-mentioned setting method, the distance between a pair of differential signal vias 1211 and the ground hole group 122 surrounding the pair of differential signal vias 1211 can be increased, thereby increasing the distance between the trace 1121 located therebetween and the differential signal via 1211, reducing the mutual interference between the signal transmitted on the trace 1121 and the signal transmitted on the differential signal via 1211, greatly reducing the crosstalk of signals (especially high-speed signals) during transmission, improving the transmission reliability of signals, and enabling the circuit board 100 to support higher-speed high-speed signal interconnections.

Furthermore, the above-mentioned configuration is adopted to reduce crosstalk, which is easy to implement, so that the circuit board 100 can meet the lower crosstalk requirements in higher rate scenarios and support higher rate business needs.

It can be understood that when multiple pairs of differential signal vias 1211 are used to transmit high-speed differential signals (the transmission rate of high-speed differential signals is greater than 15 Mbit/s), the crosstalk during transmission on the high-speed differential signal vias 1211 can be reduced, thereby improving the transmission reliability of the high-speed differential signals.

In some examples, as shown in FIG6 , the plurality of pairs of differential signal vias 1211 include a first pair of differential signal vias 1211a and a second pair of differential signal vias 1211b. The two differential signal vias 1211 in the first pair of differential signal vias 1211a are arranged along a first direction X, and the two differential signal vias 1211 in the second pair of differential signal vias 1211b are arranged along a second direction Y. The first pair of differential signal vias 1211a and the second pair of differential signal vias 1211b are arranged alternately.

It can be understood that the number of the first pair of differential signal vias 1211 a and the number of the second pair of differential signal vias 1211 b can be the same or different.

For example, the first pair of differential signal vias 1211a and the second pair of differential signal vias 1211b can be staggered along the first direction X and the second direction Y to increase the distance between two adjacent differential signal vias 1211 (adjacent along the first direction X or adjacent along the second direction Y), thereby increasing the distance between the trace 1121 and the differential signal via 1211, reducing crosstalk between signals, and improving signal transmission reliability.

As shown in Fig. 6, the plurality of ground hole groups 122 include a first ground hole group 122a and a second ground hole group 122b. The plurality of ground holes 1221 in the first ground hole group 122a surround a first pair of differential signal vias 1211a, and the plurality of ground holes 1221 in the second ground hole group 122b surround a second pair of differential signal vias 1211b.

In some examples, as shown in FIGS. 6 and 7 , in the first direction X, a center line Q1 of at least one second pair of differential signal vias 1211 b and a center line M1 of a second ground hole group 122 b surrounding the second pair of differential signal vias 1211 b are offset.

In other examples, as shown in FIGS. 8 to 10 , in the second direction Y, a center line Q2 of at least one first pair of differential signal vias 1211 a and a center line M2 of a first ground hole group 122 a surrounding the first pair of differential signal vias 1211 a are offset.

In some other examples, as shown in FIGS. 11 and 12 , in the first direction X, a center line Q1 of at least one second pair of differential signal vias 1211b and a center line M1 of the second ground hole group 122b surrounding the second pair of differential signal vias 1211b are offset; and in the second direction Y, a center line Q2 of at least one first pair of differential signal vias 1211a and a center line M2 of the first ground hole group 122a surrounding the first pair of differential signal vias 1211a are offset.

It can be understood that, as shown in Figure 7, in the first direction X, the center line Q1 of at least one second pair of differential signal vias 1211b and the center line M1 of the second ground hole group 122b surrounding the second pair of differential signal vias 1211b are staggered, which can increase the distance between the second pair of differential signal vias 1211b and the second ground hole group 122b surrounding the second pair of differential signal vias 1211b, thereby increasing the distance between the trace 1121 and the second pair of differential signal vias 1211b located therebetween, reducing the interference between the signal transmitted on the trace 1121 and the signal transmitted on the second pair of differential signal vias 1211b, greatly reducing the crosstalk of the signal (especially the high-speed signal), improving the performance of the signal, and enabling the circuit board 100 to support higher-speed high-speed signal interconnection.

As shown in FIG. 10 , in the second direction Y, a center line Q2 of at least one first pair of differential signal vias 1211a and a center line M2 of a first ground hole group 122a surrounding the first pair of differential signal vias 1211a are staggered, so that the distance between the first pair of differential signal vias 1211a and the first ground hole group 122a surrounding the first pair of differential signal vias 1211a can be increased, thereby increasing the distance between the trace 1121 and the first pair of differential signal vias 1211a located therebetween, reducing interference between signals transmitted on the trace 1121 and signals transmitted on the first pair of differential signal vias 1211a, greatly reducing crosstalk of signals (especially high-speed signals), improving signal performance, and enabling the circuit board 100 to support higher-speed high-speed signal interconnection.

It can be understood that, in the first direction X, when the center line Q1 of at least one second pair of differential signal vias 1211b and the center line M1 of the second ground hole group 122b surrounding the second pair of differential signal vias 1211b are offset, and in the second direction Y, when the center line Q2 of at least one first pair of differential signal vias 1211a and the center line M2 of the first ground hole group 122a surrounding the first pair of differential signal vias 1211a are offset, the distance between the second pair of differential signal vias 1211b and the second ground hole group 122b surrounding the second pair of differential signal vias 1211b in the first direction X can be increased, and the distance between the first pair of differential signal vias 1211a and the first ground hole group 122a surrounding the first pair of differential signal vias 1211a in the second direction Y can be increased, thereby reducing the crosstalk of signals transmitted on the first pair of differential signal vias 1211a and the crosstalk of signals transmitted on the second pair of differential signal vias 1211b.

In some examples, in the first direction X, when the center line Q1 of at least one second pair of differential signal vias 1211b and the center line M1 of the second ground hole group 122b surrounding the second pair of differential signal vias 1211b are offset:

As shown in FIG6 , the center lines Q1 of the multiple second pairs of differential signal vias 1211b located in the same row along the second direction Y in the first direction X coincide with each other, the center lines M1 of the multiple second ground hole groups 122b located in the same row along the second direction Y in the first direction X coincide with each other, and the center lines Q2 of the multiple second pairs of differential signal vias 1211b located in the same row along the second direction Y in the first direction X and the center lines Q2 of the multiple second ground hole groups 122b located in the same row along the second direction Y in the first direction X are staggered.

Such an arrangement can improve the regularity of the arrangement of the second pair of differential signal vias 1211b and the second ground via group 122b. In addition, in the first direction X, the center line Q1 of the second pair of differential signal vias 1211b and the center line M1 of the second ground via group 122b surrounding the second pair of differential signal vias 1211b can be staggered, thereby reducing the crosstalk of the signal when it is transmitted on the second pair of differential signal vias 1211b.

In some examples, in the second direction Y, when the center line Q2 of at least one first pair of differential signal vias 1211a and the center line M2 of the first ground hole group 122a surrounding the first pair of differential signal vias 1211a are offset:

As shown in Figures 8 and 9, the center lines of the multiple first pairs of differential signal vias 1211a located in the same row along the first direction X in the second direction Y coincide; the center lines of the multiple first ground hole groups 122a located in the same row along the first direction X in the second direction Y coincide; and the center lines of the multiple first pairs of differential signal vias 1211a located in the same row along the first direction X in the second direction Y are staggered with the center lines of the multiple first ground hole groups 122a located in the same row along the first direction X in the second direction Y.

Such an arrangement can improve the regularity of the arrangement of the first pair of differential signal vias 1211a and the first ground via group 122a. In addition, in the second direction Y, the center line Q2 of the first pair of differential signal vias 1211a and the center line M2 of the first ground via group 122a surrounding the first pair of differential signal vias 1211a can be staggered, thereby reducing the crosstalk of the signal when it is transmitted on the first pair of differential signal vias 1211a.

In some examples, when in the first direction X, a center line Q1 of at least one second pair of differential signal vias 1211b and a center line M1 of the second ground hole group 122b surrounding the second pair of differential signal vias 1211b are offset, and in the second direction Y, a center line Q2 of at least one first pair of differential signal vias 1211a and a center line M2 of the first ground hole group 122a surrounding the first pair of differential signal vias 1211a are offset:

As shown in FIG. 12 , the center lines Q1 of the plurality of second pairs of differential signal vias 1211b located in the same row along the second direction Y in the first direction X coincide with each other, the center lines M1 of the plurality of second ground hole groups 122b located in the same row along the second direction Y in the first direction X coincide with each other, and the center lines Q2 of the plurality of second pairs of differential signal vias 1211b located in the same row along the second direction Y in the first direction X and the center lines Q2 of the plurality of second ground hole groups 122b located in the same row along the second direction Y in the first direction X are staggered; and the center lines of the plurality of first pairs of differential signal vias 1211a located in the same row along the first direction X in the second direction Y coincide with each other; the center lines of the plurality of first ground hole groups 122a located in the same row along the first direction X in the second direction Y coincide with each other; and the center lines of the plurality of first pairs of differential signal vias 1211a located in the same row along the first direction X in the second direction Y and the center lines of the plurality of first ground hole groups 122a located in the same row along the first direction X in the second direction Y are staggered.

Such a configuration can improve the regularity of the arrangement of the first pair of differential signal vias 1211a, the second pair of differential signal vias 1211b, the first ground via group 122a, and the second ground via group 122b, and can reduce the crosstalk of signals when they are transmitted on the first pair of differential signal vias 1211a and the second pair of differential signal vias 1211b.

In some examples, in the first direction X, the distance between the center line of at least one pair of differential signal vias 1211 and the center line of the ground hole group 122 surrounding the pair of differential signal vias 1211 ranges from 5 μm to 15 μm (unit: micrometer); and/or, in the second direction Y, the distance between the center line of at least one pair of differential signal vias 1211 and the center line of the ground hole group 122 surrounding the pair of differential signal vias 1211 ranges from 5 μm to 15 μm.

Such arrangement can avoid that the distance between the center line of the first pair of differential signal vias 1211a and the center line of the first ground hole group 122a surrounding the first pair of differential signal vias 1211a is too large (for example, greater than 15 μm) in the first direction X, thereby affecting the isolation effect of the ground hole 1221 on the first pair of differential signal vias 1211a. In addition, it can avoid that the distance between the center line of the first pair of differential signal vias 1211a and the center line of the ground hole group 122a surrounding the first pair of differential signal vias 1211a is too small (for example, less than 5 μm) in the first direction X, resulting in the distance between the trace 1121 and the first pair of differential signal vias 1211a being too small.

That is, the distance between the center line Q1 of the first pair of differential signal vias 1211a and the center line M1 of the ground hole group 122 surrounding the first pair of differential signal vias 1211a is set in the range of 5μm to 15μm, which can increase the distance between the routing 1121 and the first pair of differential signal vias 1211a and reduce the crosstalk between signals on the basis of ensuring the isolation effect of the ground hole 1221 for the first pair of differential signal vias 1211a.

For example, in the first direction X, the distance between the center line Q1 of the first pair of differential signal vias 1211a and the center line M1 of the ground hole group 122 surrounding the first pair of differential signal vias 1211a may be 7 μm, 9 μm, 11 μm or 13 μm.

In addition, the above arrangement can also prevent the distance between the center line Q2 of the second pair of differential signal vias 1211b and the center line M2 of the second ground hole group 122b surrounding the second pair of differential signal vias 1211b from being too large (for example, greater than 15 μm) in the second direction Y, thereby affecting the isolation effect of the ground hole 1221 on the differential signal via 1211. In addition, it can prevent the distance between the center line Q2 of the second pair of differential signal vias 1211b and the center line M2 of the second ground hole group 122b surrounding the second pair of differential signal vias 1211b from being too small (for example, less than 5 μm) in the second direction Y, resulting in a too small distance between the trace 1121 and the differential signal via 1211.

That is, the distance between the center line Q2 of the second pair of differential signal vias 1211b and the center line M2 of the second ground hole group 122b surrounding the second pair of differential signal vias 1211b is in the range of 5μm to 15μm, which can increase the distance between the trace 1121 and the differential signal via 1211 and reduce the crosstalk between signals while ensuring the isolation effect of the ground hole 1221 on the differential signal via 1211.

For example, in the second direction Y, the distance between the center line Q2 of the second pair of differential signal vias 1211b and the center line M2 of the second ground hole group 122b surrounding the second pair of differential signal vias 1211b may be 7μm, 9μm, 11μm or 13μm, etc.

It can be understood that, in the first direction X, the distance between the center line Q1 of the first pair of differential signal vias 1211a and the center line M1 of the first ground hole group 122a surrounding the first pair of differential signal vias 1211b can be the same as or different from the distance in the second direction Y between the center line Q2 of the second pair of differential signal vias 1211b and the center line M2 of the second ground hole group 122b surrounding the second pair of differential signal vias 1211b.

FIG. 14 is a diagram showing the positional relationship among the first region, the second region, and the third region provided in some embodiments of the present application.

In some examples, the circuit board 100 has a first area P1, a second area P2, and a third area P3. The first area P1 and the second area P2 are adjacent to each other, and the first area P1 and the second area P2 surround the third area P3.

It can be understood that the shapes and areas of the first region P1, the second region P2 and the third region P3 may be the same or different.

For example, multiple pairs of differential signal vias 1211 and ground via group 122 are located in the first region P1. The multiple vias 120 also include multiple control vias and multiple power vias (the control vias and power vias are not shown in the figure). The multiple control vias are located in the second region P2, and the multiple power vias are located in the third region P3.

It can be understood that the power via is used to electrically connect to the power supply, and the control via is used to electrically connect to the control device. The number of the differential signal via 1211, the ground via 1221, the power via and the control via can be the same or different.

A plurality of pairs of differential signal vias 1211 and ground via groups 122 are arranged in the first area P1, a plurality of control vias are arranged in the second area P2, and a plurality of power vias are arranged in the third area P3, thereby improving the convenience of the power supply supplying power to other components through the power vias.

In summary, the embodiments of the present application have at least the following beneficial effects:

In the embodiments of the present application, in the first direction X, the center line Q1 of at least one pair of differential signal vias 1211 and the center line M1 of the ground hole group 122 surrounding the pair of differential signal vias 1211 are staggered, which can increase the distance between the two in the first direction X; and/or, in the second direction Y, the center line Q2 of at least one pair of differential signal vias 1211 and the center line M2 of the ground hole group 122 surrounding the pair of differential signal vias 1211 are staggered, which can increase the distance between the two in the second direction Y.

That is, by adopting the above-mentioned setting method, the distance between a pair of differential signal vias 1211 and the ground hole group 122 surrounding the pair of differential signal vias 1211 can be increased, thereby increasing the distance between the trace 1121 located therebetween and the differential signal via 1211, reducing the mutual interference between the signal transmitted on the trace 1121 and the signal transmitted on the differential signal via 1211, greatly reducing the crosstalk of signals (especially high-speed signals) during transmission, improving the transmission reliability of signals, and enabling the circuit board 100 to support higher-speed high-speed signal interconnections.

Furthermore, the above-mentioned configuration is adopted to reduce crosstalk, which is easy to implement, so that the circuit board 100 can meet the lower crosstalk requirements in higher rate scenarios and support higher rate business needs.

The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims (10)

1. A circuit board, characterized in that the circuit board has a plurality of vias; the plurality of vias include a plurality of pairs of differential signal vias and a plurality of ground via groups; the plurality of pairs of differential signal vias are arranged along a first direction and a second direction; the first direction is perpendicular to the second direction; each ground via group includes a plurality of ground vias, and the plurality of ground vias in one ground via group surround a pair of differential signal vias; In the first direction, the center line of at least one pair of the differential signal via holes is offset from the center line of the ground hole group surrounding the pair of differential signal via holes; and/or, In the second direction, a center line of at least one pair of the differential signal via holes is offset from a center line of a ground hole group surrounding the pair of differential signal via holes. 2. The circuit board according to claim 1, characterized in that the plurality of pairs of differential signal vias include a first pair of differential signal vias and a second pair of differential signal vias; two differential signal vias in the first pair of differential signal vias are arranged along the first direction, and two differential signal vias in the second pair of differential signal vias are arranged along the second direction; the first pair of differential signal vias and the second pair of differential signal vias are arranged alternately; The plurality of ground hole groups include a first ground hole group and a second ground hole group; the plurality of ground holes in the first ground hole group surround the first pair of differential signal vias; the plurality of ground holes in the second ground hole group surround the second pair of differential signal vias; In the first direction, a center line of at least one of the second pair of differential signal vias is staggered from a center line of a second ground via group surrounding the second pair of differential signal vias; and/or, In the second direction, a center line of at least one of the first pair of differential signal via holes is offset from a center line of a first ground hole group surrounding the first pair of differential signal via holes. 3. The circuit board according to claim 2, characterized in that, in the first direction, when the center line of at least one of the second pair of differential signal via holes is offset from the center line of the second ground hole group surrounding the second pair of differential signal via holes: The center lines of the multiple second pairs of differential signal vias located in the same row along the second direction in the first direction overlap; the center lines of the multiple second ground hole groups located in the same row along the second direction in the first direction overlap; and the center lines of the multiple second pairs of differential signal vias located in the same row along the second direction in the first direction are staggered with the center lines of the multiple second ground hole groups located in the same row along the second direction in the first direction. 4. The circuit board according to claim 2, characterized in that, in the second direction, when the center line of at least one of the first pair of differential signal vias is offset from the center line of the first ground hole group surrounding the first pair of differential signal vias: The center lines of the multiple first pairs of differential signal vias located in the same row along the first direction in the second direction overlap; the center lines of the multiple first ground hole groups located in the same row along the first direction in the second direction overlap; and the center lines of the multiple first pairs of differential signal vias located in the same row along the first direction in the second direction are staggered with the center lines of the multiple first ground hole groups located in the same row along the first direction in the second direction. 5. The circuit board according to claim 2, characterized in that, when in the first direction, the center line of at least one of the second pair of differential signal vias is offset from the center line of the second ground hole group surrounding the second pair of differential signal vias, and in the second direction, the center line of at least one of the first pair of differential signal vias is offset from the center line of the first ground hole group surrounding the first pair of differential signal vias: The center lines of the plurality of second pairs of differential signal vias in the same row along the second direction in the first direction overlap; the center lines of the plurality of second ground hole groups in the same row along the second direction in the first direction overlap; and the center lines of the plurality of second pairs of differential signal vias in the same row along the second direction in the first direction and the center lines of the plurality of second ground hole groups in the same row along the second direction in the first direction are staggered; The center lines of the multiple first pairs of differential signal vias located in the same row along the first direction in the second direction overlap; the center lines of the multiple first ground hole groups located in the same row along the first direction in the second direction overlap; and the center lines of the multiple first pairs of differential signal vias located in the same row along the first direction in the second direction are staggered with the center lines of the multiple first ground hole groups located in the same row along the first direction in the second direction. 6. The circuit board according to any one of claims 1 to 5, characterized in that, in the first direction, the distance between the center line of at least one pair of the differential signal vias and the center line of the ground hole group surrounding the pair of differential signal vias ranges from 5 μm to 15 μm; and/or, In the second direction, a distance between a center line of at least one pair of the differential signal via holes and a center line of a ground hole group surrounding the pair of differential signal via holes ranges from 5 μm to 15 μm. 7 . The circuit board according to claim 1 , wherein the ground hole group comprises four ground holes; the four ground holes surround a pair of differential signal vias along the first direction and the second direction. 8. The circuit board according to any one of claims 1 to 7, characterized in that the multiple pairs of differential signal vias are used to transmit high-speed differential signals; wherein the transmission rate of the high-speed differential signals is greater than 15 Mbit/s. 9. The circuit board according to any one of claims 1 to 8, characterized in that the circuit board has a first area, a second area and a third area; the first area and the second area are adjacent to each other, and the first area and the second area surround the third area; the multiple pairs of differential signal vias and the multiple ground via groups are located in the first area; The plurality of vias further include a plurality of control signal vias and a plurality of power signal vias; the plurality of control signal vias are located in the second area, and the plurality of power signal vias are located in the third area. 10. An electronic device, comprising: The circuit board according to any one of claims 1 to 9; Functional chip; the functional chip has a ball grid array package BGA; the ball grid array package BGA is electrically connected to a plurality of vias of the circuit board.