CN220963316U - Package and electronic device - Google Patents

Abstract

The application discloses a package and electronic equipment. The heat dissipation cover is arranged on the substrate, an accommodating space is formed between the heat dissipation cover and the substrate, the chip is arranged in the accommodating space, and the functional surface of the chip faces the substrate; the heat dissipation layer is arranged in the accommodating space and is positioned between the chip and the heat dissipation cover, wherein the heat dissipation cover is provided with a protrusion towards the first surface of the heat dissipation layer, so that the surface of the heat dissipation cover towards the heat dissipation layer and the surface of the heat dissipation layer towards the heat dissipation cover are in fit arrangement. The packaging body can effectively improve the bonding area of the heat dissipation layer and the heat dissipation cover and improve the heat dissipation performance of the packaging body.

Description

Package and electronic device

Technical Field

The present application relates to the field of chip packaging, and in particular, to a package and an electronic device.

Background

The chip package is a novel packaging technology and is mainly characterized in that the chip is connected with a circuit on a packaging substrate, so that the integrated connection of the chip and the packaging substrate is realized. The chip package can improve the reliability and stability of the circuit, and simultaneously can reduce the size of the package body and improve the integration level of the system. However, there are some problems in chip packaging, among which the heat dissipation problem is the most important, and the inventor of the present application found that the current package cannot meet the heat dissipation requirement of the chip in the market.

Disclosure of utility model

The application provides a packaging body and electronic equipment, which can effectively improve the bonding area of a heat dissipation layer and a heat dissipation cover and improve the heat dissipation performance of a chip.

A first aspect of an embodiment of the present application provides a package, including: the device comprises a substrate, a heat dissipation cover, a chip and a heat dissipation layer; the heat dissipation cover is arranged on the substrate, and a containing space is formed between the heat dissipation cover and the substrate; the chip is arranged in the accommodating space; the heat dissipation layer is arranged in the accommodating space and is positioned between the chip and the heat dissipation cover; the heat dissipation cover is provided with protrusions towards the first surface of the heat dissipation layer, so that the surface of the heat dissipation cover towards the heat dissipation layer and the surface of the heat dissipation layer towards the heat dissipation cover are in fit arrangement.

A second aspect of an embodiment of the present application provides an electronic device, including the package in any one of the above.

The beneficial effects are that: according to the application, the surface of the radiating cover facing to one side of the radiating layer is provided with the protrusions, so that the radiating cover and the radiating layer are mutually matched and attached, and the metal cavity between the radiating cover and the radiating layer caused by high-temperature reflow soldering is reduced, thereby realizing effective heat transfer between the chip and the radiating cover and improving the radiating performance of the packaging body.

Drawings

For a clearer description of the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the description below are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:

FIG. 1 is a schematic view of a package according to an embodiment of the present application;

FIG. 2 is a schematic view of a partial structure of another embodiment of the package of the present application;

FIG. 3 is a schematic view of a partial structure of another embodiment of the package of the present application;

FIG. 4 is a schematic view of a partial structure of another embodiment of the package of the present application

FIG. 5 is a schematic flow chart of an embodiment of a method for manufacturing a package of the present application;

In the figure:

100. a package;

10. a heat radiation cover 11, a protrusion 111, a first surface;

20. The chip 21, a first bump 22, underfill 23, a functional surface 24 and a nonfunctional surface;

30 heat sink layers, 31 metal heat sink fins, 32 heat sink material sublayers, 321 first heat sink material sublayers, 322 second heat sink material sublayers;

40. A substrate 41. A second bump;

50. capacitance, 60 resistance, 70 accommodation space.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

It should be noted that the terms "first," "second," and "second" are used herein for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Referring to fig. 1, in an embodiment of the application, a package 100 includes a heat spreader lid 10, a chip 20, a heat spreader layer 30, and a substrate 40.

The heat dissipation cover 10 is disposed on the substrate 40, and forms a receiving space 70 between the heat dissipation cover and the substrate 40. Specifically, the material of the heat dissipating cover 10 includes one of silver, copper, aluminum, and iron, and serves to rapidly conduct heat generated from the chip 20. The substrate 40 plays a supporting role in the package body 100, and its kind includes one of a BGA package substrate, a CSP package substrate, an FC package substrate, and an MCM package substrate. While various circuits (not shown) are formed on the substrate 40 for signal transmission with the chip 20. The heat dissipating cover 10 may be fixedly connected to the substrate 40 by any one of welding, bonding, clamping, and the like.

The chip 20 is disposed in the accommodating space 70, specifically, the chip 20 is provided with a functional surface 23 and a non-functional surface 24 disposed opposite to each other, and a bonding pad (not shown) is disposed on the functional surface 23 for realizing communication between the chip 20 and the outside.

In the present embodiment, the functional surface 23 of the chip 20 faces the substrate 40.

In this embodiment, the package 100 further includes a first bump 21, where the first bump 21 is located between the chip 20 and the substrate 40, and electrically connects the chip 20 and the substrate 40. Specifically, the first bump 21 electrically connects the pad on the chip 20 with the circuit on the substrate 40, so that the chip 20 and the substrate 40 can perform signal transmission. The material of the first bump 21 is not limited as long as it is conductive, and for example, the material thereof includes at least one of tin, silver, copper, and the like.

The heat dissipation layer 30 is disposed in the accommodating space 70 and located between the chip 20 and the heat dissipation cover 10. The first surface 111 of the heat dissipation cover 10 is provided with a protrusion 11, so that a surface of the heat dissipation cover 10 facing the heat dissipation layer 30 is adhered to a surface of the heat dissipation layer 30 facing the heat dissipation cover 10, and specifically, heat generated by the chip 20 is sequentially transferred to the outside through the heat dissipation layer 30 and the heat dissipation cover 10.

In the prior art, the package body 100 is larger and thinner, and the product is easy to warp after being subjected to a high temperature process before the heat dissipation cover 10 is attached, so that the heat dissipation cover 10 cannot be perfectly attached to the heat dissipation layer 30 when the heat dissipation cover 10 is attached, and a gap exists between the heat dissipation cover 10 and the heat dissipation layer 30, thereby affecting the heat dissipation performance of the package body 100. However, in the present embodiment, the protrusion 11 is disposed on the first surface 111 of the heat dissipation cover 10, and the protrusion 11 is matched with the warpage pattern of the heat dissipation layer 30 before the heat dissipation cover 10 is attached, so that the heat dissipation cover 10 and the heat dissipation layer 30 can be perfectly attached, the attaching area of the heat dissipation cover 10 and the heat dissipation layer 30 is increased, and the heat dissipation effect is further improved.

It should be noted that the specific shape and structure of the protrusion 11 may be any shape, and the embodiment of the present application is not limited thereto, and for example, in different scenarios, the shape of the protrusion 11 is shown in fig. 2, 3 and 4, respectively.

Among them, the substrate 40 plays a supporting role in the package body 100, and its kind includes one of a BGA package substrate, a CSP package substrate, an FC package substrate, and an MCM package substrate.

Referring to fig. 2, 3 and 4, in one embodiment, the heat dissipating cover 10 can be integrally formed with the protrusions 11, which can improve the overall strength of the structure.

In another embodiment, the heat dissipating cover 10 and the protrusion 11 are assembled after being manufactured separately, which may improve flexible assembly of the structure.

In an embodiment, the materials of the heat dissipation cap 10 and the protrusion 11 can be the same, so that the kinds of materials used in the manufacturing process can be reduced, the manufacturing cost can be reduced, and the manufacturing efficiency can be improved.

In another embodiment, the materials of the heat dissipating cover 10 and the protrusion 11 may be different, so that the materials with higher heat dissipating performance may be selected to be combined to the greatest extent, and the heat dissipating capability is improved.

With continued reference to fig. 1, in one embodiment, the heat sink layer 30 includes a metal heat sink 31 and at least one sub-layer 32 of heat sink material.

Specifically, the material of the metal heat sink 31 includes at least one of indium metal sheet, alloy material of indium and other metals with good heat conduction properties; the material of the heat sink material sub-layer 32 comprises at least one of titanium, nickel, silver, gold, iron, copper.

The number of the metal fins 31 may be one or more, and when the number of the metal fins 31 is more than one, the materials of the metal fins 31 may be identical or not identical.

The number of the heat dissipation material sub-layers 32 may be one or more, and when the number of the heat dissipation material sub-layers 32 is more than one, the materials of the heat dissipation material sub-layers 32 may be identical or not identical.

The heat dissipation layer 30 includes the metal heat dissipation plate 31 and the heat dissipation material sub-layer 32, so that the heat dissipation performance of the heat dissipation layer 30 can be ensured.

With continued reference to fig. 1, the at least one heat dissipating material sub-layer 32 includes a first heat dissipating material sub-layer 321 and a second heat dissipating material sub-layer 322, where the first heat dissipating material sub-layer 321, the metal heat sink 31 and the second heat dissipating material sub-layer 322 are sequentially stacked in a direction away from the substrate 40.

Specifically, the number of the heat dissipating material sub-layers 32 is more than two, and one of the heat dissipating material sub-layers 32 is defined as a first heat dissipating material sub-layer 321, and the other heat dissipating material sub-layer 32 is defined as a second heat dissipating material sub-layer 322. At this time, the metal heat sink 31 is located between the first heat sink material sub-layer 321 and the second heat sink material sub-layer 322, the heat sink layer 30 presents a sandwich structure, and the surface area of the metal heat sink 31 is at least not smaller than the surface area of the chip 20, that is, the orthographic projection of the metal heat sink 31 on the chip 20 covers the chip 20. While the first heat sink material sub-layer 321 is closer to the chip 20 than the second heat sink material sub-layer 322.

In the present application, the structure of the heat dissipation layer 30 is not particularly limited, and for example, in other embodiments, the first heat dissipation material sub-layer 321, the second heat dissipation material sub-layer 322, and the metal heat dissipation sheet 31 are sequentially stacked.

The first heat dissipation material sub-layer 321 may be formed on the chip 20 by a chemical process or an electroplating process, and the second heat dissipation material sub-layer 322 may be formed on the surface of the bump 11 by a chemical process or an electroplating process.

With continued reference to fig. 1, the package 100 further includes an underfill 22 disposed between the substrate 40 and the chip 20, surrounding the first bump 21, and having the underfill 22 on at least a portion of the sidewalls of the chip 20.

Specifically, the material of the underfill 22 may include at least one of poly-perfluoroisopropenyl and epoxy resin, and may be specifically set according to actual requirements.

In the reflow soldering process, because of the mismatch of the thermo-mechanical stress caused by the different material characteristics of the substrate 40 and the chip 20, the stress generated in the area of the first bump 21 is larger, and the cracking is easy to occur, the underfill 22 greatly relieves the stress in the area of the first bump 21, so that the pulling force between the substrate 40 and the chip 20 tends to be balanced, and the underfill 22 also plays a role in sealing, and can play roles in waterproof, dampproof, dustproof and anticorrosion.

In one embodiment, the underfill 22 must be non-compatible (i.e. poorly wettable) with the metal fins 31, and the contact angle between the surface of the underfill and the molten metal fins 31 is greater than 90 ° during the reflow process, so that the molten metal fins 31 cannot penetrate the surface of the underfill 22, and the voids of the metal fins 31 can be reduced to some extent.

With continued reference to fig. 1, the package 100 further includes a capacitor 50 and a resistor 60, where the capacitor 50 and the resistor 60 are disposed in the accommodating space 70 and are both disposed on the substrate 40 and electrically connected to the substrate 40; the capacitor 50 has the functions of smoothing the power supply voltage and stabilizing the current, and has a filtering function on the electric signal; resistor 60 allows the current to be properly adjusted in the circuit by controlling the magnitude of the current.

The number of the capacitors 50 may be one, or may be multiple, or may not be multiple at all, and when the number of the capacitors 50 is multiple, the type of the capacitors 50 and the position of the capacitors 50 in the accommodating space 70 are arbitrary, which is determined according to actual production needs, and the embodiment of the present application is not limited.

The number of the resistors 60 may be one, or may be plural, or may be none at all, and when the number of the resistors 60 is plural, the type of the resistor 60 and the position of the resistor 60 in the accommodating space 70 are arbitrary, which is determined according to actual production needs, and the embodiment of the present application is not limited.

Note that the capacitor 50 and the resistor 60 may or may not be present at the same time, and the present application is not limited thereto.

With continued reference to fig. 1, the package 100 further includes a second bump 41, where the second bump 41 is disposed on a side of the substrate 40 facing away from the chip 20, and the second bump 41 is electrically connected to the substrate 40.

Specifically, the second bump 41 is electrically connected to the substrate 40, and functions to: the package 100 can be reliably connected to the printed circuit board by the second bump 41 and mechanically support the package 100.

The material of the second bump 41 may include at least one of tin, silver, and copper. And the material of the second bump 41 may be the same as or different from that of the first bump 21, which is not limited herein.

In summary, the package 100 of the present application has good heat dissipation performance, and under the effect of the bump 11, the heat dissipation cover 10 and the heat dissipation layer 30 can be tightly attached, so as to solve the problem of large cavity caused by reflow soldering.

The following describes the preparation process of the package body 100, and in conjunction with fig. 5, the process includes:

S11: and (5) preparing a substrate.

S12: and (5) capacitor and resistor mounting.

Specifically, the capacitor 50 or the resistor 60 is mounted on the substrate 40 and electrically connected to the substrate 40.

S13: and (5) chip mounting.

Specifically, the chip 20 is mounted on the substrate 40 and electrically connected to the substrate 40.

S14: and (5) reflow soldering.

Specifically, the chip 20, the capacitor 50 and the resistor 60 are bonded to the substrate 40 by a high-temperature reflow process, and are fixed to the substrate 40.

S15: and (5) underfill.

Specifically, the underfill is dispensed between the chip 20 and the substrate 40 by a dispensing process and by capillary action, so as to fill the gap between the chip 20 and the substrate 40. Wherein an underfill 22 may also be formed on at least a portion of the sidewalls of the chip 20.

S16: and (5) attaching a heat dissipation layer.

Specifically, the heat dissipation layer 30 is attached to the chip 20.

S17: and the heat dissipation cover with the bulges is attached.

Specifically, the heat dissipation cover 10 including the protrusions 11 is attached to the substrate 40, wherein the portions including the protrusions 11 are in contact with the heat dissipation layer 30.

S18: and (5) reflow soldering.

Specifically, a high-temperature reflow process is used to fix the heat sink cap 10 on the substrate 40 on the one hand, and to fill the gaps between the protrusions 11 of the heat sink cap 10 and the heat sink layer 30 with the metal heat sink fin 31 in a molten state on the other hand.

In summary, the manufacturing method of the package 100 of the embodiment is simple to operate, convenient to process, low in cost, and capable of flexibly adjusting and controlling the shape and structure of the bump according to actual needs.

In addition, the present application also protects an electronic device, which includes the package 100 in any of the above embodiments, and the specific structure thereof may be referred to the above, and will not be described herein.

The electronic device may be any device such as a mobile phone, a computer, a television, etc., which is not limited herein.

The foregoing description is only illustrative of the present application and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present application.

Claims (10)

1. A package, the package comprising:

A substrate;

The heat dissipation cover is arranged on the substrate and forms an accommodating space with the substrate;

The chip is arranged in the accommodating space;

The heat dissipation layer is arranged in the accommodating space and is positioned between the chip and the heat dissipation cover;

The heat dissipation cover is provided with protrusions towards the first surface of the heat dissipation layer, so that the surface of the heat dissipation cover towards the heat dissipation layer and the surface of the heat dissipation layer towards the heat dissipation cover are in fit arrangement.

2. The package of claim 1, wherein the protrusion is integrally formed with the heat sink cap.

3. The package of claim 1, wherein the material of the bump is the same as the material of the heat sink cap.

4. The package of claim 1, wherein the heat sink layer comprises at least one sub-layer of heat sink material and a heat sink metal sheet.

5. The package of claim 4, wherein the at least one layer of heat sink material comprises a first layer of heat sink material and a second layer of heat sink material, the first layer of heat sink material, the heat sink metal sheet, and the second layer of heat sink material being stacked in sequence in a direction away from the substrate.

6. The package of claim 1, further comprising:

And the underfill is arranged between the chip and the substrate and on at least part of the side walls of the chip.

7. The package of claim 1, wherein the functional surface of the chip faces the substrate, the package further comprising:

The first bump is positioned between the chip and the substrate and electrically connects the chip and the substrate.

8. The package of claim 1, wherein the package further comprises:

The capacitor is arranged on the substrate and is positioned in the accommodating space; and/or the number of the groups of groups,

The resistor is arranged on the substrate and is positioned in the accommodating space.

9. The package of claim 1, further comprising:

The second bump is arranged on one side of the substrate, which is away from the chip, and is electrically connected with the substrate.

10. An electronic device comprising the package of any one of claims 1 to 9.