CN220139543U

CN220139543U - Digital receiving sampling system without intermediate frequency coaxial cable

Info

Publication number: CN220139543U
Application number: CN202321613702.8U
Authority: CN
Inventors: 伍汉云; 潘亮; 蒋建文
Original assignee: Chengdu Tiger Microelectronics Research Institute Co ltd
Current assignee: Chengdu Tiger Microelectronics Research Institute Co ltd
Priority date: 2023-06-25
Filing date: 2023-06-25
Publication date: 2023-12-05
Anticipated expiration: 2033-06-25

Abstract

The utility model discloses a digital receiving sampling system without an intermediate frequency coaxial cable, which comprises a variable frequency sampling module, a backboard and a digital receiving module; the variable frequency sampling module comprises a local oscillation unit and a plurality of variable frequency sampling channels; the variable frequency sampling channel comprises a radio frequency input interface, a variable frequency module and an ADC sampling module, wherein the radio frequency input port is used for receiving radio frequency signals, the radio frequency input port is connected with the signal input end of the variable frequency module, the output end of the variable frequency module is connected with the ADC sampling module, and the output end of the ADC sampling module is connected with the digital receiving module through a back plate; the local oscillation unit comprises a local oscillation source and a power divider, wherein the output end of the local oscillation source is connected with the power divider, and the output end of the power divider is respectively connected with the local oscillation input end of the frequency conversion module in each frequency conversion sampling channel. According to the utility model, the ADC sampling module and the frequency conversion module are integrated in the same channel, and the connection between the ADC sampling module and the FPGA is realized through the back plate, so that an intermediate frequency coaxial cable and an optical fiber are not needed, and the wiring complexity is effectively reduced.

Description

Digital receiving sampling system without intermediate frequency coaxial cable

Technical Field

The utility model relates to digital receiving sampling, in particular to a digital receiving sampling system without an intermediate frequency coaxial cable.

Background

In a conventional digital receiver sampling system, radio frequency signals are subjected to analog down-conversion to output intermediate frequency signals, all the intermediate frequency signals enter a sampling module through a coaxial cable to be sampled, and then sampled data are transmitted to a signal processing module through an optical fiber to be subjected to primary processing, and then are packaged and output.

The digital sampling system has a large number of modules and comprises a plurality of frequency conversion modules, a plurality of sampling modules, a local oscillator distribution module, a sampling clock distribution module, a signal processing module and a huge backboard.

Because of the multiple kinds of modules and complex connection relationship, a plurality of coaxial cables and optical cables exist on the back plate, and the layout is messy and complex. Whether SMA is used, the threaded fastening is required, or a mixed connector such as VPX or LRM is used for blind mating, the coaxial cables face reliability or maintainability difficulties, are troublesome to assemble and disassemble, and have high cost.

Disclosure of Invention

The utility model aims to overcome the defects of the prior art, provides a digital receiving sampling system without an intermediate frequency coaxial cable, integrates an ADC sampling module and a frequency conversion module in the same channel, realizes connection of the ADC sampling module and an FPGA through a backboard, does not need the intermediate frequency coaxial cable and an optical fiber, and effectively reduces wiring complexity.

The aim of the utility model is realized by the following technical scheme: a digital receiving sampling system without an intermediate frequency coaxial cable comprises a variable frequency sampling module, a backboard and a digital receiving module;

the variable frequency sampling module comprises a local oscillation unit and a plurality of variable frequency sampling channels;

each frequency conversion sampling channel comprises a radio frequency input interface, a frequency conversion module and an ADC sampling module, wherein the radio frequency input port is used for receiving radio frequency signals, the radio frequency input port is connected with the signal input end of the frequency conversion module, the output end of the frequency conversion module is connected with the ADC sampling module, and the output end of the ADC sampling module is connected with the digital receiving module through a backboard;

the local oscillation unit comprises a local oscillation source and a power divider, wherein the output end of the local oscillation source is connected with the power divider, and the output end of the power divider is respectively connected with the local oscillation input end of a frequency conversion module in each frequency conversion sampling channel;

the digital receiving module comprises an FPGA and a signal output interface, the FPGA is respectively connected with the ADC sampling module in each variable-frequency sampling channel through a back plate, and the FPGA is also connected with the signal output port.

The digital receiving module further comprises a clock input port and a clock distribution network, wherein the clock input port is used for accessing an external reference clock, the input end of the clock distribution network of the clock input port is connected, and the clock distribution network is respectively connected with the FPGA and the ADC sampling module of each frequency conversion sampling channel. The digital receiving module further comprises a DDR3 array connected with the FPGA.

The backboard comprises a plurality of groups of printing lines, each group of printing lines corresponds to a variable frequency sampling channel, and each group of printing lines comprises LVDS printing lines and clock synchronization printing lines; one end of the LVDS printed line is connected with the output end of the ADC sampling module in the corresponding variable frequency sampling channel, and the other end of the LVDS printed line is connected with the FPGA and is used for realizing signal transmission from the ADC sampling module to the FPGA; one end of the clock synchronization printed line is connected with the clock distribution network, the other end of the clock synchronization printed line is connected with the ADC sampling module in the corresponding variable frequency sampling channel, and the clock synchronization printed line synchronously transmits the reference clock to the ADC sampling module to realize clock synchronization.

The beneficial effects of the utility model are as follows: according to the utility model, the ADC sampling module and the frequency conversion module are integrated in the same channel, and the connection between the ADC sampling module and the FPGA is realized through the back plate, so that an intermediate frequency coaxial cable and an optical fiber are not needed, and the wiring complexity is effectively reduced; meanwhile, clock signals of the digital receiving modules can be transmitted to the ADC sampling modules and the FPGA through the backboard printed wiring, and clock synchronization among the ADC sampling modules and the FPGA is achieved, and clock signal transmission is carried out through the backboard, so that the complexity of the system is further simplified.

Drawings

FIG. 1 is a schematic diagram of the present utility model;

FIG. 2 is a schematic diagram of a variable frequency sampling channel;

fig. 3 is a schematic diagram of a digital receiving module.

Detailed Description

The technical solution of the present utility model will be described in further detail with reference to the accompanying drawings, but the scope of the present utility model is not limited to the following description.

As shown in fig. 1, a digital receiving sampling system without an intermediate frequency coaxial cable comprises a variable frequency sampling module, a backboard and a digital receiving module;

each frequency conversion sampling channel comprises a radio frequency input port, a frequency conversion module and an ADC sampling module, wherein the radio frequency input port is used for receiving radio frequency signals, the radio frequency input port is connected with the signal input end of the frequency conversion module, the output end of the frequency conversion module is connected with the ADC sampling module, and the output end of the ADC sampling module is connected with the digital receiving module through a backboard;

In an embodiment of the present utility model, the frequency conversion module is a down conversion module. Because the ADC sampling module and the frequency conversion module are integrated in the same channel, the interconnection relation of the intermediate frequency cable between the frequency conversion module and the ADC sampling module is changed into the inside of the channel, and the ADC sampling module and the frequency conversion module can be connected in a butt-buckling mode through an interface, and the connecting wire of the ADC sampling module and the frequency conversion module can be directly buried in the board card to realize connection, so that the intermediate frequency coaxial cable between the board cards is omitted.

In an embodiment of the present utility model, the digital receiving module further includes a clock input port and a clock distribution network, the clock input port is used for accessing an external reference clock, the input end of the clock distribution network of the clock input port is connected, and the clock distribution network is respectively connected with the FPGA and the ADC sampling module of each variable frequency sampling channel. The digital receiving module further comprises a DDR3 array connected with the FPGA. In an embodiment of the present utility model, the output interface may be an all-in-one optical module; a conventional signal output interface may also be employed.

The backboard comprises a plurality of groups of printed lines, and each group of printed lines corresponds to one variable-frequency sampling channel. Each group of printing lines comprises LVDS printing lines and clock synchronization printing lines; one end of the LVDS printed line is connected with the output end of the ADC sampling module in the corresponding variable frequency sampling channel, and the other end of the LVDS printed line is connected with the FPGA and is used for realizing signal transmission from the ADC sampling module to the FPGA; one end of the clock synchronization printed line is connected with the clock distribution network, the other end of the clock synchronization printed line is connected with the ADC sampling module in the corresponding variable frequency sampling channel, and the clock synchronization printed line synchronously transmits a reference clock to the ADC sampling module to realize clock synchronization; as shown in fig. 2-3, clock synchronization between the ADC sampling modules and the FPGA is achieved through the backplane printed circuit, and clock synchronization between the ADC sampling modules is further simplified (clock signals are provided by clock input ports of the digital receiving modules, and clock synchronization can also be completed between the ADC sampling modules).

It is to be noted that various corresponding changes and modifications can be made by those skilled in the art without departing from the spirit and the essence of the present utility model, and these corresponding changes and modifications should fall within the scope of the appended claims.

Claims

1. A digital receiving sampling system without an intermediate frequency coaxial cable is characterized in that: the device comprises a variable frequency sampling module, a backboard and a digital receiving module;

2. A digital receive sampling system without intermediate frequency coaxial cable according to claim 1, wherein: the frequency conversion module is a down-conversion module.

3. A digital receive sampling system without intermediate frequency coaxial cable according to claim 1, wherein: the digital receiving module further comprises a clock input port and a clock distribution network, wherein the clock input port is used for accessing an external reference clock, the input end of the clock distribution network of the clock input port is connected, and the clock distribution network is respectively connected with the FPGA and the ADC sampling module of each frequency conversion sampling channel.

4. A digital receive sampling system without intermediate frequency coaxial cable according to claim 3, wherein: the digital receiving module further comprises a DDR3 array connected with the FPGA.

5. A digital receive sampling system without intermediate frequency coaxial cable according to claim 3, wherein: the backboard comprises a plurality of groups of printed lines, and each group of printed lines corresponds to one variable-frequency sampling channel.

6. The digital reception sampling system without intermediate frequency coaxial cable according to claim 4, wherein: each group of printing lines comprises LVDS printing lines and clock synchronization printing lines;

one end of the LVDS printed line is connected with the output end of the ADC sampling module in the corresponding variable frequency sampling channel, and the other end of the LVDS printed line is connected with the FPGA and is used for realizing signal transmission from the ADC sampling module to the FPGA;

one end of the clock synchronization printed line is connected with the clock distribution network, the other end of the clock synchronization printed line is connected with the ADC sampling module in the corresponding variable frequency sampling channel, and the clock synchronization printed line synchronously transmits the reference clock to the ADC sampling module to realize clock synchronization.