CN220121820U - Semiconductor packaging device - Google Patents

Abstract

The utility model provides a semiconductor packaging device, comprising: a first mold seal material and a second mold seal material; a first rewiring layer disposed between the first mold seal material and the second mold seal material; the first chip is buried in the first mold sealing material and is electrically connected with the first rewiring layer through a bonding wire. The semiconductor packaging device forms an ePo (embedded stacked package) structure, is an integral structure, has better rigidity and is beneficial to inhibiting warping. In addition, CTE matching can be performed during manufacturing by choice of materials, helping to reduce warpage. In addition, the ePO structure can realize better thinning effect. In addition, the utility model is connected by the bonding wire, and the IO (input output) density is higher.

Description

Semiconductor packaging device

Technical field

The present application relates to the field of semiconductor packaging technology, and specifically to a semiconductor packaging device.

Background technique

The PoP (Package on Package, embedded stacked package) structure is a stack of multiple Packages (packages). Each Package has one or more chips (Die) placed on the substrate (SBT). They are connected through solder balls and integrated into high-density electronic component packages.

Referring to FIG. 1 , a current PoP structure semiconductor packaging device is shown, including a second packaging structure 12 and a first packaging structure 11 stacked thereon. The first packaging structure 11 and the second packaging structure 12 pass through solder balls. 13 realizes electrical connection and physical connection, and the gap between the first packaging structure 11 and the second packaging structure 12 can also be filled with an underfill 14 covering the solder ball 13 . In addition, the first packaging structure 11 and the second packaging structure 12 usually also include a solder resist layer (not shown in the figure) provided on the outer surface.

Each package in the PoP structure comes from different manufacturers. Under normal circumstances, each manufacturer will not particularly consider whether the CTE (coefficient of thermal expansion, coefficient of thermal expansion) of each material in the PoP matches. If the material CTE is not considered in the previous stage, the assembly plant will encounter problems such as warpage caused by CTE mismatch and its derived welding when stacking packages, such as the first package structure 11 and the second package structure 11. Due to the warping of the packaging structure 12, the distances between the solder ball contacts are different, causing the first packaging structure 11 to be unable to be well soldered to the second packaging structure 12.

Utility model content

This application proposes a semiconductor packaging device to solve the technical problem that the PoP structure is prone to warping after stacking due to the inability to consider the CTE of each package in the front-end process.

To achieve the above objectives, this application provides the following technical solution: a semiconductor packaging device, including: a first molding material and a second molding material; a first rewiring layer disposed between the first molding material and the Between the second molding materials; the first chip is embedded in the first molding material and is electrically connected to the first rewiring layer through a first bonding wire.

In some optional implementations, the first chip is connected to the first redistribution layer through a first adhesive layer, and the back side of the first chip faces the first redistribution layer.

In some optional implementations, the semiconductor packaging device further includes a second chip stacked on the first chip, and the second chip is embedded in the first molding material.

In some optional implementations, the second chip is electrically connected to the first chip through a second bonding wire.

In some optional implementations, the semiconductor packaging device further includes: a third chip, embedded in the second molding material, connected to the first rewiring layer through a second adhesive layer, and The back side of the third chip faces the first redistribution layer.

In some optional implementations, the semiconductor packaging device further includes: a fourth chip, embedded in the second molding material, connected to the first redistribution layer through the second adhesive layer ; The back side of the fourth chip faces the first redistribution layer, the fourth chip and the third chip are arranged side by side, and the thickness of the fourth chip and the third chip are different.

In some optional implementations, the semiconductor packaging device further includes: a second redistribution layer disposed on the other side of the second molding material relative to the first redistribution layer.

In some optional implementations, the semiconductor packaging device further includes: a thermal conductive layer disposed on the other side of the first molding material relative to the first rewiring layer.

In some optional implementations, the semiconductor packaging device further includes: the hardness of the first molding material is greater than the hardness of the second molding material.

In some optional implementations, the semiconductor packaging device further includes: the size of the filler in the first molding material is larger than the size of the filler in the second molding material.

In some optional implementations, the semiconductor packaging device further includes: an active surface of the first chip faces the first redistribution layer and is spaced apart from the first redistribution layer.

In some optional implementations, the semiconductor packaging device further includes: the active surface of the third chip faces the first redistribution layer and is spaced apart from the first redistribution layer.

In order to solve the technical problem that the PoP structure is prone to warping after stacking due to the inability to consider the CTE of each package in the front-end process, this application proposes a semiconductor packaging device. In this application, a first rewiring layer is provided on the surface of a certain package (i.e., the second molding material), and then another package (i.e., the first molding material) is stacked on the first rewiring layer. The chip can be embedded inside the second molding material to form an ePoP (embedded Package on Package) structure.

Compared with the PoP structure, the ePoP structure of this application no longer has solder ball bonding parts, but is an integrated overall structure with better rigidity, which helps to suppress warpage. Moreover, even if warpage occurs, due to the first layer The structural strength of the wiring layer is much higher than that of the solder ball bonding part, and there will be no cracking problem.

In addition, the ePoP structure of this application is an integrated overall structure and does not involve packaging from different manufacturers. Therefore, the CTE can be matched through the selection of materials during the manufacturing process, reducing the difference in material properties, thereby helping to reduce Warping, and helps solve other problems such as welding that arise from CTE mismatch.

In addition, the PoP structure contains solder balls (thickness is about 80 μm), and each package includes a substrate (thickness is about 200 μm-300 μm), which is relatively thick and difficult to thin. However, the ePoP structure of this application uses a rewiring layer.

(Thickness about 50μm) The substrate and solder balls are eliminated, and the thickness is much smaller, which can achieve better thinning effect.

In addition, the solder balls are used to connect the packages of the PoP structure, which may lead to poor welding or failure to weld due to warping. However, in the ePoP structure of this application, the first molding material and the second molding material pass through the first rewiring layer. connection, and the first chip embedded in the first molding material is connected to the first rewiring layer through bonding wires. In this way, welding problems can be avoided, such as void problems, and the electrical performance is better, and IO (input and output) density is higher.

In addition, the ePoP structure of this application reduces materials such as underfill and solder mask. By reducing the types of materials, it helps to reduce CTE mismatch and thereby suppress warpage. It also helps to reduce material and process costs.

In addition, the ePoP structure of the present application is an integrated structure, which is light, thin and short. It can realize more functions in one package, and has higher process efficiency and higher production capacity.

Description of the drawings

Other features, objects and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments with reference to the following drawings:

Figure 1 is a schematic structural diagram of a longitudinal cross-section of a current semiconductor packaging device;

Figure 2 is a schematic longitudinal cross-sectional structural diagram of a semiconductor packaging device 2a according to an embodiment of the present application;

Figure 3A is a partial enlarged view of Figure 2;

Figure 3B is another partial enlarged view of Figure 2;

Figure 4 is a schematic longitudinal cross-sectional structural diagram of a semiconductor packaging device 4a according to an embodiment of the present application;

Figure 5 is a schematic longitudinal cross-sectional structural diagram of a semiconductor packaging device 5a according to an embodiment of the present application;

Figure 6 is a schematic longitudinal cross-sectional structural diagram of a semiconductor packaging device 6a according to an embodiment of the present application;

Figure 7 is a schematic longitudinal cross-sectional structural diagram of a semiconductor packaging device 7a according to an embodiment of the present application;

8A-8J are schematic diagrams of manufacturing steps of a semiconductor packaging device according to one embodiment of the present application.

Explanation of reference signs/symbols:

11-First packaging structure; 12-Second packaging structure; 13-Solder ball; 14-Underfill material; 21-First molding material; 22-Second molding material; 23-First rewiring layer; 231 - Circuit pattern; 232-dielectric layer; 233-connection pad; 24-second rewiring layer; 25-adhesive layer; 251-first adhesive layer; 252-second adhesive layer; 253-third adhesive layer; 26 -bonding wire; 261-first bonding wire; 262-second bonding wire; 27-conductive pillar; 28-bump; 29-solder ball; 30-filler; 31-first chip; 32-second chip; 33 -The third chip; 34-the fourth chip; 35-thermal conductive layer; 40-carrier board.

Detailed ways

Specific implementations of the present application will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by the present application and the technical effects produced through the content recorded in this specification. It can be understood that the specific embodiments described here are only used to explain the relevant inventions and creations, but not to limit the inventions and creations. In addition, for convenience of description, only parts related to the invention are shown in the drawings.

It should be readily understood that the meanings of "on", "on" and "on" in this application should be construed in the broadest manner such that "on" Not only means "directly on something," but also "on something" including the presence of intermediate parts or layers in between.

In addition, for convenience of description, spatially relative terms such as “below”, “below”, “lower”, “above”, “upper”, etc. may be used herein. The relationship of one element or component to another element or component as illustrated in the drawings. In addition to the orientation depicted in the figures, spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "layer" as used herein refers to a portion of material that includes a region of thickness. A layer may extend throughout the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. Furthermore, a layer may be a region of a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. The layers may extend horizontally, vertically and/or along tapered surfaces. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers on, above and/or below it. A layer can include multiple layers. For example, the semiconductor layers may include one or more doped or undoped semiconductor layers and may be of the same or different materials.

The term "substrate" as used herein refers to a material onto which subsequent layers of material are added. The substrate itself can be patterned. The material added to the top of the substrate can be patterned or can remain unpatterned. Additionally, the substrate may include a variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of non-conductive material, such as glass, plastic, or sapphire wafers. As a further alternative, the substrate may have a semiconductor device or circuit formed therein.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the specification are only used to coordinate with the content recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the implementation of the present application. Restrictive conditions, so it has no technical substantive significance. Any structural modifications, changes in proportions, or adjustments in size shall still fall within the scope of this application without affecting the effectiveness and purpose of this application. The technical content disclosed must be within the scope that can be covered. At the same time, terms such as "above", "first", "second" and "a" cited in this specification are only for convenience of description and are not used to limit the scope of the application. Changes or adjustments to the relative relationship, provided there is no substantial change in the technical content, shall also be deemed to be within the implementable scope of this application.

It should also be noted that the longitudinal section corresponding to the embodiment of the present application may be a section corresponding to the direction of the front view, the transverse section may be a section corresponding to the direction of the right view, and the horizontal section may be a section corresponding to the direction of the top view.

In addition, the embodiments and features in the embodiments of the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and embodiments.

Referring to FIG. 2, FIG. 2 is a schematic longitudinal cross-sectional structural diagram of a semiconductor packaging device 2a according to an embodiment of the present application. As shown in Figure 2, the semiconductor packaging device 2a according to the embodiment of the present application includes:

first molding material 21;

The second molding material 22 is located below the first molding material 21;

The first rewiring layer 23 is disposed between the first molding material 21 and the second molding material 22; specifically, the first rewiring layer 23 can be disposed on the second molding material 22, and the first molding material 21 may be disposed on the first rewiring layer 23;

The first chip 31 is embedded in the first molding material 21 and is electrically connected to the first redistribution layer 23 through the bonding wires 26 (specifically, the first bonding wires 261 ).

In some optional implementations, the semiconductor packaging device 2 a further includes: a third chip 33 embedded in the second molding material 22 .

Here, the first molding material 21 and the first chip 31 embedded therein may constitute the first packaging structure 11 , and the second molding material 22 and the third chip 33 embedded therein may constitute the second packaging structure 12 . Electrical connection is achieved through the first rewiring layer 23 in the middle.

In some optional embodiments, the first molding material 21 and the second molding material 22 can use the same or similar molding materials, so that the CTE (coefficient of thermal expansion) of the two is substantially equal, thereby reducing the CTE mismatch suppresses warpage.

In some optional implementations, the first chip 31 can be connected to the first rewiring layer 23 through an adhesive layer 25 (specifically, the first adhesive layer 251 ), and the back side of the first chip 31 faces the first rewiring layer. In layer 23 , the active surface of the first chip 31 is away from the first redistribution layer 23 and is electrically connected to the first redistribution layer 23 through the bonding wire 26 .

In some optional implementations, the third chip 33 can be connected to the first rewiring layer 23 through an adhesive layer 25 (specifically, the second adhesive layer 252), and the back side of the third chip 33 faces the first rewiring layer. Layer 23 , the active surface of the third chip 33 is away from the first rewiring layer 23 . Here, the first chip 31 and the third chip 33 are respectively located on the upper and lower sides of the first rewiring layer 23 .

In some optional implementations, the semiconductor packaging device 2 a further includes: a fourth chip 34 embedded in the second molding material 22 , and the fourth chip 34 may be arranged side by side with the third chip 33 . Similar to the third chip 33, the fourth chip 34 can also be connected to the first redistribution layer 23 through an adhesive layer 25 (ie, the second adhesive layer 252), with the back facing the first redistribution layer 23, and the active surface away from the first redistribution layer 23. A rewiring layer 23. Here, the thicknesses of the fourth chip 34 and the third chip 33 may be the same or different.

In some optional implementations, the semiconductor packaging device 2 a further includes: a second redistribution layer 24 , which is disposed on the other side of the second molding material 22 relative to the first redistribution layer 23 .

In some optional implementations, the active surfaces of the third chip 33 and the fourth chip 34 face the second redistribution layer 24 and may be electrically connected to the second redistribution layer 24 through the bumps 28 .

In some optional implementations, the semiconductor packaging device 2a further includes: a conductive pillar 27 that penetrates the second molding material 22 and has both ends electrically connected to the first redistribution layer 23 and the second redistribution layer 24 respectively. That is, the first redistribution layer 23 and the second redistribution layer 24 may be electrically connected through the conductive pillars 27 . Here, the conductive pillar 27 includes but is not limited to a copper pillar (Cu pillar).

In some optional implementations, the semiconductor packaging device 2a further includes: a solder ball 29, which is electrically connected to the other side of the second rewiring layer 24 relative to the second molding material 22. The solder ball 29 is configured to connect an external device, such as a PCB (Printed Circuit Board). There may be multiple solder balls 29 distributed in an array to form a ball array.

In some optional implementations, the first chip 31 embedded in the first molding material 21 may be a memory die; the third chip 33 and the fourth chip 34 embedded in the second molding material 22 , which may be a logic die, such as an application processor (Application Processor) chip.

Referring to FIG. 3A , FIG. 3A is a partial enlarged view of FIG. 2 . As shown in FIG. 3A , the first rewiring layer 23 may include at least one layer of circuit patterns 231 and a dielectric layer 232 , and may also include connection pads 233 , and the connection pads 233 may be configured to connect the bonding wires 26 . Here, the first rewiring layer 23 does not need to be exposed for a long time in the manufacturing process, and therefore, its surface does not need to be covered with a solder resist layer (eg, green paint).

Referring to FIG. 3B , FIG. 3B is another partial enlarged view of FIG. 2 . As shown in FIG. 3B , the second molding material 22 may include a filler 30 . It is easy to understand that the first molding material 21 may also include filler 30 . In some optional embodiments, the size of the filler 30 in the first molding material 21 is larger than the size of the filler 30 in the second molding material 22 , so that the hardness of the first molding material 21 can be greater than that of the second molding material. The hardness of material 22. Of course, in other embodiments, other methods can also be used to make the hardness of the first molding material 21 greater than the hardness of the second molding material 22 . Since the first molding material 21 is disposed above the second molding material 22 , and generally the thickness of the first molding material 21 is thicker than that of the second molding material 22 , by increasing the hardness of the first molding material 21 It is larger than the second molding material 22 and can help suppress warpage.

Continuing to refer to FIG. 3B , it can be seen that some of the fillers 30 close to the second redistribution layer 24 may be partially shaved off due to grinding to have a grinding surface, and the grinding surface contacts the second redistribution layer 24 , so that the second molding The bonding performance between the material 22 and the second redistribution layer 24 can be better.

In order to facilitate the understanding and implementation of this application, the materials and dimensions of some components in the semiconductor packaging device 2a according to the embodiment of this application are further introduced below:

In some optional implementations, the first molding material 21 and the second molding material 22 may be formed of various molding materials (Molding Compound). For example, the molding material may include epoxy resin (Epoxy resin), filler (Filler), catalyst (Catalyst), pigment (Pigment), release agent (Release Agent), flame retardant (FlameRetardant), coupling agent (Coupling Agent), hardener (Hardener), low stress absorber (Low StressAbsorber), adhesion promoter (Adhesion Promoter), ion trapping agent (Ion Trapping Agent), etc. For example, the molding material may be EMC (Epoxy molding compound, epoxy resin molding compound or epoxy molding compound).

In some optional embodiments, the adhesive layer 25 may be a liquid or thin film organic substance (organic polymer material), such as: non-conductive glue (NCP, Non-Conductive Paste), non-conductive film (NCF, Non-Conductive Film) ), Anisotropic Conductive Paste (ACP), Anisotropic Conductive Film (ACF), Polyimide (PI), Epoxy Resin (Resin), PP (PrePreg, prepreg material or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-upFilm), glue, etc.

In some optional implementations, the dielectric layer 232 in the first redistribution layer 23 and the dielectric layer in the second redistribution layer 24 include, but are not limited to, polyimide (PI).

In some optional embodiments, the bonding wire 26 is also called a bonding wire, a bonding wire or a bonding wire, and its materials include but are not limited to gold, silver, copper, aluminum, palladium, platinum, nickel and their alloys, etc. , used in the wire bonding process to use heat, pressure, and ultrasonic energy to tightly weld the bonding pads (connection pads). It is usually used to achieve electrical connections between chips and other components.

In some optional embodiments, the bump 28 is an electrical connector, and its material includes but is not limited to solder, or Cu (copper), Au (gold), Ag (silver), Al (aluminum), Pd (palladium), Pt (platinum) and Ni (nickel) and their alloys. For example, the bumps 28 may be gold bumps (usually rectangular, gold) or solder bumps (solder bumps, usually round, copper plus tin).

In some optional embodiments, the solder ball (ball) 29 is a spherical electrical connector, and its material includes but is not limited to solder (solder), and optionally, its surface can be provided with ACP/ACF (differential materials). Anisotropic conductive paste/adhesive).

In some optional implementations, the thickness of the first redistribution layer 23 and the second redistribution layer 24 may be below 100 μm, for example, about 50 μm. The thickness of both the first molding material 21 and the second molding material 22 can be about several hundred microns (μm), for example, it can be between 300 μm and 500 μm, or it can be less than 300 μm or more than 500 μm, for example, The thickness of the first molding material 21 is greater than the thickness of the second molding material 22 .

As mentioned above, the embodiment of the present application provides a semiconductor packaging device 2a. In this application, a first rewiring layer 23 is provided on the surface of a certain package (for example, the second molding material 22), and then another package (for example, the first molding material 21) is stacked on the first rewiring layer 23, and A chip (eg, the first chip 31 ) may be embedded inside the first molding material 21 and the second molding material 22 , thereby forming an ePoP (embedded Package on Package) structure.

Next, the advantages of the semiconductor packaging device 2a according to the embodiment of the present application will be further described.

Compared with the PoP structure, the ePoP structure of this application no longer has solder ball bonding parts, but is an integrated overall structure with better rigidity, which helps to suppress warpage. Moreover, even if warpage occurs, due to the first layer The structural strength of the wiring layer 23 is much higher than that of the solder ball bonding part, and the problem of cracking will not occur.

In addition, the ePoP structure of this application is an integrated overall structure and does not involve packages from different manufacturers. Therefore, CTE can be matched through the selection of materials during the manufacturing process, reducing material property differences, thereby helping to reduce warpage. curve, and help solve other problems such as welding that arise from CTE mismatch.

In addition, the PoP structure contains solder balls with a thickness of about 80 μm, and each package includes a substrate with a thickness of about 200 μm-300 μm. The thickness is relatively large and difficult to thin. However, the ePoP structure of the present application utilizes the first rewiring layer 23 (thickness of 100 μm). below, for example, about 50 μm), the substrate and solder balls are eliminated, the thickness is much smaller, and a better thinning effect can be achieved.

In addition, the various packages of the PoP structure are connected by solder balls, which may lead to poor welding or failure to weld due to warping. However, in the ePoP structure of the present application, the first molding material 21 and the second molding material 22 pass through the first layer. The wiring layer 23 is connected, and the first chip 31 embedded in the first molding material 21 is connected to the first rewiring layer 23 through the bonding wire 26. In this way, welding problems, such as void problems, can be avoided. And the electrical performance is better, and the IO (input and output) density is higher.

In addition, the ePoP structure of this application reduces materials such as underfill and solder mask. By reducing the types of materials, it helps to reduce CTE mismatch and thereby suppress warpage. It also helps to reduce material and process costs.

In addition, the ePoP structure of the present application is an integrated structure, which is light, thin and short. It can realize more functions in one package, and has higher process efficiency and higher production capacity.

In addition, the semiconductor packaging device of the present application can adopt a wafer level or panel level process. For example, after the molding process (forming the first molding material 21 and the second molding material 22), the warpage can be controlled to 1mm. Below, the warpage can be controlled below 200μm after the reflow process.

In further embodiments, the first molding material 21 and the second molding material 22 can be made of the same or close molding materials, and their CTEs are substantially equal, thereby improving the CTE matching degree and suppressing warpage.

In a further embodiment, a second redistribution layer 24 may also be provided on the other side of the second molding material 22 relative to the first redistribution layer 23 . Here, the first rewiring layer 23 and the second rewiring layer 24 can be designed to oppose each other to further suppress warpage.

In a further embodiment, the first redistribution layer 23 and the second redistribution layer 24 can be connected through conductive pillars 27, which can improve IO density and connection reliability compared to the existing PoP structure that is connected through solder balls.

In a further embodiment, the chips (including the first chip 31, the third chip 33, and the fourth chip 34) and the redistribution layer (including the first redistribution layer 23) can be connected through the adhesive layer 25. It can improve the firmness of the connection and avoid chip deflection.

Referring to FIG. 4, FIG. 4 is a schematic longitudinal cross-sectional structural diagram of a semiconductor packaging device 4a according to an embodiment of the present application. The semiconductor packaging device 4a shown in FIG. 4 is similar to the semiconductor packaging device 2a shown in FIG. 2, except that:

The semiconductor packaging device 4 a further includes a second chip 32 stacked on the first chip 31 , and the second chip 32 is embedded in the first molding material 21 .

Here, the second chip 32 may also be a memory chip.

In some optional implementations, the second chip 32 can be connected to the first chip 31 through an adhesive layer 25 (specifically, a third adhesive layer 253), and the back side of the second chip 32 faces the first chip 31. The active surface is away from the first chip 31 .

In some optional implementations, the second chip 32 is electrically connected to the first chip 31 through the bonding wire 26 (specifically, the second bonding wire 262). Optionally, the first chip 31 and the second chip 32 partially overlap in the top view direction, and part of the active surface of the first chip 31 is not covered by the second chip 32. The bonding wire 26 can be used to electrically connect the active surface of the second chip 32. Connected to the active surface of the first chip 31 .

In some further embodiments, other second chips 32 may be further stacked on the second chip 32 stacked on the first chip 31. That is, there may be multiple second chips 32 and may be stacked in multiple layers. The second chip 32 on the top layer is connected downward through bonding wires 26 in sequence.

Here, the chips (including the first chip 31 and the second chip 32) embedded in the first molding material 21 can be stacked, and the stacked chips can be connected through bonding wires 26, which helps to reduce the thickness and can Avoid processing TMV (through molding via, plastic sealing through hole), thereby saving material and time costs in the process.

Referring to Figure 5, Figure 5 is a schematic longitudinal cross-sectional structural diagram of a semiconductor packaging device 5a according to an embodiment of the present application. The semiconductor packaging device 5a shown in Figure 5 is similar to the semiconductor packaging device 4a shown in Figure 4, except that:

In the semiconductor packaging device 5a, the active surface of the first chip 31 faces the first redistribution layer 23 and is spaced apart from the first redistribution layer 23.

Here, the active surface of the first chip 31 may be electrically connected to the first redistribution layer 23 through the bonding wire 26 . Optionally, the bonding wire 26 electrically connected between the first chip 31 and the first redistribution layer 23 may be arranged vertically, that is, perpendicular to the upper surface of the first redistribution layer 23 .

Referring to Figure 6, Figure 6 is a schematic longitudinal cross-sectional structural diagram of a semiconductor packaging device 6a according to an embodiment of the present application. The semiconductor packaging device 6a shown in FIG. 6 is similar to the semiconductor packaging device 2a shown in FIG. 2, except that:

In the semiconductor packaging device 6a, the active surface of the third chip 33 faces the first redistribution layer 23 and is spaced apart from the first redistribution layer 23.

Here, the third chip 33 can be electrically connected to the first rewiring layer 23 through the bumps 28 .

Here, the back side of the third chip 33 may be connected to the second rewiring layer 24 through the adhesive layer 25 .

In further embodiments, the semiconductor packaging device 6a may further include a fourth chip 34 arranged side by side with the third chip 33. The fourth chip 34 may also actively face the first rewiring layer 23 and be connected to the first rewiring layer through the bumps 28. The wiring layer 23 is electrically connected, and the back side is connected to the second rewiring layer 24 through the adhesive layer 25. The thickness of the fourth chip 34 and the third chip 33 may be the same or different.

Referring to Figure 7, Figure 7 is a schematic longitudinal cross-sectional structural diagram of a semiconductor packaging device 7a according to an embodiment of the present application. The semiconductor packaging device 7a shown in Figure 7 is similar to the semiconductor packaging device 2a shown in Figure 2, except that:

The semiconductor packaging device 7a further includes a thermal conductive layer 35 disposed on the other side of the first molding material 21 relative to the first rewiring layer 23.

In some optional implementations, the thermal conductive layer 35 may be a metal layer formed by physical vapor deposition (PVD), electroplating, lamination, sputtering, tin spraying, or other processes.

In some optional embodiments, the thermally conductive layer 35 may be thermally conductively connected to the chips (including the first chip 31 and/or the second chip 32 ) embedded in the first molding material 21 through some thermally conductive structures/materials.

Here, by providing the thermal conductive layer 35, the heat dissipation performance of the semiconductor package device 7a can be increased.

Referring to FIGS. 8A-8J , FIGS. 8A-8J are schematic diagrams of manufacturing steps of a semiconductor packaging device according to an embodiment of the present application. As shown in Figures 8A-8J, the manufacturing steps of the semiconductor packaging device according to the embodiment of the present application may include:

As shown in FIG. 8A , a first redistribution layer 23 is formed on a carrier board 40 . Here, the carrier plate 40 includes but is not limited to a glass carrier plate, and the glass carrier plate has good surface flatness. Here, the step of forming the first rewiring layer 23 may include: forming a dielectric layer through a coating or lamination process, and forming a metal circuit pattern on the dielectric layer through an additive or subtractive method. The additive method first uses photoresist to transfer patterns through photolithography, development and other steps, and then forms metal circuit patterns through electroplating. The subtractive method first forms a metal layer, then uses photoresist to perform pattern transfer through photolithography, development and other steps, and then etches to form a metal circuit pattern.

As shown in FIG. 8B , the first chip 31 is bonded to the first redistribution layer 23 through an adhesive layer 25 , and the active surface of the first chip 31 (away from the first redistribution layer) is electrically connected to the bonding wire 26 . The first rewiring layer 23. The first chip 31 may be a memory chip, for example.

As shown in FIG. 8C , a molding process is performed to form a first molding material 21 covering the first chip 31 and the bonding wire 26 on the first rewiring layer 23 . The carrier board 40 is then removed.

As shown in FIG. 8D , the structure after the carrier board 40 is removed is shown.

As shown in FIG. 8E , at least one conductive pillar 27 is formed on the other side of the first redistribution layer 23 by implantation or electroplating processes, and the third chip 33 and the fourth chip with the active side facing upward are 34 is bonded to the first redistribution layer 23 through the adhesive layer 25 . The third chip 33 and the fourth chip 34 are lower than the conductive pillars 27 , and bumps 28 may be provided on the upward active surfaces of the third chip 33 and the fourth chip 34 .

As shown in FIG. 8F , a molding process is performed to form a second molding material 22 covering the third chip 33 , the fourth chip 34 and the conductive pillar 27 on the first redistribution layer 23 .

As shown in FIG. 8G , the upper surface of the second molding material 22 is ground so that the conductive pillars 27 and the bumps 28 are exposed from the surface of the second molding material 22 .

As shown in FIG. 8H , a second rewiring layer 24 is formed on the upper surface of the second molding material 22 . Here, the step of forming the second redistribution layer 24 may include: forming a dielectric layer through a coating or lamination process, and forming a metal pattern on the dielectric layer through an additive or subtractive method. Here, the second redistribution layer 24 is electrically connected to the first redistribution layer 23 through the conductive pillars 27 , and is electrically connected to the third chip 33 and the fourth chip 34 through the bumps 28 .

As shown in FIG. 8I , the surface of the first molding material 21 is ground and made thin.

As shown in FIG. 8J , solder balls 29 are placed on the second rewiring layer 24 through a ball planting process, and surface treatment is performed on the second rewiring layer 24 and the solder balls 29 . Here, solder balls 29 are configured to connect external devices. And, through the singulation process, independent semiconductor packaging devices are obtained by cutting.

Above, the manufacturing process of the semiconductor packaging device according to the embodiment of the present application has been described.

It is worth noting that in the above process steps, the orientation of the active surfaces of the first to fourth chips 31 to 34 can be changed when they are placed.

While the application has been described and illustrated with reference to specific embodiments of the application, these descriptions and illustrations do not limit the application. It will be apparent to those skilled in the art that various changes may be made and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the application as defined by the appended claims. Illustrations may not necessarily be drawn to scale. Differences may exist between the technical representations in this application and actual implementations due to manufacturing process variables and the like. There may be other embodiments of the application not specifically illustrated. The instructions and drawings should be regarded as illustrative and not restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the object, spirit and scope of the present application. All such modifications are within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the application.

Claims (10)

1. A semiconductor package apparatus, comprising:

a first mold seal material and a second mold seal material;

a first rewiring layer disposed between the first mold seal material and the second mold seal material;

the first chip is buried in the first mold sealing material and is electrically connected with the first rewiring layer through a first bonding wire.

2. The semiconductor package apparatus according to claim 1, wherein the first chip is connected to the first rewiring layer through a first adhesive layer, and a back surface of the first chip faces the first rewiring layer.

3. The semiconductor package apparatus according to claim 1, further comprising a second chip stacked on the first chip, the second chip being buried in the first mold compound.

4. The semiconductor package apparatus according to claim 3, wherein the second chip is electrically connected to the first chip through a second bonding wire.

5. The semiconductor package apparatus according to claim 1, further comprising: and the third chip is buried in the second mold sealing material and connected to the first rewiring layer through a second adhesive layer, and the back surface of the third chip faces the first rewiring layer.

6. The semiconductor package apparatus according to claim 5, further comprising: a fourth chip embedded in the second molding material and connected to the first rewiring layer through the second adhesive layer; the back of the fourth chip faces the first rewiring layer, the fourth chip and the third chip are arranged side by side, and the thickness of the fourth chip is different from that of the third chip.

7. The semiconductor package apparatus according to claim 1, further comprising: and a second redistribution layer provided on the other side of the second mold seal material with respect to the first redistribution layer.

8. The semiconductor package apparatus according to claim 1, further comprising: and the heat conduction layer is arranged on the other side of the first mold sealing material relative to the first rewiring layer.

9. The semiconductor package apparatus according to claim 1, wherein the hardness of the first mold seal material is greater than the hardness of the second mold seal material.

10. The semiconductor package apparatus of claim 1, wherein an active face of the first chip faces the first redistribution layer and is spaced apart from the first redistribution layer.