CN219917080U - Jig - Google Patents

Abstract

The utility model provides a jig, one embodiment of which comprises: the jig is suitable for carrying out mold sealing on a semiconductor structure, the semiconductor structure comprises an adhesive layer used for fixing, the jig is pressed on the semiconductor structure, and the jig comprises: the inside wall, inside wall with there is first space between the side of adhesion layer, avoid carrying carrier plate and adhesion layer and the tool direct contact that carries among the prior art, the tool presses the adhesion layer and causes the damage of adhesion layer, avoids removing carrier plate and adhesion layer in the prior art simultaneously after, directly carries out the mould seal, because the high temperature leads to the base plate warpage in the mould seal in-process, causes the problem of mould seal difficulty.

Description

Jig

Technical field

The utility model relates to the technical field of semiconductor packaging, in particular to a fixture.

Background technique

The current semiconductor packaging technology adheres the substrate to the carrier through a reusable adhesive layer, then welds the electronic components to the substrate, and then removes the carrier, and then separately molds the substrate with the electronic components. However, when performing the molding operation, the substrate lacks the support of the carrier board and is prone to warpage, which increases the difficulty of molding.

In order to avoid substrate warping, you can carry out the molding operation with the carrier board, and then remove the carrier board after molding. However, using this method, the molding fixture will crush the adhesive layer, making the adhesive layer unable to be reused.

Utility model content

The utility model provides a fixture.

The first method of the present invention is to provide a jig, which is suitable for molding semiconductor structures. The characteristic is that the semiconductor structure includes an adhesive layer for fixation, and the jig is overlaid on the semiconductor structure. , the fixture includes:

There is a first gap between the inner wall and the side surface of the adhesive layer.

In some optional implementations, the width of the first gap is no greater than 50 μm.

In some optional implementations, the semiconductor structure includes a substrate fixed on the adhesive layer, and a second gap exists between the inner side wall and the side surface of the substrate.

In some optional implementations, the width of the first gap is smaller than the width of the second gap.

In some optional embodiments, the inner side wall is stepped.

In some optional embodiments, the semiconductor structure includes a substrate fixed on the adhesive layer, and the inner sidewall includes a step contacting a top surface of the substrate.

In some optional implementations, the width of the contact surface between the step and the substrate is no greater than 50 μm.

In some optional implementations, the substrate has a positioning hole located in its inactive area, and the contact surface between the step and the substrate covers the positioning hole.

In some optional embodiments, the fixture includes:

An upper mold and a lower mold. The upper mold has an upper groove that is recessed upward from its bottom surface. The lower mold has a lower groove that is recessed downward from its top surface. The upper groove and the lower groove form a housing. In the cavity of the semiconductor structure, the inner side wall is the side wall of the upper groove.

In some optional implementations, the semiconductor structure further includes a carrier and a substrate, the carrier is located below the adhesive layer and carries the adhesive layer, and the substrate is fixed on the adhesive layer;

The lower groove accommodates the carrier plate, and the thickness of the carrier plate is substantially equal to the depth of the lower groove;

The upper groove accommodates the base plate, and the thickness of the base plate is less than the depth of the upper groove.

In some optional embodiments, the opening width of the upper groove is smaller than the opening width of the lower groove.

In order to solve the problem that the fixture will crush the adhesive layer during the molding process and the adhesive layer cannot be reused, the utility model proposes a fixture that is pressed on the semiconductor structure and has an inner wall. , there is a first gap between the inner wall and the side surface of the adhesive layer to avoid damage to the adhesive layer caused by the fixture pressing onto the adhesive layer.

Description of the drawings

Other features, objects and advantages of the present invention will become more apparent by reading the detailed description of the non-limiting embodiments with reference to the following drawings:

Figure 1 is a schematic diagram of the longitudinal cross-sectional structure of a current fixture suitable for molding semiconductor structures;

Figure 2 is a schematic longitudinal cross-sectional view of an embodiment of a jig 2a suitable for performing a molding process on a semiconductor structure according to the present invention;

Figure 3 is a schematic longitudinal cross-sectional structural diagram of an embodiment of a semiconductor structure placed in a jig 2a suitable for molding a semiconductor structure according to the present invention;

4 is a schematic longitudinal cross-sectional structural diagram of an embodiment of the semiconductor structure according to the present invention after molding;

Figure 5 is a schematic top structural view of an embodiment of the semiconductor structure according to the present invention after molding;

Figure 6 is a schematic longitudinal cross-sectional structural diagram of an embodiment 6a of a jig suitable for molding a semiconductor structure according to the present invention;

7 is a schematic longitudinal cross-sectional structural diagram of an embodiment of the semiconductor structure according to the present invention after molding;

Figure 8 is a schematic top structural view of an embodiment of the semiconductor structure according to the present invention after molding;

9-15 are schematic diagrams of the manufacturing steps of molding a semiconductor structure according to an embodiment of the present invention.

Explanation of reference signs/symbols:

10-carrier; 11-adhesive layer 12-substrate; 13-bump; 14-electronic component (die); 15-molding material; 16-upper mold; 17-lower mold ; 18-upper groove; 19-lower groove; 20-through hole; 21-step; 22-second gap; 23-first gap; 24-inner wall; 30-carrier; 31-adhesion Layer; 32-substrate; 33-bump; 34-electronic component (die); 35-molding material; 36-upper mold; 37-lower mold.

Detailed ways

Specific implementations of the present utility model will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by the present utility model and the technical effects produced by the content recorded in this specification. It can be understood that the specific embodiments described here are only used to explain the relevant invention, but not to limit the invention. In addition, for convenience of description, only parts relevant to the invention are shown in the drawings.

It should be easily understood that the meanings of "on", "on" and "on" in the present invention should be interpreted in the broadest sense, such that "on" ” means not only “directly on something” but also “on something” including the presence of intermediate parts or layers in between.

In addition, for convenience of description, spatially relative terms such as “below”, “below”, “lower”, “above”, “upper”, etc. may be used herein. The relationship of one element or component to another element or component as illustrated in the drawings. In addition to the orientation depicted in the figures, spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "layer" as used herein refers to a portion of material that includes a region of thickness. A layer may extend throughout the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. Furthermore, a layer may be a region of a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. The layers may extend horizontally, vertically and/or along tapered surfaces. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers on, above and/or below it. A layer can include multiple layers. For example, the semiconductor layers may include one or more doped or undoped semiconductor layers and may be of the same or different materials.

The term "substrate" as used herein refers to a material onto which subsequent layers of material are added. The substrate itself can be patterned. The material added to the top of the substrate can be patterned or can remain unpatterned. Additionally, the substrate may include a variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of non-conductive material, such as glass, plastic, or sapphire wafers. As a further alternative, the substrate may have a semiconductor device or circuit formed therein.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the specification are only used to coordinate with the content recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the implementation of the present invention. Therefore, it has no technical substantive significance. Any modification of the structure, change of the proportional relationship or adjustment of the size shall still fall within The technical content disclosed in this utility model must be within the scope that can be covered. At the same time, terms such as "above", "first", "second" and "a" cited in this specification are only for convenience of description and are not used to limit the scope of the present utility model. Changes or adjustments in their relative relationships, provided there is no substantial change in the technical content, shall also be deemed to be within the scope of the present utility model's implementation.

It should also be noted that the longitudinal section corresponding to the embodiment of the present invention may be a section corresponding to the direction of the front view, the transverse section may be a section corresponding to the direction of the right view, and the horizontal section may be a section corresponding to the direction of the top view.

In addition, the embodiments and features of the embodiments of the present invention may be combined with each other without conflict. The utility model will be described in detail below with reference to the accompanying drawings and embodiments.

Referring to FIG. 1 , FIG. 1 is a schematic structural diagram of a longitudinal section of a current fixture suitable for molding a semiconductor structure.

As shown in FIG. 1 , the jig includes an upper mold 36 and a lower mold 37 , and a cavity for accommodating the semiconductor structure is formed between the upper mold 36 and the lower mold 37 . The current semiconductor structure includes a substrate 32 adhered to a carrier 30 through an adhesive layer 31 , a plurality of electronic components 34 welded to the substrate 32 through bumps 33 , and molded using a molding material 35 , and the semiconductor structure is molded during molding. During the process, it is covered by the jig, which is used to assist the semiconductor structure in molding.

During the molding operation, because the upper mold 36 of the fixture is in direct contact with the adhesive layer 31 , the adhesive layer 31 will be damaged, affecting the reuse of the adhesive layer 31 and the carrier 30 , and increasing the cost of semiconductor packaging. If the carrier board is removed first to remove the adhesive layer 31 and the carrier board 30, and then the molding operation is performed, the substrate 32 will be warped due to the lack of support from the carrier board 30 and the molding temperature being too high, thereby increasing the molding process. Difficulty.

Therefore, in order to solve the above problems, the present utility model proposes a fixture.

Referring to FIG. 2 , FIG. 2 is a schematic longitudinal cross-sectional view of an embodiment of a jig 2 a suitable for performing a molding process on a semiconductor structure according to the present invention. As shown in Figure 2, the jig 2a of the present invention includes an upper mold 16 and a lower mold 17. The upper mold 16 has an upper groove 18 that is concave upward from its bottom surface, and the lower mold 17 has a concave groove that is concave downward from its top surface. The lower groove 19 , the upper groove 18 and the lower groove 19 form a cavity, and the cavity has an inner wall 24 .

Referring to FIG. 3 , FIG. 3 is a schematic longitudinal cross-sectional structural diagram of an embodiment of a semiconductor structure placed in a jig 2 a suitable for molding a semiconductor structure according to the present invention. As shown in Figures 2 and 3, the jig 2a of the present invention is suitable for molding semiconductor structures, and the semiconductor structures that need to be molded are placed in the cavity of the jig 2a. The semiconductor structure includes an adhesive layer 11 for fixing, and the jig 2a is pressed on the semiconductor structure. There is a first gap 23 between the inner side wall 24 of the jig 2a and the side surface of the adhesive layer 11. Therefore, direct contact between the fixture 2 a and the adhesive layer 11 can be avoided, thereby avoiding damage to the adhesive layer 11 .

Here, the adhesive layer 11 may be a liquid or gel adhesive (glue) or a tape (tape).

In some optional embodiments, the inner side wall 24 is stepped.

In some alternative embodiments, the inner side wall 24 is a side wall of the upper groove 18 .

In some embodiments, the width of the first gap 23 existing between the inner wall 24 of the jig 2a and the side surface of the adhesive layer 11 is no greater than 50 μm.

In some optional embodiments, the semiconductor structure in the jig 2a also includes a substrate 12 fixed on the adhesive layer 11, and there is a second gap 22 between the inner side wall 24 and the side surface of the substrate 12, and the second The width of the gap 22 is greater than the width of the first gap 23, that is, the width of the adhesive layer 11 will be greater than the width of the substrate 12, and in subsequent operations, the substrate 12 and the carrier plate 10 can be separated through the adhesive layer 11, ensuring that the carrier plate 10 and the recycling and reuse of the adhesive layer 11. This further saves the cost of using materials and reduces the cost of molding.

In some optional embodiments, the semiconductor structure of the present invention also includes electronic components 14 , and the electronic components 14 can be electrically connected to the substrate 12 through the bumps 13 . Here, the electronic component 14 may be various types of bare wafers (ie, Dies), which the present invention does not specifically limit. For example, the electronic component 14 may be a logic chip, a memory chip, a micro-electro-mechanical system (MEMS, Micro-Electro-Mechanical System) chip, a radio frequency chip, etc.

In some optional embodiments, the cavity of the fixture 2a of the present invention can be injected with liquid molding material during the molding process. After the molding material is cured, the molding material 15 covering the electronic component 14 is formed.

In some optional embodiments, the inner wall 24 of the jig 2a includes a step 21 that contacts the top surface of the substrate 12, and the step 21 can surround the substrate 12, so that the contact surface between the step 21 and the substrate 12 can be The molding material 15 is isolated from the second gap 22 and the first gap 23, thereby preventing the liquid molding material 15 from flowing into the second gap 22 and the first gap 23 during the molding process and affecting the molding effect.

In some optional embodiments, the width of the contact surface between the step 21 and the substrate 12 is no more than 50 μm, so that the molding material 15 formed after the molding operation maintains a normal width and avoids applying excessive pressure to the substrate 12 .

In some optional embodiments, the semiconductor structure further includes a carrier plate 10 , the carrier plate 10 is located below the adhesive layer 11 and carries the adhesive layer 11 , and the substrate 12 is fixed on the adhesive layer 11 ; the lower groove 19 To accommodate the carrier plate 10 , the thickness of the carrier plate 10 is substantially equivalent to the depth of the lower groove 19 ; the upper groove 18 accommodates the substrate 12 , and the thickness of the substrate 12 is smaller than the depth of the upper groove 18 .

In some optional embodiments, the opening width of the upper groove 18 of the jig 2a is smaller than the opening width of the lower groove 19 .

In some optional embodiments, in order to prevent the molding material 15 from flowing into the positioning holes in the inactive area of the substrate 12, the positioning holes in the inactive area of the substrate 12 can be sealed with some resin or other materials before performing the molding operation. The hole is sealed, and when the positioning hole needs to be used in subsequent operations, the mold sealing material 15 is re-drilled downward to form a new positioning hole.

Referring to Figure 4, Figure 4 is a schematic longitudinal cross-sectional structural diagram of an embodiment of the semiconductor structure of the present invention after molding. Figure 4 shows the removal of the carrier board from the molding material 15 based on Figure 3. The semiconductor structure formed by drilling downwards includes a substrate 12, a molding material 15, an electronic component 14 and a through hole 20 (ie, the positioning hole in the inactive area of the substrate 12).

In some optional embodiments, see Figure 5. Figure 5 is a schematic top structural view of an embodiment of a semiconductor structure according to the present invention after molding. Figure 5 is a schematic view of the semiconductor structure after molding after the removal of the carrier board. The positioning holes on the substrate 12 covered by the material 15 are re-drilled to form a plurality of through holes 20 to facilitate subsequent operations based on the plurality of through holes 20 .

In some optional embodiments, see FIG. 6 , which is a schematic longitudinal cross-sectional structural diagram of an embodiment 6a of a jig suitable for molding a semiconductor structure according to the present invention. The jig shown in FIG. 6 The fixture 6a is similar to the fixture 2a shown in Figure 3, except that:

In the jig 6a shown in Figure 6, the width of the contact surface between the step 21 and the substrate 12 is greater than 50 μm, so that the step 21 covers the positioning hole on the substrate 12, preventing the molding material 15 from entering the positioning hole, and further preventing the molding material 15 from entering the positioning hole. The flow flows to the back of the substrate 12 through the positioning holes. Compared with the aforementioned structure, in order to prevent the mold sealing material 15 from flowing into the positioning holes, the positioning holes are sealed in advance, and the subsequent re-drilling operation is performed as needed, which can reduce the tedious sealing process. Holes and punching operations simplify the molding process.

Referring to Figure 7, Figure 7 is a schematic longitudinal cross-sectional structural diagram of an embodiment of a semiconductor structure after molding according to the present invention, and is a semiconductor structure formed after removing the carrier board on the basis of Figure 6. Because Figure 6 The increase in the contact surface between the middle step 21 and the substrate 12 reduces the width of the molding material 15 formed, and at the same time avoids the sealing operation of the positioning holes in the invalid area of the substrate 12 before the molding operation, further avoiding the need for subsequent operations. The cumbersome operation of re-drilling the molding material 15 and the substrate 12 is performed to speed up the efficiency of the molding process.

Referring to Figure 8, Figure 8 is a schematic top view of an embodiment of a semiconductor structure according to the present invention after molding. As shown in Figure 8, the molding material 15 after molding does not cover the positioning holes on the substrate 12. (ie, the through hole 20), which reduces the need to re-punch the molding material 15 after molding to facilitate subsequent operations.

Referring now to FIGS. 9 to 15 , FIGS. 9 to 15 are schematic diagrams of the manufacturing steps of molding a semiconductor structure according to an embodiment of the present invention.

In order to better understand various aspects of the present invention, the figures have been simplified.

Referring to FIG. 9 , FIG. 9 illustrates the preparation operation of the carrier plate 10 . An adhesive layer 11 is added to the carrier plate 10 . The adhesive layer 11 here is generally tape.

Referring to FIG. 10 , FIG. 10 shows the step of adding the substrate 12 , and the substrate 12 is fixed on the carrier 10 through the adhesive layer 11 .

Referring to FIG. 11 , FIG. 11 illustrates a flip-chip soldering operation of electronic components. Multiple electronic components 14 are flip-chip soldered to the substrate 12 through bumps 13 .

Referring to Figure 12, Figure 12 shows the molding operation. The semiconductor structure obtained by the steps shown in Figure 11 is placed in a jig to perform the molding operation. The jig has an inner wall and a first gap between the adhesive layer 11 to avoid This eliminates the direct contact between the fixture and the adhesive layer 11, causing damage to the adhesive layer 11; the inner wall has a second gap with the base plate 12, and at the same time, the step 21 of the fixture is in contact with the base plate 12 to avoid molding during the molding process. The sealing material 15 flows into the first void and the second void, affecting the semiconductor structure generated by the molding.

Referring to FIG. 13 , FIG. 13 is a schematic diagram of a longitudinal cross-sectional structure of the molded semiconductor structure, that is, the molded semiconductor structure is formed after the jig is removed.

Referring to FIG. 14 , FIG. 14 illustrates the operation of removing the carrier board. The adhesive layer 11 is separated from the substrate 12 through the adhesive layer 11 , and recycling of the carrier board 10 and the adhesive layer 11 is realized.

Referring to Figure 15, Figure 15 shows the operation of re-drilling the molded semiconductor structure after removing the carrier board, by re-drilling downwards from the molding material 15, and opening up the substrate 12 to form a new through hole 20, so that Subsequent operations are performed based on the new through hole 20 .

Although the invention has been described and illustrated with reference to specific embodiments of the invention, these descriptions and illustrations do not limit the invention. It will be apparent to those skilled in the art that various changes may be made and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the invention as defined by the appended claims. Illustrations may not necessarily be drawn to scale. Differences may exist between technical representations of the invention and actual implementations due to manufacturing process variables and the like. There may be other embodiments of the invention not specifically illustrated. The instructions and drawings should be regarded as illustrative and not restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the object, spirit and scope of the invention. All such modifications are within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the present invention. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the invention.

Claims (10)

1. A jig suitable for use in molding a semiconductor structure, the semiconductor structure including an adhesive layer for securing, the jig overlying the semiconductor structure, the jig comprising:

and a first gap is formed between the inner side wall and the side surface of the adhesive layer.

2. The jig according to claim 1, wherein the width of the first void is not more than 50 μm.

3. The jig of claim 1, wherein the semiconductor structure comprises a substrate secured to the adhesive layer, a second gap being present between the inner sidewall and a side of the substrate.

4. The jig of claim 3, wherein the width of the first void is less than the width of the second void.

5. A jig according to claim 3, wherein the inner side wall is stepped.

6. The jig of claim 3, wherein the inner sidewall comprises a step contacting a top surface of the substrate.

7. The jig of claim 6, wherein the substrate has a positioning hole in an inactive area thereof, and a contact surface of the step with the substrate covers the positioning hole.

8. The jig according to claim 1, wherein the jig comprises:

the upper die is provided with an upper groove recessed upwards from the bottom surface of the upper die, the lower die is provided with a lower groove recessed downwards from the top surface of the lower die, the upper groove and the lower groove form a cavity for accommodating the semiconductor structure, and the inner side wall is the side wall of the upper groove.

9. The jig of claim 8, wherein the semiconductor structure further comprises a carrier and a substrate, the carrier being located below the adhesive layer and carrying the adhesive layer, the substrate being fixed on the adhesive layer;

the lower groove accommodates the carrier plate, and the thickness of the carrier plate is substantially equal to the depth of the lower groove;

the upper groove accommodates the substrate, and the thickness of the substrate is smaller than the depth of the upper groove.

10. The jig of claim 8, wherein the upper groove has an opening width smaller than an opening width of the lower groove.