CN219761295U - Linear 4.1 sound channel circuit - Google Patents
Linear 4.1 sound channel circuit Download PDFInfo
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- CN219761295U CN219761295U CN202321141956.4U CN202321141956U CN219761295U CN 219761295 U CN219761295 U CN 219761295U CN 202321141956 U CN202321141956 U CN 202321141956U CN 219761295 U CN219761295 U CN 219761295U
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Abstract
The utility model relates to the technical field of sound channel circuits, and discloses a linear 4.1 sound channel circuit, which comprises a CPU (central processing unit) electrically connected with a sound channel sheet source, a first power amplification chip electrically connected with the CPU, a second power amplification chip electrically connected with the CPU, a third power amplification chip electrically connected with the CPU, wherein the first power amplification chip is used for being electrically connected with a first left sound box and a first right sound box at the same time, the second power amplification chip is used for being electrically connected with a second left sound box and a second right sound box at the same time, and the third power amplification chip is used for being electrically connected with a subwoofer; the CPU is used for jointly outputting I2S signals to the first power amplification chip, the second power amplification chip and the third power amplification chip, and the first power amplification chip, the second power amplification chip and the third power amplification chip share the I2S signals; the utility model only needs to provide 1 path of data to be respectively supplied to 3 power amplifier chips for use by the application source end, and achieves a linear matrix mode, and the rear end can adjust the frequency curve of the sound according to the actual effect so as to achieve the effect of 4.1 channels.
Description
Technical Field
The utility model relates to the technical field of sound channel circuits, in particular to a linear 4.1 sound channel circuit.
Background
With the development of audio equipment, the application of sound channels is more and more extensive, and stereo sound meets the requirements of people on the experience of the position sense of the left sound channel and the right sound channel, but with the further development of technology, people gradually find that double sound channels cannot meet the requirements of people; the four-channel system can bring sound surrounding from a plurality of different directions to listeners, can obtain hearing feeling of being in various different environments, and brings brand new experience to users. Four-channel technology is widely integrated into the design of various middle-high-grade sound cards, and becomes the main trend of future development, and the four-channel technology mainly describes a linear 4.1-channel circuit design.
The traditional four-channel surround specifies 4 pronunciation points: front left, front right, back left, back right, the listener is enclosed in the middle. Meanwhile, a bass loudspeaker is also suggested to be added to enhance the playback processing of low-frequency signals (which is the reason that 4.1 channel loudspeaker systems are widely popular nowadays), a 4.1 channel film source is needed, the design end is more complicated, the linear 4.1 channel built in the text only needs one channel of signals to process 4.1 channel data, and the traditional 4.1 channel needs 3 channels of signals to process; some CPUs do not support 3 signals and cannot apply 4.1 channels.
Disclosure of Invention
The present utility model aims to provide a linear 4.1 channel circuit, which aims to solve the above problems in the prior art.
The utility model is realized in this way, the utility model provides a linear 4.1 sound channel circuit, which comprises a CPU electrically connected with a sound channel sheet source, a first power amplification chip electrically connected with the CPU, a second power amplification chip electrically connected with the CPU, a third power amplification chip electrically connected with the CPU, wherein the first power amplification chip is used for being electrically connected with a first left sound box and a first right sound box at the same time, the second power amplification chip is used for being electrically connected with a second left sound box and a second right sound box at the same time, and the third power amplification chip is used for being electrically connected with a subwoofer; the CPU is used for jointly outputting I2S signals to the first power amplification chip, the second power amplification chip and the third power amplification chip, and the first power amplification chip, the second power amplification chip and the third power amplification chip share the I2S signals.
Further, the input signal of the first power amplifier chip is an I2S signal: i2s_lrck, i2s_sclk, i2s_sdo, i2s_sdi, and I2C signals: i2c_sda, i2c_scl;
the input signal of the second power amplifier chip is an I2S signal: i2s_lrck, i2s_sclk, i2s_sdo, i2s_sdi, and I2C signals: i2c_sda, i2c_scl;
the input signal of the third power amplifier chip is an I2S signal: i2s_lrck, i2s_sclk, i2s_sdo, i2s_sdi, and I2C signals: i2c_sda, i2c_scl.
Further, the first power amplifier chip, the second power amplifier chip and the third power amplifier chip are all output in the form of data i2s_sdo.
Further, the first power amplifier chip is connected with an inductor L6403, the first power amplifier chip is further connected with an inductor L6404, the inductor L6403 is used for being connected with one end of the first left sound box, the inductor L6404 is used for being connected with the other end of the first left sound box, the inductor L6403 is electrically connected with one end of a capacitor C6442, the other end of the capacitor C6442 is electrically connected with one end of the capacitor C6443, and the other end of the capacitor C6443 is electrically connected with the inductor L6404.
Further, the first power amplifier chip is connected with an inductor L6405, the first power amplifier chip is further connected with an inductor L6406, the inductor L6405 is used for being connected with one end of a first right sound box, the inductor L6406 is used for being connected with the other end of the first right sound box, the inductor L6405 is electrically connected with one end of a capacitor C6444, the other end of the capacitor C6444 is electrically connected with one end of a capacitor C6445, and the other end of the capacitor C6445 is electrically connected with the inductor L6406.
Further, the second power amplification chip is connected with an inductor L3501, the second power amplification chip is further connected with an inductor L3502, the inductor L3501 is used for being connected with one end of a second left sound box, the inductor L3502 is used for being connected with the other end of the second left sound box, the inductor L3501 is electrically connected with one end of a capacitor C3515, the other end of the capacitor C3515 is electrically connected with one end of a capacitor C3516, and the other end of the capacitor C3516 is electrically connected with the inductor L3502.
Further, the second power amplification chip is connected with an inductor L3503, the second power amplification chip is further connected with an inductor L3504, the inductor L3503 is used for being connected with one end of a second right sound box, the inductor L3504 is used for being connected with the other end of a second left sound box, the inductor L3503 is electrically connected with one end of a capacitor C3517, the other end of the capacitor C3517 is electrically connected with one end of a capacitor C3518, and the other end of the capacitor C3518 is electrically connected with the inductor L3504.
Further, the third power amplifier chip is connected with an inductor L6407, the second power amplifier chip is further connected with an inductor L6409, the inductor L6407 is used for being connected with one end of a subwoofer, the inductor L6409 is used for being connected with the other end of the subwoofer, the inductor L6407 is electrically connected with a capacitor C6460, the C6460 is grounded, the inductor L6409 is electrically connected with a capacitor C6462, and the capacitor C6462 is grounded.
Further, the first power amplifier chip, the second power amplifier chip and the third power amplifier chip are all grounded.
Compared with the prior art, the linear 4.1 channel circuit provided by the utility model can be applied to most products; providing 1 path of signal to the first power amplification chip, the second power amplification chip and the third power amplification chip for use through the source end of the sound channel sheet, wherein the first power amplification chip and the second power amplification chip are used as 2.0 sound channels, and the third power amplification chip is used for connecting with a subwoofer; according to the scheme, only 1 path of I2S signals are provided by the CPU, the I2S signals are shared by 3 power amplifier chips, and data do not need to be acquired separately, so that a plurality of data do not need to be hung; the traditional 4.1 sound channel requires I2S to hang a plurality of data, and the CPU end also needs to provide a 4.1 sound channel film source to play; the 4.1 sound channel technology cannot be applied to many platforms, and the scheme is that an application source end only needs to provide 1 path of data to be respectively supplied to 3 power amplifier chips to be used in a mode of achieving a linear matrix; the back end can adjust the frequency curve of the sound according to the actual effect so as to achieve the effect of 4.1 sound channels.
Drawings
Fig. 1 is a block diagram of a linear 4.1 channel circuit according to an embodiment of the present utility model;
fig. 2 is a circuit diagram of a first power amplifier chip according to an embodiment of the present utility model;
fig. 3 is a circuit diagram of a second power amplifier chip according to an embodiment of the present utility model;
fig. 4 is a circuit diagram of a third power amplifier chip according to an embodiment of the present utility model.
Detailed Description
Embodiments of the present utility model are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the utility model.
In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present utility model and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present utility model.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present utility model, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present utility model, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present utility model, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
The implementation of the present utility model will be described in detail below with reference to specific embodiments.
Referring to fig. 1-4, a preferred embodiment of the present utility model is provided.
The utility model provides a linear 4.1 sound channel circuit, which comprises a CPU (central processing unit) electrically connected with a sound channel sheet source, a first power amplification chip electrically connected with the CPU, a second power amplification chip electrically connected with the CPU, a third power amplification chip electrically connected with the CPU, wherein the first power amplification chip is used for being electrically connected with a first left sound box and a first right sound box at the same time, the second power amplification chip is used for being electrically connected with a second left sound box and a second right sound box at the same time, and the third power amplification chip is used for being electrically connected with a subwoofer; the CPU is used for jointly outputting I2S signals to the first power amplification chip, the second power amplification chip and the third power amplification chip, and the first power amplification chip, the second power amplification chip and the third power amplification chip share the I2S signals.
The linear 4.1 channel circuit provided by the above can be applied to most products; providing 1 path of signal to the first power amplification chip, the second power amplification chip and the third power amplification chip for use through the source end of the sound channel sheet, wherein the first power amplification chip and the second power amplification chip are used as 2.0 sound channels, and the third power amplification chip is used for connecting with a subwoofer; according to the scheme, only 1 path of I2S signals are provided by the CPU, the I2S signals are shared by 3 power amplifier chips, and data do not need to be acquired separately, so that a plurality of data do not need to be hung; the traditional 4.1 sound channel requires I2S to hang a plurality of data, and the CPU end also needs to provide a 4.1 sound channel film source to play; the 4.1 sound channel technology cannot be applied to many platforms, and the scheme is that an application source end only needs to provide 1 path of data to be respectively supplied to 3 power amplifier chips to be used in a mode of achieving a linear matrix; the back end can adjust the frequency curve of the sound according to the actual effect so as to achieve the effect of 4.1 sound channels.
Specifically, the input signal of the first power amplifier chip is an I2S signal: i2s_lrck, i2s_sclk, i2s_sdo, i2s_sdi, and I2C signals: i2c_sda, i2c_scl;
the input signal of the second power amplifier chip is an I2S signal: i2s_lrck, i2s_sclk, i2s_sdo, i2s_sdi, and I2C signals: i2c_sda, i2c_scl;
the input signal of the third power amplifier chip is an I2S signal: i2s_lrck, i2s_sclk, i2s_sdo, i2s_sdi, and I2C signals: i2c_sda, i2c_scl.
Specifically, the first power amplifier chip, the second power amplifier chip and the third power amplifier chip are all output in the form of data i2s_sdo.
As a specific implementation manner, the first power amplification chip is connected with an inductor L6403, the first power amplification chip is further connected with an inductor L6404, the inductor L6403 is used for being connected with one end of the first left sound box, the inductor L6404 is used for being connected with the other end of the first left sound box, the inductor L6403 is electrically connected with one end of a capacitor C6442, the other end of the capacitor C6442 is electrically connected with one end of a capacitor C6443, and the other end of the capacitor C6443 is electrically connected with the inductor L6404.
As a specific implementation manner, the first power amplification chip is connected with an inductor L6405, the first power amplification chip is further connected with an inductor L6406, the inductor L6405 is used for being connected with one end of the first right sound box, the inductor L6406 is used for being connected with the other end of the first right sound box, the inductor L6405 is electrically connected with one end of a capacitor C6444, the other end of the capacitor C6444 is electrically connected with one end of a capacitor C6445, and the other end of the capacitor C6445 is electrically connected with the inductor L6406.
As a specific implementation manner, the second power amplification chip is connected with an inductor L3501, the second power amplification chip is further connected with an inductor L3502, the inductor L3501 is used for being connected with one end of the second left sound box, the inductor L3502 is used for being connected with the other end of the second left sound box, the inductor L3501 is electrically connected with one end of a capacitor C3515, the other end of the capacitor C3515 is electrically connected with one end of a capacitor C3516, and the other end of the capacitor C3516 is electrically connected with the inductor L3502.
As a specific implementation manner, the second power amplification chip is connected with an inductor L3503, the second power amplification chip is further connected with an inductor L3504, the inductor L3503 is used for being connected with one end of the second right sound box, the inductor L3504 is used for being connected with the other end of the second left sound box, the inductor L3503 is electrically connected with one end of a capacitor C3517, the other end of the capacitor C3517 is electrically connected with one end of a capacitor C3518, and the other end of the capacitor C3518 is electrically connected with the inductor L3504.
As a specific implementation manner, the third power amplification chip is connected with an inductor L6407, the second power amplification chip is further connected with an inductor L6409, the inductor L6407 is used for being connected with one end of a subwoofer, the inductor L6409 is used for being connected with the other end of the subwoofer, the inductor L6407 is electrically connected with a capacitor C6460, the C6460 is grounded, the inductor L6409 is electrically connected with a capacitor C6462, and the capacitor C6462 is grounded.
As a specific implementation manner, the first power amplification chip, the second power amplification chip and the third power amplification chip are all grounded; thus, the effect of protecting the power amplifier chip can be achieved.
The foregoing description of the preferred embodiments of the utility model is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the utility model.
Claims (9)
1. The linear 4.1 sound channel circuit is characterized by comprising a CPU (central processing unit) electrically connected with a sound channel film source, a first power amplification chip electrically connected with the CPU, a second power amplification chip electrically connected with the CPU, a third power amplification chip electrically connected with the CPU, wherein the first power amplification chip is used for being electrically connected with a first left sound box and a first right sound box at the same time, the second power amplification chip is used for being electrically connected with a second left sound box and a second right sound box at the same time, and the third power amplification chip is used for being electrically connected with a subwoofer; the CPU is used for jointly outputting I2S signals to the first power amplification chip, the second power amplification chip and the third power amplification chip, and the first power amplification chip, the second power amplification chip and the third power amplification chip share the I2S signals.
2. The linear 4.1 channel circuit of claim 1, wherein the input signal of the first power amplifier chip is an I2S signal: i2s_lrck, i2s_sclk, i2s_sdo, i2s_sdi, and I2C signals: i2c_sda, i2c_scl;
the input signal of the second power amplifier chip is an I2S signal: i2s_lrck, i2s_sclk, i2s_sdo, i2s_sdi, and I2C signals: i2c_sda, i2c_scl;
the input signal of the third power amplifier chip is an I2S signal: i2s_lrck, i2s_sclk, i2s_sdo, i2s_sdi, and I2C signals: i2c_sda, i2c_scl.
3. The linear 4.1 channel circuit of claim 2, wherein the first power amplifier chip, the second power amplifier chip, and the third power amplifier chip are all output as data i2s_sdo.
4. The linear 4.1-channel circuit of claim 1, wherein the first power amplifier chip is connected with an inductor L6403, the first power amplifier chip is further connected with an inductor L6404, the inductor L6403 is used for connecting one end of the first left speaker box, the inductor L6404 is used for connecting the other end of the first left speaker box, the inductor L6403 is electrically connected with one end of a capacitor C6442, the other end of the capacitor C6442 is electrically connected with one end of a capacitor C6443, and the other end of the capacitor C6443 is electrically connected with the inductor L6404.
5. The linear 4.1-channel circuit of claim 4, wherein the first power amplifier chip is connected with an inductor L6405, the first power amplifier chip is further connected with an inductor L6406, the inductor L6405 is used for connecting one end of the first right sound box, the inductor L6406 is used for connecting the other end of the first right sound box, the inductor L6405 is electrically connected with one end of a capacitor C6444, the other end of the capacitor C6444 is electrically connected with one end of a capacitor C6445, and the other end of the capacitor C6445 is electrically connected with the inductor L6406.
6. The linear 4.1-channel circuit of claim 1, wherein the second power amplification chip is connected with an inductor L3501, the second power amplification chip is further connected with an inductor L3502, the inductor L3501 is used for being connected with one end of a second left sound box, the inductor L3502 is used for being connected with the other end of the second left sound box, the inductor L3501 is electrically connected with one end of a capacitor C3515, the other end of the capacitor C3515 is electrically connected with one end of a capacitor C3516, and the other end of the capacitor C3516 is electrically connected with the inductor L3502.
7. The linear 4.1-channel circuit of claim 6, wherein the second power amplification chip is connected with an inductor L3503, the second power amplification chip is further connected with an inductor L3504, the inductor L3503 is used for connecting one end of a second right sound box, the inductor L3504 is used for connecting the other end of a second left sound box, the inductor L3503 is electrically connected with one end of a capacitor C3517, the other end of the capacitor C3517 is electrically connected with one end of a capacitor C3518, and the other end of the capacitor C3518 is electrically connected with the inductor L3504.
8. The linear 4.1-channel circuit of claim 1, wherein the third power amplification chip is connected with an inductor L6407, the second power amplification chip is further connected with an inductor L6409, the inductor L6407 is used for connecting one end of a subwoofer, the inductor L6409 is used for connecting the other end of the subwoofer, the inductor L6407 is electrically connected with a capacitor C6460, the C6460 is grounded, the inductor L6409 is electrically connected with a capacitor C6462, and the capacitor C6462 is grounded.
9. The linear 4.1 channel circuit of claim 1, wherein the first power amplifier chip, the second power amplifier chip, and the third power amplifier chip are all grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321141956.4U CN219761295U (en) | 2023-05-12 | 2023-05-12 | Linear 4.1 sound channel circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321141956.4U CN219761295U (en) | 2023-05-12 | 2023-05-12 | Linear 4.1 sound channel circuit |
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| Publication Number | Publication Date |
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| CN219761295U true CN219761295U (en) | 2023-09-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN202321141956.4U Active CN219761295U (en) | 2023-05-12 | 2023-05-12 | Linear 4.1 sound channel circuit |
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| CN (1) | CN219761295U (en) |
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- 2023-05-12 CN CN202321141956.4U patent/CN219761295U/en active Active
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