CN219609076U - Capacitance compensation circuit, capacitance detection circuit, chip and electronic device - Google Patents
Capacitance compensation circuit, capacitance detection circuit, chip and electronic device Download PDFInfo
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- CN219609076U CN219609076U CN202320288432.1U CN202320288432U CN219609076U CN 219609076 U CN219609076 U CN 219609076U CN 202320288432 U CN202320288432 U CN 202320288432U CN 219609076 U CN219609076 U CN 219609076U
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Abstract
The application discloses a capacitance compensation circuit, a capacitance detection circuit, a chip and electronic equipment, wherein in the capacitance compensation circuit, a capacitance module comprises N compensation capacitors and first double-channel switches which are respectively corresponding to the N compensation capacitors; the first ends of the N compensation capacitors are respectively connected with the inverting input ends of the operational amplifiers of the capacitance compensation circuit, the second ends of the N compensation capacitors are respectively connected with the first ends of the corresponding first two-channel switches, the second ends of the first two-channel switches are respectively connected with the first internal driving voltage of the capacitance detection circuit through the first resistor modules, and the third ends of the first two-channel switches are respectively connected with the second internal driving voltage of the capacitance detection circuit through the second resistor modules; the capacitance module is used for counteracting parasitic capacitance of the measurement pin of the capacitance detection circuit; the first resistor module and the second resistor module are used for preventing charge leakage of the capacitance detection circuit. The application can improve the accuracy of the determined capacitance to be measured.
Description
Technical Field
The application relates to the technical field of circuits, in particular to a capacitance compensation circuit, a capacitance detection circuit, a chip and electronic equipment.
Background
The capacitance detection chip is generally applied to products such as SAR sensors, touch detection, in-ear detection and the like, and two detection schemes of self capacitance and mutual capacitance are adopted aiming at different application scenes. The self-capacitance detection scheme is typically to apply an excitation voltage to a measurement pin to detect the magnitude of the capacitance between the pin and ground, and the mutual capacitance detection scheme is typically to apply an excitation voltage to one electrode to detect the magnitude of the mutual capacitance between the two electrodes. If the external input capacitance (including parasitic capacitance) of the chip is too large, saturation of the capacitance detection circuit is easily caused. Therefore, the capacitance sensing device is usually provided with a parasitic capacitance compensation function.
In the capacitive detection process, the voltages on the external input capacitor and the internal compensation capacitor are periodically changed, and considering that the charges on the capacitors are not suddenly changed, when the voltages of the lower electrode plates of the capacitors are switched, the voltages of the upper electrode plates of the capacitors (i.e. the middle nodes of the charge transfer paths) are also changed in the same direction, and in the extreme case, the voltages are higher than the power supply and/or lower than the ground voltage. When this voltage exceeds the turn-on voltage of the pn junction, charge leakage occurs during charge transfer, resulting in inaccurate results of capacitance detection.
Disclosure of Invention
In view of this, the present utility model provides a capacitance compensation circuit, a capacitance detection circuit, a chip and an electronic device, so as to solve the problem that in the conventional scheme, charge leakage may occur in the charge transfer process between the plates of the capacitor.
The utility model provides a capacitance compensation circuit, which is used for compensating parasitic capacitance in a capacitance detection circuit, wherein the capacitance detection circuit comprises an operational amplifier; the capacitance compensation circuit comprises a capacitance module, a first resistance module and a second resistance module, wherein the capacitance module comprises N compensation capacitors and first double-channel switches respectively corresponding to the N compensation capacitors;
the first ends of the N compensation capacitors are respectively connected with the inverting input ends of the operational amplifiers of the capacitance detection circuit, the second ends of the N compensation capacitors are respectively connected with the first ends of the corresponding first two-channel switches, the second ends of the first two-channel switches are respectively connected with the first internal driving voltage of the capacitance detection circuit through the first resistor modules, and the third ends of the first two-channel switches are respectively connected with the second internal driving voltage of the capacitance detection circuit through the second resistor modules;
the capacitance module is used for counteracting parasitic capacitance of the measurement pin of the capacitance detection circuit;
The first resistor module and the second resistor module are used for preventing charge leakage of the capacitance detection circuit.
Optionally, the capacitor module further includes first control switches corresponding to the N compensation capacitors, and each of the first control switches is connected between an inverting input terminal of the operational amplifier and a first terminal of the corresponding compensation capacitor; the N first control switches are used to turn on at least one of the compensation capacitors to provide an amount of charge for counteracting the parasitic capacitance.
Optionally, the first resistance module includes a first adjustment unit, and the second resistance module includes a second adjustment unit; the first adjusting unit is used for adjusting the equivalent impedance of the first resistor module according to the voltage of the inverting input end of the operational amplifier; the second adjusting unit is used for adjusting the equivalent impedance of the second resistor module according to the voltage of the inverting input end of the operational amplifier.
Optionally, the first adjusting unit includes a first comparator, a second control switch, and a first transistor; the positive input end of the first comparator is connected with the inverting input end of the operational amplifier, the negative input end of the first comparator is connected with the first internal driving voltage, the output end of the first comparator is connected with the grid electrode of the first transistor through the second control switch, the source electrode of the first transistor is connected with the first internal driving voltage, and the drain electrodes of the first comparator are respectively connected with one channel of the first two-channel switch.
Optionally, the first adjusting unit further includes a first capacitor; the first capacitor is connected between the positive input end and the output end of the first comparator; the first capacitor is used for adjusting the gradient of the grid voltage change of the first transistor.
Optionally, the second adjusting unit includes a second comparator, a third control switch, and a second transistor; the positive input end of the second comparator is connected with the inverting input end of the operational amplifier, the negative input end of the second comparator is connected with the second internal driving voltage, the output end of the second comparator is connected with the grid electrode of the second transistor through the third control switch, the source electrode of the second transistor is connected with the second internal driving voltage, and the drain electrodes of the second comparator are respectively connected with one channel of the first two-channel switch.
Optionally, the second adjusting unit further includes a second capacitor; the second capacitor is connected between the positive input end and the output end of the second comparator; the second capacitor is used for adjusting the gradient of the grid voltage change of the second transistor.
Optionally, the first adjusting unit and the second adjusting unit form a differential structure.
Optionally, the first resistor module further comprises a first adjustable resistor and a second two-channel switch; the first ends of the second double-channel switches are respectively connected with the channels of the first double-channel switches, the second ends of the second double-channel switches are connected with the first internal driving voltage through the first adjusting unit, and the third ends of the second double-channel switches are connected with the first internal driving voltage through the first adjustable resistor.
Optionally, the second resistor module further comprises a second adjustable resistor and a third dual-channel switch; the first ends of the third two-channel switches are respectively connected with the channels of the first two-channel switches, the second ends of the third two-channel switches are connected with the second internal driving voltage through the second adjusting unit, and the third ends of the third two-channel switches are connected with the second internal driving voltage through the second adjustable resistor.
The application also provides a capacitance detection circuit, which comprises any one of the capacitance compensation circuits.
Optionally, the capacitance detection circuit further comprises an operational amplifier; and the inverting input end of the operational amplifier is connected with the upper polar plate of the compensation capacitor in the capacitance compensation circuit.
Optionally, the capacitance detection circuit further includes a feedback capacitance; the feedback capacitor is connected between the inverting input terminal and the output terminal of the operational amplifier.
The application also provides a chip comprising any one of the capacitance detection circuits.
The application also provides electronic equipment comprising any one of the capacitance detection circuits or any one of the chips.
In the capacitance compensation circuit, the capacitance detection circuit, the chip and the electronic equipment provided by the application, the capacitance module can offset the parasitic capacitance of the measurement pin of the capacitance detection circuit, and the first resistance module and the second resistance module can prevent the capacitance detection circuit from leaking charges, so that the output voltage of the operational amplifier is more stable and accurate, and the accuracy of the capacitance to be measured determined according to the output voltage is improved.
Further, the first resistor module comprises a first adjusting unit, the second resistor module comprises a second adjusting unit, and the first adjusting unit and the second adjusting unit can respectively and automatically adjust the magnitude of equivalent impedance connected to the compensation capacitor in series according to the real-time voltage of the inverting input end of the operational amplifier, so that the risk of charge leakage is avoided; and the variable resistors such as the pull-up resistor, the pull-down resistor and the like can be prevented from being controlled respectively, so that the control process is simplified.
Furthermore, the control time sequence of the second control switch in the first adjusting unit and the control time sequence of the third control switch in the second adjusting unit can be matched with the control time sequence of the related switch component in the switching process from the reset stage to the detection stage of the capacitance detection circuit, frequent switching is not needed, the control time sequence is simpler, and the corresponding control process can be further simplified.
Therefore, the capacitance compensation circuit can simplify the control process when compensating the parasitic capacitance from various aspects on the basis of improving the accuracy of the determined capacitance to be measured.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a capacitance detection circuit in the course of a study;
FIG. 2 is a schematic diagram of a capacitance compensation circuit according to an embodiment of the application;
FIG. 3 is a schematic diagram of a capacitance compensation circuit according to another embodiment of the present application;
FIG. 4 is a schematic diagram of a capacitance compensation circuit according to another embodiment of the present application;
FIG. 5 is a schematic diagram of an adjusting unit according to an embodiment of the application;
FIG. 6 is a schematic diagram of an adjusting unit according to another embodiment of the application
FIG. 7 is a control timing diagram according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a capacitance compensation circuit according to another embodiment of the present application;
FIG. 9 is a schematic diagram of a capacitive sensing circuit according to an embodiment of the application;
fig. 10 is a schematic diagram of a capacitance detection circuit according to another embodiment of the application.
Detailed Description
The inventor studied a capacitance detection circuit, and referred to fig. 1, the capacitance detection circuit includes an operational amplifier OPAMP having a reset voltage VCM, an inverting input terminal voltage VIN, and an output voltage Vo; fig. 1 shows an externally input capacitance to be measured and a parasitic capacitance in a circuit structure of a capacitance detection circuit, where the circuit structure further includes a parasitic capacitance Cp, a capacitance to be measured Cx, a feedback capacitance Cfb, a capacitance compensation module 200, a fourth control switch Φ11, a fifth control switch Φ12, a sixth control switch Φ13, and a seventh control switch Φ21, and a first internal driving voltage VP and a second internal driving voltage VN are further provided in the capacitance detection circuit. The range of the first internal driving voltage VP and the second internal driving voltage VN is respectively between the ground voltage and the power voltage of the capacitance detection circuit; optionally VP > VN. The connection relationship of the capacitance detection circuit shown in fig. 1 includes that a first end of a fourth control switch Φ11 is used for accessing a first internal driving voltage VP, a second end is respectively grounded through a parasitic capacitance Cp, is grounded through a capacitance Cx to be detected, and is connected with an inverting input end of an operational amplifier OPAMP through a sixth control switch Φ21; the inverting input terminal of the operational amplifier OPAMP is connected to the non-inverting input terminal of the operational amplifier OPAMP and the second internal driving voltage VN, respectively, through the fifth control switch Φ12, and the inverting input terminal of the operational amplifier OPAMP is also connected to the output terminal of the operational amplifier OPAMP through the feedback capacitor Cfb, and the output terminal of the operational amplifier OPAMP is connected to the reset voltage VCM through the sixth control switch Φ13. The capacitance compensation module 200 is disposed at an inverting input terminal of the operational amplifier OPAMP, and a compensation capacitor Coff and a dual-channel switch are disposed in the capacitance compensation module 200, and a first channel Φ1 of the dual-channel switch is connected to the first internal driving voltage VP, and a second channel Φ2 of the dual-channel switch is connected to the second internal driving voltage VN.
Specifically, the working process of the capacitance detection circuit comprises a reset phase and a detection phase. In the resetting stage, a first channel phi 1 of the fourth control switch phi 11, the fifth control switch phi 12, the sixth control switch phi 13 and the two-channel switch is closed, a second channel phi 2 of the sixth control switch phi 21 and the two-channel switch is opened, and the capacitance detection circuit is reset; in the detection stage, the sixth control switch Φ21 and the second channel Φ2 of the two-channel switch are closed, the fourth control switch Φ11, the fifth control switch Φ12, the sixth control switch Φ13 and the first channel Φ1 of the two-channel switch are opened, and charges on the parasitic capacitance Cp, the capacitance to be detected Cx, the feedback capacitance Cfb and the compensation capacitance Coff in the capacitance compensation module 200 are redistributed; ideally, the compensation capacitance Coff and the charge amount stored on the parasitic capacitance Cp cancel each other out, and the charge amount changed on the capacitance Cx to be measured entirely flows into or out of the feedback capacitance Cfb. However, in the detection phase, at an instant when the sixth control switch Φ21 and the second channel Φ2 of the two-channel switch are closed, the voltage VIN at the inverting input terminal of the op amp deviates from VN due to the fact that the charges on the capacitors will not be suddenly changed. If VN is close to the power supply voltage or the ground voltage, the voltage VIN at the inverting input terminal of the operational amplifier OPAMP is easily higher than the power supply voltage or lower than the ground voltage, and in an extreme case, the voltage exceeds the forward turn-on voltage of the pn junction of the relevant transistor, so that the charge leakage occurs at the inverting input terminal of the operational amplifier OPAMP. Because the parasitic capacitance Cp, the capacitance to be measured Cx and the lower plate of the feedback capacitance Cfb are all strong drivers, the charge leakage does not affect the charges stored on the three capacitances, but rather affects the charges stored on the feedback capacitance Cfb, i.e., affects the output voltage Vo of the operational amplifier OPAMP, thereby affecting the accuracy of the capacitance to be measured Cx determined according to the output voltage Vo.
In view of the above problems, the present application can prevent the capacitance detection circuit from leaking charges, so that the output voltage Vo of the OPAMP is more stable and accurate, and the accuracy of the capacitance Cx to be measured determined according to the output voltage Vo is improved.
The following description of the embodiments of the present application will be made in detail and with reference to the accompanying drawings, wherein it is apparent that the embodiments described are only some, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application. The various embodiments described below and their technical features can be combined with each other without conflict.
The first aspect of the present application provides a capacitance compensation circuit for compensating for parasitic capacitance in a capacitance detection circuit. The structure of the capacitance detection circuit may be as shown in fig. 1, and includes an operational amplifier OPAMP, where the reset voltage of the operational amplifier OPAMP is VCM, the voltage of the inverting input terminal is VIN, and the output voltage is Vo.
Referring to fig. 2, the capacitance compensation circuit includes a capacitance module 110, a first resistance module 120 and a second resistance module 130, where the capacitance module 110 includes N compensation capacitances and first dual-channel switches corresponding to the N compensation capacitances, for example, fig. 2 shows that capacitance parameters are C and 2, respectively 1 C、2 2 C、……、2 N-1 N compensation capacitors of C, a 0 、a 1 、a 2 、……、a n-1 There are N first two-channel switches.
The first ends of the N compensation capacitors are respectively connected with the inverting input ends of the operational amplifier OPAMP of the capacitance detection circuit, the second ends of the N compensation capacitors are respectively connected with the first ends of the corresponding first two-channel switches, the second ends of the first two-channel switches are respectively connected with the first internal driving voltage VP of the capacitance detection circuit through the first resistor module 120, and the third ends of the first two-channel switches are respectively connected with the second internal driving voltage VN of the capacitance detection circuit through the second resistor module 130. Specifically, the first end of each first two-channel switch is connected to the second end of each first two-channel switch, so that a first channel of the first two-channel switch can be formed, and the first end of each first two-channel switch is connected to the third end of each first two-channel switch, so that a second channel of the first two-channel switch can be formed.
The capacitance module 110 is configured to cancel the parasitic capacitance Cp at the detection pin of the capacitance detection circuit. Specifically, the N compensation capacitors of the capacitor module 110 may form a capacitor array, and the capacitance parameters of the capacitor array may be adjusted by setting the first control signals of the N first dual-channel switches, so that the capacitance parameters can offset the parasitic capacitance Cp, so as to accurately obtain the capacitance Cx to be measured. Here, the first control signals of the N first two-channel switches may include a signal for turning on a certain channel of the first two-channel switches, for example, the first control signal a i =1, characterizing the first two-channel switch a i Switching on a first channel thereof, i.e. a first two-channel switch a i The first end of the capacitor detection circuit is connected to the second end through the first resistor module 120, and the first control signal a is connected to the first internal driving voltage VP of the capacitor detection circuit i = -1, characterizing a first two-channel switch a i Switching on the second channel, i.e. the first two-channel switch a i The first terminal of the capacitor detection circuit is connected to the third terminal, and the second internal driving voltage VN, i of the capacitor detection circuit is connected to the second resistor module 130, so that the values from 1 to N can be sequentially obtained.
The first resistor module 120 and the second resistor module 130 are used for preventing the capacitance detection circuit from leaking charges, so that the output voltage Vo of the operational amplifier OPAMP is more stable and accurate, and the accuracy of the capacitance Cx to be detected determined according to the output voltage Vo is improved. Specifically, the first resistor module 120 may be configured to determine a resistance parameter of the connection of the first internal driving voltage VP according to the inverted input voltage VIN of the operational amplifier OPAMP, and the second resistor module 130 may be configured to determine a resistance parameter of the connection of the second internal driving voltage VN according to the inverted input voltage VIN of the operational amplifier OPAMP, so that the inverted input voltage VIN of the operational amplifier OPAMP can be maintained in a relatively stable range, i.e., the inverted input voltage VIN is not much higher than the power supply voltage or much lower than the ground voltage.
Specifically, the first resistor module 120 and the second resistor module 130 may include adjustable resistors and/or equivalent impedances that can be adjusted according to factors such as switching operations of various stages in the capacitance detection circuit, so that the voltage VIN of the inverting input terminal of the operational amplifier OPAMP is not far higher than the power supply voltage or far lower than the ground voltage by adjusting the resistance parameters of the first resistor module 120 and the second resistor module 130, so as to prevent charge leakage at the inverting input terminal of the operational amplifier OPAMP, thereby preventing charge leakage in the capacitance detection circuit.
In one embodiment, referring to fig. 3, the capacitance module further includes first control switches corresponding to the N compensation capacitances, and fig. 3 shows b 0 、b 1 、b 2 、……、b n-1 And N first control switches. Each first control switch is connected between the inverting input end of the operational amplifier and the first end of the corresponding compensation capacitor and used for controlling the on-off of the corresponding compensation capacitor. The N first control switches are used to turn on at least one of the compensation capacitors to provide an amount of charge for canceling the parasitic capacitance Cp.
Alternatively, the capacitance detection circuit may first attempt to turn on a part of the compensation capacitance during the detection process, and determine the magnitude relationship between the supplied charge amount and the charge amount of the parasitic capacitance Cp by observing the relationship between the output voltage Vo and the preset voltage; if the provided charge amount is smaller than the charge amount of the parasitic capacitor Cp, the other compensation capacitors can be sequentially turned on until the output voltage Vo characterizes that the provided charge amount is consistent with the charge amount of the parasitic capacitor Cp; if provided for The amount of charge is greater than the amount of charge of the parasitic capacitance Cp, the switched compensation capacitance may be turned off in turn until the output voltage Vo characterizes the amount of charge provided in correspondence with the amount of charge of the parasitic capacitance Cp. Alternatively, the present embodiment may employ the second control signal b i Control the first control switch, the second control signal b i Simple control signals, e.g. second control signal b, which may be high or low i =1, characterizing the first control switch b on i Second control signal b i =0, characterizing the turning off of the first control switch b i I may take on values from 1 to N in sequence.
In one embodiment, the first resistor module 120 includes a first adjustment unit ra_p, and the second resistor module 130 includes a second adjustment unit ra_n. The first end of the first regulating unit Ra_P is respectively connected with each channel of each first two-channel switch, the second end is connected with the first internal driving voltage VP, and the third end is connected with the inverting input end voltage VIN of the operational amplifier OPAMP; the first end of the second adjusting unit ra_n is connected to each channel of each first two-channel switch, the second end is connected to the second internal driving voltage VN, and the third end is connected to the inverting input voltage VIN of the operational amplifier OPAMP.
The first adjusting unit ra_p is configured to adjust an equivalent impedance of the first resistor module according to an inverting input terminal voltage VIN of the operational amplifier OPAMP; the second adjusting unit ra_n is configured to adjust an equivalent impedance of the second resistor module according to the inverting input terminal voltage VIN of the operational amplifier OPAMP.
Specifically, the capacitance detection circuit comprises a reset stage and a detection stage; the first adjusting unit ra_p and the second adjusting unit ra_n may assist each other, and adjust the equivalent impedances corresponding to the first resistor module 120 and the second resistor module 130 according to the voltage VIN of the inverting input terminal of the OPAMP, that is, according to the switching operation from the reset stage to the detection stage, so that the voltage VIN of the inverting input terminal of the OPAMP is kept in a relatively stable range, and the situation that the voltage VIN of the inverting input terminal of the OPAMP is not far higher than the power supply voltage or far lower than the ground voltage is avoided, thereby achieving the purpose of preventing the leakage of charges at the inverting input terminal of the OPAMP.
Optionally, the first adjusting unit ra_p and the second adjusting unit ra_n may be implemented by MOS transistors with controllable gate voltages, and the gate voltages of the MOS transistors may be adjusted by a comparator, so as to simplify the structures of the first adjusting unit ra_p and the second adjusting unit ra_n, and ensure stability in the process of adjusting equivalent impedance.
In this embodiment, the first adjusting unit ra_p and the second adjusting unit ra_n can respectively automatically adjust the magnitude of the equivalent impedance connected in series to the compensation capacitor according to the real-time voltage VIN of the inverting input terminal of the operational amplifier OPAMP, so as to avoid the risk of charge leakage; and the variable resistors such as the pull-up resistor, the pull-down resistor and the like can be prevented from being controlled respectively, so that the control process is simplified.
In one example, referring to fig. 5, the first adjustment unit ra_p includes a first comparator CMP1, a second control switch S1, and a first transistor MP; alternatively, the first transistor MP is a PMOS transistor, and may be a pull-up transistor.
The positive input end of the first comparator CMP1 is connected to the inverting input end of the operational amplifier OPAMP to access the voltage VIN of the inverting input end, the negative input end of the first comparator CMP1 is connected to the first internal driving voltage VP, the output end of the first comparator CMP1 is connected to the gate of the first transistor MP through the second control switch S1, the source of the first transistor MP is connected to the first internal driving voltage VP, the drain is respectively connected to one channel of the first dual-channel switch, and the drain voltage of the first transistor MP is the lower plate voltage of the compensation capacitor connected in the capacitor module 110, denoted as VC.
Optionally, referring to fig. 6, the first adjusting unit ra_p further includes a first capacitor CL1; the first capacitor CL1 is connected between the positive input end and the output end of the first comparator CMP1, i.e. the first end of the first capacitor CL1 is connected to the inverting input end of the operational amplifier OPAMP to be connected to the inverting input end voltage VIN thereof, and the second end of the first capacitor CL1 is connected to the gate of the first transistor MP. The first capacitor CL1 is used for adjusting the slope of the gate voltage variation of the first transistor MP to make the equivalent impedance adjustment process of the first adjustment unit ra_p smoother.
In one example, as shown in fig. 5, the second adjustment unit ra_n includes a second comparator CMP2, a third control switch S2, and a second transistor MN; alternatively, the second transistor MN is an NMOS transistor, and may be a pull-down transistor.
The positive input end of the second comparator CMP2 is connected to the inverting input end of the operational amplifier OPAMP to access the voltage VIN of the inverting input end, the negative input end of the second comparator CMP2 is connected to the second internal driving voltage VN, the output end of the second comparator CMP2 is connected to the gate of the second transistor MN through the third control switch S2, the source of the second transistor MN is connected to the second internal driving voltage VN, the drain is respectively connected to one channel of the first dual-channel switch, and the drain voltage of the second transistor MN is the lower plate voltage of the compensation capacitor connected in the capacitor module 110, denoted as VC.
Optionally, as shown in fig. 6, the second adjusting unit ra_n further includes a second capacitor CL2; the second capacitor CL2 is connected between the positive input end and the output end of the second comparator CMP2, that is, the first end of the second capacitor CL2 is connected to the inverting input end of the operational amplifier OPAMP to access the voltage VIN of the inverting input end thereof, and the second end of the second capacitor CL2 is connected to the gate of the second transistor MN. The second capacitor CL2 is used for adjusting the slope of the gate voltage variation of the second transistor MN to make the equivalent impedance adjustment process of the second adjustment unit ra_n smoother.
Further, the first adjusting unit ra_p and the second adjusting unit ra_n shown in fig. 5 and fig. 6 may form a differential structure, so as to simplify the control timing of each control signal, and make the control process relatively simple and stable; and the control time sequence of the second control switch S1 in the first adjusting unit Ra_P and the control time sequence of the third control switch S2 in the second adjusting unit Ra_N can be matched with the control time sequence of the related switch component in the switching process from the reset stage to the detection stage of the capacitor detection circuit, frequent switching is not needed, so that the control time sequence is simpler, and the corresponding control process can be further simplified.
Specifically, referring to each control switch provided in the capacitance detection circuit shown in fig. 1, if Φ1 is used to represent the control timings of the fourth control switch Φ11, the fifth control switch Φ12, the sixth control switch Φ13, and the first channel Φ1 of the two-channel switch, Φ2 is used to represent the control timings of the sixth control switch Φ21 and the second channel Φ2 of the two-channel switch, where the two-channel switch may include the first two-channel switch. Referring to fig. 7, the control timing of the second control switch S1 may coincide with Φ1, and the control timing of the third control switch S2 may coincide with Φ2. In the reset phase of the capacitance detection circuit, the second control switch S1 is closed, the third control switch S2 is opened, the second comparator CMP2 is opened, and the gate of the first transistor MP is controlled by the first comparator CMP 1. Since the positive input terminal of the first comparator CMP1 is connected to the inverted input terminal voltage VIN, and the negative input terminal is connected to the first internal driving voltage VP, VP > VIN, the output of the first comparator CMP1 is at a low level, the first transistor MP is turned on, and the lower plate voltage VC of the turned-on compensation capacitor is finally pulled up to the first internal driving voltage VP. In the detection stage of the capacitance detection circuit, the second control switch S1 is opened, the third control switch S2 is closed, the first comparator CMP1 is opened, and the gate of the second transistor MN is controlled by the second comparator CMP 2. The inverting input terminal of the second comparator CMP2 is connected to the second internal driving voltage VN, and if the positive input terminal VIN of the second comparator CMP2 (i.e. the inverting input terminal of the operational amplifier OPAMP, the upper plate of the connected compensation capacitor) has a transient voltage higher than the second internal driving voltage VN, the gate voltage VG of the second transistor MN rapidly increases, and the on-resistance of the second transistor MN starts to be turned on and decreases with the increase of the gate voltage VG. If the positive input terminal VIN of the second comparator CMP2 has a transient voltage lower than the second internal driving voltage VN, the gate voltage VG of the second transistor MN remains unchanged or starts to drop (does not drop below the ground voltage), so that the on-resistance of the second transistor MN gradually increases. When the second transistor MN is turned on, the lower plate voltage VC of the turned-on compensation capacitor is pulled down, and the upper plate voltage VIN of the compensation capacitor is also lowered. If VIN is reduced far below the second internal driving voltage VN, the second transistor MN is turned off completely, and the voltage VC of the bottom plate of the compensation capacitor is not reduced any more. According to the virtual short characteristic of the operational amplifier, as the operational amplifier OPAMP is established, VIN is clamped slowly to the second internal driving voltage VN, and as the VIN voltage is recovered, the second transistor MN is turned on again, and the lower plate of the compensation capacitor is finally pulled down to VN, so that the inverting input VIN of the operational amplifier OPAMP can be dynamically maintained in the range between the ground voltage and the corresponding pn junction turn-on voltage to the power supply voltage in the whole detection stage.
Preferably, the size of the input tube corresponding to the positive input terminal of the second comparator CMP2 is larger than the size of the input tube corresponding to the negative input terminal, so that the bias current of the positive input terminal of the second comparator CMP2 is larger, and the output voltage VG of the second comparator CMP2 is low when vin=vn can be ensured. Here, by adjusting the ratio of the input pair of the second comparator CMP2, the size of the input tube corresponding to the positive input end of the second comparator CMP2 is larger than the size of the input tube corresponding to the negative input end of the second comparator CMP2, and the voltage of VIN corresponding to the second transistor MN when turned off is controlled, so long as the difference between the voltage of VIN and the voltage of the ground terminal is not more than the on voltage of the pn junction, the capacitance detection circuit will not leak charges.
In one example, referring to fig. 8, the first resistor module 120 further includes a first adjustable resistor RP and a second two-channel switch Sp. The first end of the second dual-channel switch Sp is connected to each channel of each first dual-channel switch, the second end is connected to the first internal driving voltage VP through the first adjusting unit ra_p, and the third end is connected to the first internal driving voltage VP through the first adjustable resistor RP. Specifically, the first end of the second two-channel switch Sp is connected to the second end thereof, so as to form a first channel of the second two-channel switch Sp, and the first end of the second two-channel switch Sp is connected to the third end thereof, so as to form a second channel of the second two-channel switch Sp.
Alternatively, the first adjustable resistor RP may be a single resistor or an array of resistors. If the first adjustable resistor RP is an N-bit resistor array, the second dual-channel switch Sp is an N-bit switch array, and each bit switch can be independently controlled by a register to access a corresponding resistor.
The present example may be configured in advance or by a register to configure a third control signal corresponding to the second two-channel switch Sp, to switch the second two-channel switch Sp on its first channel, to switch the first internal driving voltage VP on via the first adjusting unit ra_p, or to switch the second two-channel switch Sp on its second channel, to switch the first internal driving voltage VP on via the first adjustable resistor RP, to contribute to preventing charge leakage.
In one example, as shown in fig. 8, the second resistor module 130 further includes a second adjustable resistor RN and a third dual-channel switch Sn; the first end of the third dual-channel switch Sn is connected to each channel of the first dual-channel switch, the second end is connected to the second internal driving voltage VN through the second adjusting unit ra_n, and the third end is connected to the second internal driving voltage VN through the second adjustable resistor RN. Specifically, the first end of the third dual-channel switch Sn is connected to the second end thereof, so that a first channel of the third dual-channel switch Sn can be formed, and the first end of the third dual-channel switch Sn is connected to the third end thereof, so that a second channel of the third dual-channel switch Sn can be formed.
Alternatively, the second adjustable resistor RN may be a single resistor or an array of resistors. If the second adjustable resistor RN is an N-bit resistor array, the third dual-channel switch Sn is an N-bit switch array, and each bit switch can be independently controlled by a register to access a corresponding resistor.
The present example may be configured in advance or by a register to configure a fourth control signal corresponding to the third two-channel switch Sn, to switch on its first channel, to switch on the second internal driving voltage VN by the second adjusting unit ra_n, or to switch on its second channel, to switch on the second internal driving voltage VN by the second adjustable resistor RN, to contribute to preventing charge leakage.
The capacitance compensation circuit shown in fig. 8 can be connected to the first adjusting unit ra_p corresponding to the first channel or the first adjustable resistor RP corresponding to the first channel by setting the second dual-channel switch Sp, and can be connected to the second adjusting unit ra_n corresponding to the first channel or the second adjustable resistor RN corresponding to the first channel by setting the third dual-channel switch Sn, so that various charge leakage prevention schemes can be provided for the capacitance compensation circuit, and higher flexibility is provided. Optionally, in the capacitance compensation circuit shown in fig. 8, a third control signal corresponding to the second dual-channel switch Sp and a fourth control signal corresponding to the third dual-channel switch Sn may also be determined according to a compensation capacitance type of the capacitance module 110, for example, when the compensation capacitance is a signed capacitance, the third control signal may switch on a first channel of the second dual-channel switch Sp, so that a resistor connected to the first internal driving voltage VP selects the first adjustment unit ra_p, and the fourth control signal may switch on a second channel of the third dual-channel switch Sn, so that a resistor connected to the second internal driving voltage VN selects the second adjustable resistor RN; or when the compensation capacitor is a signed capacitor, the third control signal may switch on the second channel of the second dual-channel switch Sp to enable the resistor connected to the first internal driving voltage VP to select the first adjustable resistor RP, and the fourth control signal may switch on the first channel of the third dual-channel switch Sn to enable the resistor connected to the second internal driving voltage VN to select the second adjusting unit ra_n. When the compensation capacitor is an unsigned capacitor, the third control signal may switch on the first channel of the second dual-channel switch Sp, so that the resistor connected to the first internal driving voltage VP selects the first adjustment unit ra_p, the fourth control signal may switch on the first channel of the third dual-channel switch Sn, so that the resistor connected to the second internal driving voltage VN selects the second adjustment unit ra_n, and at this time, the structures of the first resistor module 120 and the second resistor module 130 may be as shown in fig. 5 and 6, and the magnitude of the corresponding equivalent impedance may be automatically adjusted according to the voltage VIN at the inverting input terminal of the operational amplifier OPAMP, respectively, so as to simplify the control process.
In the capacitance compensation circuit, the capacitance module 110 can offset the parasitic capacitance Cp of the measurement pin of the capacitance detection circuit, and the first resistor module 120 and the second resistor module 130 can prevent the capacitance detection circuit from leaking charges, so that the output voltage Vo of the operational amplifier OPAMP is more stable and accurate, and the accuracy of the capacitance Cx to be measured determined according to the output voltage Vo is improved. Further, the first resistor module 120 includes a first adjusting unit ra_p, the second resistor module 130 includes a second adjusting unit ra_n, and the first adjusting unit ra_p and the second adjusting unit ra_n can respectively automatically adjust the magnitude of the equivalent impedance connected in series to the compensation capacitor according to the real-time voltage VIN of the inverting input terminal of the operational amplifier OPAMP, so as to avoid the risk of charge leakage; and the variable resistors such as the pull-up resistor, the pull-down resistor and the like can be prevented from being controlled respectively, so that the control process is simplified. Further, the control timing of the second control switch S1 in the first adjusting unit ra_p and the control timing of the third control switch S2 in the second adjusting unit ra_n can be matched with the control timing of the relevant switch component in the switching process from the reset stage to the detection stage of the capacitance detection circuit, so that frequent switching is not required, the control timing is simpler, and the corresponding control process can be further simplified. Therefore, the capacitance compensation circuit can simplify the control process when compensating the parasitic capacitance from various aspects on the basis of improving the accuracy of the determined capacitance Cx to be measured.
The present application provides in a second aspect a capacitance detection circuit, as shown with reference to fig. 9, comprising a capacitance compensation circuit as described in any of the embodiments above. The capacitance compensation circuit can compensate parasitic capacitance generated in the capacitance detection circuit when the capacitance detection circuit detects external capacitance.
In one embodiment, as shown in fig. 9, the capacitance detection circuit further includes an operational amplifier OPAMP; the inverting input terminal of the operational amplifier OPAMP is connected to the upper plate of the compensation capacitor in the capacitance compensation circuit 100. Specifically, the inverting input terminal of the operational amplifier OPAMP may be connected to the upper plate of one compensation capacitor through each of the first control switches in the capacitance compensation circuit 100.
Optionally, as shown in fig. 9, the capacitance detection circuit further includes a feedback capacitance Cfb; the feedback capacitance Cfb is connected between the inverting input terminal and the output terminal of the operational amplifier OPAMP.
Specifically, if the capacitance detection circuit includes the capacitance to be detected and the parasitic capacitance, the circuit structure of the capacitance detection circuit may be shown with reference to fig. 10, where the circuit structure further includes the parasitic capacitance Cp, the capacitance to be detected Cx, the fourth control switch Φ11, the fifth control switch Φ12, the sixth control switch Φ13, and the seventh control switch Φ21, and the first internal driving voltage VP and the second internal driving voltage VN are further disposed in the capacitance detection circuit. The range of the first internal driving voltage VP and the second internal driving voltage VN is respectively between the ground voltage and the power voltage of the capacitance detection circuit; optionally VP > VN. The connection relationship of the capacitance detection circuit shown in fig. 10 includes that a first end of a fourth control switch Φ11 is used for accessing a first internal driving voltage VP, a second end is grounded through a parasitic capacitance Cp, and is grounded through a capacitance Cx to be detected and is connected with an inverting input end of an operational amplifier OPAMP through a sixth control switch Φ21; the inverting input terminal of the operational amplifier OPAMP is connected to the non-inverting input terminal of the operational amplifier OPAMP and the second internal driving voltage VN, respectively, through the fifth control switch Φ12, and the inverting input terminal of the operational amplifier OPAMP is also connected to the output terminal of the operational amplifier OPAMP through the feedback capacitor Cfb, and the output terminal of the operational amplifier OPAMP is connected to the reset voltage VCM through the sixth control switch Φ13. The capacitance compensation circuit 100 is disposed at an inverting input terminal of the operational amplifier OPAMP, first dual-channel switches corresponding to the N compensation capacitors and the N compensation capacitors are disposed in the capacitance compensation circuit 100, a first channel of each first dual-channel switch is connected to a first internal driving voltage VP of the capacitance detection circuit through the first resistor module 120, and a second channel of each first dual-channel switch is connected to a second internal driving voltage VN of the capacitance detection circuit through the second resistor module 130.
Next, the capacitance detection circuit shown in fig. 10 will be described as an example, in which the charge variation amounts of the respective partial capacitances are described when the reset phase is switched to the detection phase. From the reset stage to the detection stage, the charge variation Q1 on the capacitance Cx to be detected and the parasitic capacitance Cp is: q1= - (cx+cp) × (VP-VN), cx representing the capacitance parameter corresponding to the capacitance Cx to be measured, cp representing the capacitance parameter corresponding to the parasitic capacitance Cp. The charge variation Q2 on the switched-on compensation capacitor is: q2=coff (VP-VN), coff represents the capacitance parameter corresponding to the compensation capacitance switched on. Control the first control signal a in the capacitive module 110 i And a second control signal b i The capacitance parameter Coff corresponding to the switched-on compensation capacitance can be made equal to the capacitance corresponding to the parasitic capacitance CpThe parameter Cp, the amount of charge change on the switched compensation capacitor and the parasitic capacitor Cp cancel each other out, and for the whole capacitance detection circuit, the capacitance parameter Cx of the capacitance to be detected Cx can be simplified as: qx= -Cx (VP-VN), qx is an intermediate parameter determined according to the output voltage Vo, the first internal driving voltage VP and the second internal driving voltage VN are preset known amounts, and the capacitance parameter Cx of the capacitance Cx to be detected can be accurately calculated according to the above formula, so as to implement capacitance detection.
The capacitance detection circuit includes the capacitance compensation circuit 100 according to any one of the embodiments, and has all the advantages of the capacitance compensation circuit 100 according to any one of the embodiments, which are not described herein.
The application provides a chip in a third aspect, which comprises the capacitance detection circuit in any embodiment, can accurately detect corresponding external capacitance, has relatively simple control logic in the capacitance detection process, can be compatible with a signed and unsigned capacitance compensation scheme, and has strong applicability.
The application provides an electronic device in a fourth aspect, which comprises the capacitance detection circuit described in any embodiment or the chip described in any embodiment, and is capable of accurately detecting a corresponding external capacitance, and control logic in a capacitance detection process is relatively simple, and is capable of being compatible with a signed and unsigned capacitance compensation scheme at the same time, so that the applicability is strong.
Although the application has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The present application includes all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification.
That is, the foregoing embodiments of the present application are merely examples, and are not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions of the present application and the accompanying drawings, such as the combination of technical features of the embodiments, or direct or indirect application in other related technical fields, are included in the scope of the present application.
In addition, the present application may be identified by the same or different reference numerals for structural elements having the same or similar characteristics. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present application, the term "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described as "exemplary" in this disclosure is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make or use the present application. In the above description, various details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been shown in detail to avoid unnecessarily obscuring the description of the application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Claims (15)
1. A capacitance compensation circuit, wherein the capacitance compensation circuit is used for compensating parasitic capacitance in a capacitance detection circuit, and the capacitance detection circuit comprises an operational amplifier; the capacitance compensation circuit comprises a capacitance module, a first resistance module and a second resistance module, wherein the capacitance module comprises N compensation capacitors and first double-channel switches respectively corresponding to the N compensation capacitors;
the first ends of the N compensation capacitors are respectively connected with the inverting input ends of the operational amplifiers of the capacitance detection circuit, the second ends of the N compensation capacitors are respectively connected with the first ends of the corresponding first two-channel switches, the second ends of the first two-channel switches are respectively connected with the first internal driving voltage of the capacitance detection circuit through the first resistor modules, and the third ends of the first two-channel switches are respectively connected with the second internal driving voltage of the capacitance detection circuit through the second resistor modules;
the capacitance module is used for counteracting parasitic capacitance of the measurement pin of the capacitance detection circuit;
the first resistor module and the second resistor module are used for preventing charge leakage of the capacitance detection circuit.
2. The capacitance compensation circuit according to claim 1, wherein the capacitance module further comprises first control switches corresponding to the N compensation capacitances, respectively, each of the first control switches being connected between an inverting input terminal of the operational amplifier and a first terminal of the corresponding compensation capacitance;
The N first control switches are used to turn on at least one of the compensation capacitors to provide an amount of charge for counteracting the parasitic capacitance.
3. The capacitance compensation circuit according to claim 1, wherein the first resistance module comprises a first adjustment unit and the second resistance module comprises a second adjustment unit;
the first adjusting unit is used for adjusting the equivalent impedance of the first resistor module according to the voltage of the inverting input end of the operational amplifier;
the second adjusting unit is used for adjusting the equivalent impedance of the second resistor module according to the voltage of the inverting input end of the operational amplifier.
4. The capacitance compensation circuit according to claim 3, wherein the first adjustment unit includes a first comparator, a second control switch, and a first transistor;
the positive input end of the first comparator is connected with the inverting input end of the operational amplifier, the negative input end of the first comparator is connected with the first internal driving voltage, the output end of the first comparator is connected with the grid electrode of the first transistor through the second control switch, the source electrode of the first transistor is connected with the first internal driving voltage, and the drain electrodes of the first comparator are respectively connected with one channel of the first two-channel switch.
5. The capacitance compensation circuit according to claim 4, wherein the first adjusting unit further comprises a first capacitance; the first capacitor is connected between the positive input end and the output end of the first comparator; the first capacitor is used for adjusting the gradient of the grid voltage change of the first transistor.
6. The capacitance compensation circuit according to claim 3, wherein the second adjusting unit includes a second comparator, a third control switch, and a second transistor;
the positive input end of the second comparator is connected with the inverting input end of the operational amplifier, the negative input end of the second comparator is connected with the second internal driving voltage, the output end of the second comparator is connected with the grid electrode of the second transistor through the third control switch, the source electrode of the second transistor is connected with the second internal driving voltage, and the drain electrodes of the second comparator are respectively connected with one channel of the first two-channel switch.
7. The capacitance compensation circuit according to claim 6, wherein the second adjusting unit further comprises a second capacitance; the second capacitor is connected between the positive input end and the output end of the second comparator; the second capacitor is used for adjusting the gradient of the grid voltage change of the second transistor.
8. A capacitance compensation circuit according to claim 3 wherein the first and second adjustment units form a differential structure.
9. The capacitance compensation circuit of claim 3 wherein the first resistor module further comprises a first adjustable resistor and a second two-channel switch;
the first ends of the second double-channel switches are respectively connected with the channels of the first double-channel switches, the second ends of the second double-channel switches are connected with the first internal driving voltage through the first adjusting unit, and the third ends of the second double-channel switches are connected with the first internal driving voltage through the first adjustable resistor.
10. The capacitance compensation circuit of claim 3 wherein the second resistor module further comprises a second adjustable resistor and a third dual channel switch;
the first ends of the third two-channel switches are respectively connected with the channels of the first two-channel switches, the second ends of the third two-channel switches are connected with the second internal driving voltage through the second adjusting unit, and the third ends of the third two-channel switches are connected with the second internal driving voltage through the second adjustable resistor.
11. A capacitance detection circuit, characterized in that the capacitance detection circuit comprises the capacitance compensation circuit according to any one of claims 1 to 10.
12. The capacitance detection circuit according to claim 11, wherein the capacitance detection circuit further comprises an operational amplifier; and the inverting input end of the operational amplifier is connected with the upper polar plate of the compensation capacitor in the capacitance compensation circuit.
13. The capacitance detection circuit according to claim 11, wherein the capacitance detection circuit further comprises a feedback capacitance; the feedback capacitor is connected between the inverting input terminal and the output terminal of the operational amplifier.
14. A chip comprising the capacitance detection circuit of any one of claims 11 to 13.
15. An electronic device comprising the capacitance detection circuit of any one of claims 11 to 13 or the chip of claim 14.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320288432.1U CN219609076U (en) | 2023-02-21 | 2023-02-21 | Capacitance compensation circuit, capacitance detection circuit, chip and electronic device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320288432.1U CN219609076U (en) | 2023-02-21 | 2023-02-21 | Capacitance compensation circuit, capacitance detection circuit, chip and electronic device |
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| CN219609076U true CN219609076U (en) | 2023-08-29 |
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| CN202320288432.1U Active CN219609076U (en) | 2023-02-21 | 2023-02-21 | Capacitance compensation circuit, capacitance detection circuit, chip and electronic device |
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