CN219420745U - Multiplexing multi-interface circuit structure - Google Patents
Multiplexing multi-interface circuit structure Download PDFInfo
- Publication number
- CN219420745U CN219420745U CN202320686818.8U CN202320686818U CN219420745U CN 219420745 U CN219420745 U CN 219420745U CN 202320686818 U CN202320686818 U CN 202320686818U CN 219420745 U CN219420745 U CN 219420745U
- Authority
- CN
- China
- Prior art keywords
- electrically connected
- branch
- signal line
- field effect
- interface circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Electronic Switches (AREA)
Abstract
The utility model discloses a multiplexing multi-interface circuit structure, which belongs to the technical field of robot control and comprises two groups of multi-path selectors; the input ends of the two groups of multiplexers are respectively electrically connected with the I2C_SCL signal line and the I2C_SDA signal line; each output end of one group of the multiplexers is electrically connected with a plurality of I2C_SCL signal lines; the outputs of the other set of multiplexers are electrically connected to the multiple i2c_sda signal lines. Through the mode, the utility model forms the multiplexer through the two groups of analog switches, multiplexes the SDA and SCL signal lines of the I2C bus into the multiplexing I2C_SCL signal line and the I2C_SDA signal line, expands the limited processor pins to a larger number of interfaces, and realizes the balance of cost and channel number.
Description
Technical Field
The utility model relates to the technical field of robot control, in particular to a multiplexing multi-interface circuit structure.
Background
The building block robot is a robot in various forms formed by integrating a controller, a motor and a sensor into a building block system and splicing and constructing a plurality of building blocks. And programming is utilized, so that the controller can control the motor and the sensor to work, and finally, the building block robot can move to complete various tasks.
However, when there are multiple paths, such as 8 paths of I2C interfaces, on the demand setting controller, the conventional controller cannot provide so many I2C interfaces, and it is necessary to expand the I2C bus interfaces, and how to achieve the balance between the cost and the number of channels is a problem to be solved in the art.
Based on the above, the present utility model designs a multiplexing multi-interface circuit structure to solve the above problems.
Disclosure of Invention
In view of the foregoing drawbacks of the prior art, the present utility model provides a multiplexing multi-interface circuit structure.
In order to achieve the above purpose, the utility model is realized by the following technical scheme:
a multiplexing multi-interface circuit structure comprises two groups of multiplexers;
one branch of the input end of one group of the multiplexers is electrically connected with the protection circuit DEV through a resistor A, and the other branch is electrically connected with the drain electrode of the first field effect transistor; the grid electrode of the first field effect transistor is electrically connected with the MCU; the I2C_SCL signal line of the input end is electrically connected with the source electrode of the first field effect transistor, and the MCU is electrically connected with the I2C_SCL signal line of the input end at the left side of the source electrode of the first field effect transistor through a resistor B; one branch of the input end of the other group of multiplexers is electrically connected with the protection circuit DEV through a resistor C, and the other branch is electrically connected with the drain electrode of the field effect tube II; the grid electrode of the second field effect transistor is electrically connected with the MCU; the I2C_SDA signal line of the input end is electrically connected with the source electrode of the second field effect transistor, and the MCU is electrically connected with the I2C_SDA signal line of the input end at the left side of the source electrode of the second field effect transistor through a resistor D;
each output end of one group of the multiplexers is electrically connected with a plurality of I2C_SCL signal lines; the outputs of the other set of multiplexers are electrically connected to the multiple i2c_sda signal lines.
Further, the multiplexer employs an analog switch.
Furthermore, one branch of the power supply VDD terminal of one group of analog switches is electrically connected to the protection circuit DEV, and the other branch is grounded through the capacitor a and the capacitor B.
Furthermore, one branch of the power supply VDD end of the other group of analog switches is electrically connected with the MCU, and the other branch is grounded through a capacitor C; the MCU is grounded through a capacitor D.
Further, one branch of each output end of one group of analog switches is electrically connected with the I2C_SDA signal line of the output end through a resistor E, and the other branch is grounded through a transient voltage suppression diode.
Furthermore, one branch of each output end of the other group of analog switches is electrically connected with the I2C_SDA signal line of the output end through a resistor F, and the other branch is grounded through a transient voltage suppression diode.
Furthermore, the input ends of the other group of analog switches are also respectively and electrically connected with the MCU through resistors G.
Further, the VEE terminal, INH terminal, and VSS terminal of the two groups of analog switches are all grounded.
Furthermore, the first field effect transistor and the second field effect transistor are of the SI2302 type; the transient voltage suppression diode adopts model SMF5.0CA; the analog switch adopts a CD4051BMT/TR model; the i2c_scl signal line or the i2c_sda signal line at the output of the analog switch has eight groups.
Advantageous effects
The utility model forms a multiplexer through two groups of analog switches, multiplexes SDA and SCL signal lines of the I2C bus into a plurality of I2C_SCL signal lines and I2C_SDA signal lines, and then the hardware can be packaged by driving, so that a user can operate the plurality of I2C by adopting a conventional I2C operation method, and the signal quality, the speed and the compatibility of the plurality of I2C are all comparable to those of the I2C bus;
the utility model can expand the limited processor pins to more interfaces by adopting the multiplexing electronic switch in the controller, thereby realizing the balance of cost and channel number.
Drawings
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the present utility model and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a circuit diagram of a multiplexing multi-interface circuit of the present utility model;
fig. 2 is a functional block diagram of a multiplexing multi-interface circuit structure of the present utility model.
Description of the embodiments
In order to make the objects, technical solutions and advantages of the embodiments of the present utility model more clear, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. It will be apparent that the described embodiments are some, but not all, embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
The utility model is further described below with reference to examples.
Examples
Referring to fig. 1-2 of the drawings, a multiplexing multi-interface circuit structure includes two groups of multiplexers;
the input ends of the two groups of multiplexers are respectively electrically connected with the I2C_SCL signal line and the I2C_SDA signal line;
preferably, the multiplexer adopts an analog switch; for example, analog switch CD4051BMT/TR;
each output end of one group of the multiplexers is electrically connected with a plurality of I2C_SCL signal lines;
preferably, each output end of one group of the multiplexers is electrically connected with 8 paths of I2C_SCL signal lines respectively;
each output end of the other group of multiplexers is electrically connected with a plurality of I2C_SDA signal lines;
preferably, each output end of the other group of multiplexers is electrically connected with 8 paths of I2C_SDA signal lines respectively;
preferably, one branch of the input end of one group of analog switches is electrically connected with the protection circuit DEV through a resistor, and the other branch is electrically connected with the drain electrode of the field effect transistor Q15; the grid electrode of the field effect transistor Q15 is electrically connected with the MCU; the I2C_SCL signal line of the input end is electrically connected with the source electrode of the field effect transistor Q15, and the MCU is electrically connected with the I2C_SCL signal line of the input end at the left side of the source electrode of the field effect transistor Q15 through a resistor;
the protection circuit DEV may employ an electrostatic ESD tube or the like;
one branch of the input end of the other group of analog switches is electrically connected with the protection circuit DEV through a resistor, and the other branch is electrically connected with the drain electrode of the field effect transistor Q16; the grid electrode of the field effect transistor Q16 is electrically connected with the MCU; the I2C_SDA signal line of the input end is electrically connected with the source electrode of the field effect transistor Q16, and the MCU is electrically connected with the I2C_SDA signal line of the input end at the left side of the source electrode of the field effect transistor Q16 through a resistor;
preferably, the field effect transistors Q15 and Q16 can be of the SI2302 type;
one branch of the power supply VDD end of one group of analog switches is electrically connected with the protection circuit DEV, and the other branch is grounded through a capacitor C53 and a capacitor C52;
one branch of the power supply VDD end of the other group of analog switches is electrically connected with the MCU, and the other branch is grounded through a capacitor C54; the MCU is grounded through a capacitor C55;
one branch of each output end of one group of analog switches is electrically connected with an I2C_SDA signal line of the output end through a resistor, and the other branch is grounded through a transient voltage suppression diode;
one branch of each output end of the other group of analog switches is electrically connected with the I2C_SDA signal line of the output end through a resistor, and the other branch is grounded through a transient voltage suppression diode;
the input ends of the other group of analog switches are also respectively and electrically connected with the MCU through resistors;
preferably, the transient voltage suppression diode is model SMF5.0CA;
the VEE end, the INH end and the VSS end of the two groups of analog switches are all grounded;
the utility model forms a multiplexer through two groups of analog switches, multiplexes SDA and SCL signal lines of the I2C bus into a plurality of I2C_SCL signal lines and I2C_SDA signal lines, and then the hardware can be packaged by driving, so that a user can operate the plurality of I2C by adopting a conventional I2C operation method, and the signal quality, the speed and the compatibility of the plurality of I2C are all comparable to those of the I2C bus;
the utility model can expand the limited processor pins to more interfaces by adopting the multiplexing electronic switch in the controller, thereby realizing the balance of cost and channel number.
The above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model.
Claims (9)
1. A multiplexing multi-interface circuit structure comprising two sets of multiplexers;
one branch of the input end of one group of the multiplexers is electrically connected with the protection circuit DEV through a resistor A, and the other branch is electrically connected with the drain electrode of the first field effect transistor; the grid electrode of the first field effect transistor is electrically connected with the MCU; the I2C_SCL signal line of the input end is electrically connected with the source electrode of the first field effect transistor, and the MCU is electrically connected with the I2C_SCL signal line of the input end at the left side of the source electrode of the first field effect transistor through a resistor B; one branch of the input end of the other group of multiplexers is electrically connected with the protection circuit DEV through a resistor C, and the other branch is electrically connected with the drain electrode of the field effect tube II; the grid electrode of the second field effect transistor is electrically connected with the MCU; the I2C_SDA signal line of the input end is electrically connected with the source electrode of the second field effect transistor, and the MCU is electrically connected with the I2C_SDA signal line of the input end at the left side of the source electrode of the second field effect transistor through a resistor D;
each output end of one group of the multiplexers is electrically connected with a plurality of I2C_SCL signal lines; the outputs of the other set of multiplexers are electrically connected to the multiple i2c_sda signal lines.
2. The multiplexing multi-interface circuit structure of claim 1, wherein the multiplexer employs an analog switch.
3. The multiplexing multi-interface circuit structure of claim 2, wherein one branch of the power supply VDD terminal of one set of analog switches is electrically connected to the protection circuit DEV, and the other branch is grounded through the capacitors a and B.
4. A multiplexing multi-interface circuit structure according to claim 3, wherein one branch of the power supply VDD terminal of the other group of analog switches is electrically connected to the MCU, and the other branch is grounded through a capacitor C; the MCU is grounded through a capacitor D.
5. The multiplexing multi-interface circuit structure of claim 4, wherein one branch of each output of a set of analog switches is electrically connected to the i2c_sda signal line of the output through a resistor E, and the other branch is grounded through a transient voltage suppression diode.
6. The multiplexing multi-interface circuit structure of claim 5, wherein one branch of each output of the other set of analog switches is electrically connected to the i2c_sda signal line of the output via a resistor F, and the other branch is grounded via a transient voltage suppression diode.
7. The multiplexing multi-interface circuit structure of claim 6, wherein the inputs of the other set of analog switches are further electrically connected to the MCUs through resistors G, respectively.
8. The multiplexing multi-interface circuit structure of claim 7, wherein the VEE terminals, INH terminals, and VSS terminals of the two groups of analog switches are all grounded.
9. The multiplexing multi-interface circuit structure according to any one of claims 2-8, wherein the first field effect transistor and the second field effect transistor are SI 2302; the transient voltage suppression diode adopts model SMF5.0CA; the analog switch adopts a CD4051BMT/TR model; the i2c_scl signal line or the i2c_sda signal line at the output of the analog switch has eight groups.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320686818.8U CN219420745U (en) | 2023-03-31 | 2023-03-31 | Multiplexing multi-interface circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320686818.8U CN219420745U (en) | 2023-03-31 | 2023-03-31 | Multiplexing multi-interface circuit structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219420745U true CN219420745U (en) | 2023-07-25 |
Family
ID=87206465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320686818.8U Active CN219420745U (en) | 2023-03-31 | 2023-03-31 | Multiplexing multi-interface circuit structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219420745U (en) |
-
2023
- 2023-03-31 CN CN202320686818.8U patent/CN219420745U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103091526B (en) | Voltage detection circuit | |
| SU1573458A2 (en) | Addressing device | |
| CN113704157B (en) | System for controlling multipath reset signals with different levels based on bus | |
| CN116225197B (en) | Voltage mode driving method and circuit | |
| CN107222213B (en) | Analog-to-digital converter based on single chip microcomputer technology | |
| CN219420745U (en) | Multiplexing multi-interface circuit structure | |
| US7425860B2 (en) | Level converting circuit | |
| CN209267542U (en) | Slope control switch circuit and electronic equipment | |
| KR970022771A (en) | Calculation circuit and instant recognition method with instant recognition | |
| CN107707248A (en) | Same OR circuit, adjusting method and NOR gate circuit | |
| WO2024001537A1 (en) | Input circuit for display apparatus, and display apparatus and control method therefor | |
| CN215340774U (en) | Circuit for automatic selection of slave machine of photovoltaic film selection equipment controller | |
| CN214626961U (en) | Novel voltage switching circuit and communication logic conversion circuit | |
| US10109235B2 (en) | Compensation circuit, AMOLED structure and display device | |
| DE10107437A1 (en) | display module | |
| CN109119045B (en) | Display driving device, display device and display module | |
| AU8107898A (en) | Interconnect apparatus including a signal bus | |
| US11249528B2 (en) | Power supply device for supplying power to server and power supply management system | |
| JPS6120421A (en) | Semiconductor integrated circuit | |
| CN107610667B (en) | LCD driving circuit | |
| CN112951142A (en) | Gate drive circuit, display panel and display device | |
| CN221283176U (en) | Digital quantity acquisition circuit, chip and device | |
| CN117200781A (en) | Drive output circuit and electronic apparatus | |
| CN220773583U (en) | Connecting circuit, circuit board and connecting device | |
| CN113595546B (en) | Broadband high-speed level switching circuit and high-speed clock chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |