CN219350223U - Chip circuit structure - Google Patents

Abstract

The utility model provides a chip circuit structure, which belongs to the technical field of integrated circuit design and comprises a metal layer, wherein the metal layer comprises an active wire area and a passive wire area, and the distance between the active wire area and the passive wire area is larger than a first preset value. The utility model can reduce the probability of short circuit between the active line area and the passive line area of different wafers when the chips are stacked, thereby reducing the chip failure problem caused by overlarge current in the test process.

Description

Chip circuit structure

Technical Field

The utility model belongs to the technical field of integrated circuit design, and particularly relates to a chip circuit structure.

Background

With the development of semiconductor technology, the cost of reducing the size of a semiconductor process is higher and higher, while with the successful use of a silicon wafer thinning technology, the three-dimensional integrated chip stacking technology can effectively enhance the functions and performances of electronic products while reducing the size of the chips, so as to achieve the effect of reducing the size of the semiconductor products, and thus the three-dimensional integrated chip stacking technology is widely used, but the three-dimensional stacking technology needs to stack two or more wafers, and the number of chip failures caused by any defect is doubled in the process of stacking the wafers, so that the chip failure caused by the defect problem is reduced as much as possible, the improvement of the wafer yield is particularly important, and the defect is generally the tangible pollution or the imperfection existing on the wafers and is generally caused by one of the following factors:

1. physical variability on the wafer, such as: dust, process residues or abnormal reaction products.

2. Chemical contamination, for example: residual chemicals or organic solvents.

3. Pattern defects such as: abnormal imaging caused by photoetching or etching, mechanical scratch deformation and abnormal color caused by uneven thickness.

4. The wafer itself or a lattice curve induced during the fabrication process.

It is found that when two wafers are bonded face to form a bond between a metal layer and an oxide layer, for larger-sized products, the chip loss per wafer due to defects resulting in short circuit or open circuit becomes more and more apparent, and the short circuit or open circuit becomes a major source of chip failure.

Disclosure of Invention

In order to solve the above-mentioned problems of short circuit or open circuit in the prior art, which is a main source of chip failure, the present utility model provides a chip circuit structure for avoiding the problems of short circuit or open circuit of wafers during stacking.

Because great effort, time and cost are required to be invested in improving the short circuit problem or the open circuit problem generated when the wafers are stacked from the aspect of factory processing and the effect is very little, the metal circuit layout is optimized from the design end, so that the robustness of the product is enhanced; the specific technical scheme is as follows:

a chip circuit structure, the chip circuit structure comprising:

the metal layer comprises an active line area and a passive line area, wherein the distance between the active line area and the passive line area is larger than a first preset value, and the first preset value refers to the distance between an active line and a ground source line on the original metal layer of the chip.

Further defined, the chip circuit structure further comprises: at least two metal layers which are arranged in a laminated manner and a passivation layer which is arranged between two adjacent metal layers;

the metal layer comprises an active wire region and a passive wire region, the passivation layer comprises an active through hole and a passive through hole, the active wire region is electrically connected with the active through hole, and the passive wire region is electrically connected with the passive through hole;

the distance between the active through hole and the passive through hole is larger than a second preset value, wherein the second preset value refers to the distance between the active through hole and the passive through hole on the original passivation layer of the chip.

Further defined, the active line area is spaced apart from the passive line area;

the active hole area and the passive hole area are arranged at intervals.

Further defined, the chip circuit structure further comprises: a first region and a second region, wherein the first region is provided with one or more active line regions and one or more active hole regions, and the second region is provided with one or more inactive line regions and one or more inactive hole regions.

Further defined, the spacing between the active line region and the inactive line region adjacent thereto is 1.1-1.5 times the first preset value.

Further defined, the number of active line areas in the first area and/or the number of inactive line areas in the second area is determined based on a first preset value:

when the first preset value is less than 10um, the number of the active line areas in the first area and/or the number of the passive line areas in the second area are 1 group;

when the first preset value is more than or equal to 10um and less than 20um, the number of the active line areas in the first area and/or the number of the passive line areas in the second area are 2 groups;

when the first preset value is more than or equal to 20um, the number of the active line areas in the first area and/or the number of the passive line areas in the second area are 3 groups.

Further defined, the spacing between the active via and the passive via adjacent thereto is 1.1-1.5 times the second predetermined value.

Further defined, the number of active vias in the first region and/or the number of passive vias in the second region is determined based on a second preset value:

when the second preset value is less than 10um, the number of the active through holes in the first area and/or the number of the passive through holes in the second area are 1 group;

when the second preset value is more than or equal to 10um and less than 20um, the number of the active through holes in the first area and/or the number of the passive through holes in the second area are 2 groups;

when the second preset value is more than or equal to 20um, the number of the active through holes in the first area and/or the number of the passive through holes in the second area are 3 groups.

Further defined, the aperture of the active via in the first region and/or the aperture of the passive via in the second region is greater than a third preset value, which isRefers toWidth of active and passive vias on the original passivation layer of the chip.

Further defined, the number of active through holes in the first area and/or the number of passive through holes in the second area is greater than a fourth preset value, where the fourth preset value refers to the number of active through holes and passive through holes on the passivation layer of the chip.

Compared with the prior art, the utility model has the beneficial effects that:

1. the utility model relates to a chip circuit structure, which comprises a metal layer, wherein the metal layer comprises an active line area and a passive line area, and the distance between the active line area and the passive line area is larger than a first preset value; according to the utility model, the metal layer is divided into the regions, the distance between the active line region and the passive line region is increased, and the probability of short circuit between the active line region and the passive line region of different wafers in stacking is reduced, so that the chip failure problem caused by overlarge current in the test process is reduced.

2. The chip circuit structure comprises at least two metal layers which are arranged in a stacked manner and a passivation layer arranged between the adjacent two metal layers, wherein the passivation layer comprises an active through hole and a passive through hole, and the distance between the active through hole and the passive through hole is larger than a second preset value; according to the utility model, the metal layer and the passivation layer are arranged in a dividing way, the distance between the active line area and the passive line area and the distance between the active through hole and the passive through hole are increased, the probability that defects fall between the active line area and the passive line area and between the active through hole and the passive through hole is reduced, and then the probability that short circuits occur between the active line area and the passive line area and between the active through hole and the passive through hole of different wafers when chips are stacked is reduced, so that the chip failure problem caused by overlarge current in the testing process is reduced.

3. The active line area and the passive line area are arranged at intervals, and the active hole area and the passive hole area are arranged at intervals, so that the realization of the chip function is not affected, and the probability that a defect falls between the active line and the passive line can be reduced; and meanwhile, the distance between the active line area and the inactive line area is increased, even if a defect falls between the active line area and the inactive line area and between the active hole area and the inactive hole area, the risk of short circuit between the active line area and the inactive line area and between the active hole area and the inactive hole area is reduced.

4. The aperture of the active through holes and/or the number of the active through holes are increased, the aperture of the passive through holes and/or the number of the passive through holes are increased, and the open circuit problem caused by metal migration is reduced by a method of increasing the number and/or the width of the power line through holes, the signal line through holes and the passive through holes, so that the yield of products is effectively improved from a design end.

Drawings

FIG. 1 is a diagram of conventional active and ground source line distribution in the prior art;

FIG. 2 is a diagram of an active line and ground line distribution diagram I in embodiment 2 of the present application;

FIG. 3 is a second active line and ground line distribution diagram in embodiment 2 of the present application;

FIG. 4 is a diagram showing the distribution of active vias and power line channels in the prior art;

FIG. 5 is a diagram showing a first distribution of active via and power line channels in embodiment 3;

FIG. 6 is a second distribution diagram of active vias and power line channels in embodiment 3;

FIG. 7 is a prior art layout of a circuit path;

FIG. 8 is a first design drawing of the circuit channel in embodiment 4;

FIG. 9 is a second design drawing of the circuit channel in embodiment 4;

FIG. 10 is a schematic view of a two wafer stack;

FIG. 11 is a diagram showing wafer yield test results, wherein blue represents failed chips with excessive current resulting in short circuits, red represents functional failure of partial areas inside the chips, and green represents areas with good functions;

FIG. 12 is a diagram showing a wafer shorting problem; wherein VDD represents an active line and VSS represents a ground source line;

FIG. 13 is a diagram showing a wafer break problem;

wherein, 1-active wire, 2-ground source wire, 3-active through hole, 4-passive through hole, 5-metal layer, 6-passivation layer.

Detailed Description

The preferred embodiments of the present utility model will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present utility model only, and are not intended to limit the present utility model.

Referring to fig. 10, two logic wafers and memory wafers from different processes are respectively provided, and bonding of the metal of the wafer bottom layer, or bonding of the metal of the wafer bottom layer and bonding of the metal of the wafer bottom layer are performed in the middle through hybrid bonding (hybrid bonding or hybrid bonding); referring to fig. 11, the yield test results of chips formed by bonded wafers show that, due to the larger chip size, there are only 61 complete encapsulatable chips on each wafer above 30um, and ideally, the yield of chips should be 100%, i.e. the yield test results of the whole chip are all shown as area 9, but various factors that cause chip failure are encountered during the wafer processing, such as: in fig. 11, a dashed box represents a separation line between chips, and areas 8 and 7 represent functional failure of partial areas inside the chips, wherein a part of failure causes are from the problem of disconnection of a single channel of an underlying aluminum wafer due to stress factors, and refer to fig. 13 specifically; another part is from the problem of short circuit due to power and ground lines, see fig. 12. The failed chip as shown in region 8 and region 7 does not meet the criteria for continuing with the subsequent packaging, so it is very significant to reduce its duty cycle.

In the design of the present integrated circuit chip, as shown in fig. 1, especially for large chips with a size above 30um, in order to make the chip voltage distributed more uniformly over the whole chip, usually, in the layout and wiring of the metal layer 5, a design that the power line and the ground source line 2 are spaced is adopted, but for the whole chip, the power line is interconnected on the whole chip, so that the power line and the ground source line 2 are shorted easily due to defects randomly distributed on the wafer. Therefore, the method for optimizing the chip circuit layout from the design end can enhance the robustness of the product.

Example 1

The chip circuit structure of this embodiment includes a metal layer 5, where the metal layer 5 includes an active line area and a passive line area, and a distance between the active line area and the passive line area is greater than a first preset value. The active wire area is used for setting the active wire 1, the active wire 1 is a power wire and/or a signal wire, the passive wire area is used for setting the ground source wire 2, the distance between the active wire area and the passive wire area is increased, the probability of short circuit between the active wire area and the passive wire area of different wafers when stacking is reduced, and therefore the chip failure problem caused by overlarge current in the testing process is reduced. The first preset value refers to the interval between the active line 1 and the ground source line 2 on the original metal layer 5 of the chip.

Example 2

The chip circuit structure of the embodiment comprises at least two metal layers 5 which are arranged in a stacked manner, and a passivation layer 6 which is arranged between the adjacent two metal layers 5; the metal layer 5 comprises an active wire area and a passive wire area, the passivation layer 6 comprises an active through hole 3 and a passive through hole 4, the active wire area is electrically connected with the active through hole 3, and the passive wire area is electrically connected with the passive through hole 4; the distance between the active line area and the passive line area is larger than a first preset value, and the distance between the active via 3 and the passive via 4 is larger than a second preset value. The active wire area is used for arranging an active wire 1, the active wire 1 is a power wire and/or a signal wire, the passive wire area is used for arranging a ground source wire 2, the passive through hole 4 is used for penetrating the active wire 1, and the passive through hole 4 is used for penetrating the ground source wire 2; the second preset value refers to the spacing between the active vias 3 and the passive vias 4 on the original passivation layer 6 of the chip.

The number of the active line areas is divided into a plurality of (not less than 1), the number of the passive line areas is divided into a plurality of (not less than 1), and when the number of the active line areas and the number of the passive line areas are both more than 1, the active line areas and the passive line areas are arranged alternately. The probability of defects falling between the active line area and the inactive line area is reduced.

The active line area and the passive line area are arranged at intervals; the active hole area is spaced from the passive hole area.

In the chip stacking, the metal layers 5 and the passivation layers 6 are arranged at intervals, and two adjacent metal layers 5 are connected by passing through the power supply line and/or the signal line in the active through hole 3 on the passivation layer 6 and passing through the ground source line 2 in the passive through hole 4.

Referring to fig. 1, in the current chip circuit design, the metal layer 5 is spaced between the active line 1 and the ground line 2 during wiring, and the probability of defects falling on any area inside the wafer is equal because the defects fall on the positions on the wafer, so that the risk of short circuits between the active line 1 and the ground line 2 in the metal layer 5 is greatly increased by the current wiring scheme.

In the embodiment, the power line and the ground source line 2 are reasonably arranged in a partitioning manner, and the active through hole area in the original passivation layer 6 are arranged in a partitioning manner; the probability that the defects fall between the active wire 1 and the ground wire 2 and between the active through hole 3 and the passive through hole 4 are reduced, and the probability that the active wire 1 is short-circuited with the ground wire 2 and the active through hole 3 and the passive through hole 4 is reduced, so that the yield of the chip is improved.

Example 3

The chip circuit structure of the present embodiment, which is formed on the basis of embodiment 2, includes a first region and a second region, wherein the first region is provided with one or more active wire regions and one or more active hole regions, and the second region is provided with one or more inactive wire regions and one or more inactive hole regions.

The distance between the active line area and the adjacent passive line area is 1.1-1.5 times of the first preset value; specifically, the increase may be 1.1 times, 1.2 times, 1.3 times, 1.4 times or 1.5 times.

The number of active line areas in the first area and/or the number of inactive line areas in the second area are determined based on a first preset value:

referring to fig. 2, when the first preset value is less than 10um, the number of active line areas in the first region and the number of inactive line areas in the second region are 1 group, i.e., one each of the first region and the second region; 3 active wires 1 are arranged in the region, the 3 active wires 1 are arranged in parallel in the region, and the interval between two adjacent active wires 1 in the region is 2um; 3 ground source lines 2 are arranged in the area, the 3 ground source lines 2 are arranged in parallel in the area, and the interval between two adjacent ground source lines 2 in the area is 2um; the distance between the adjacent active line regions and the inactive line regions is 1.2 times the first preset value, and specifically, when the first preset value is 8um, the distance between the adjacent active line regions and the inactive line regions is 9.6um.

Referring to FIG. 3, when the first preset value is greater than or equal to 10um and less than 20um, the number of active line areas in the first area and the number of inactive line areas in the second area are 2 groups, namely, two active line areas and two inactive line areas in the first area are respectively arranged; 2 active wires 1 are arranged in the area, the 2 active wires 1 are arranged in parallel in the area, and the interval between two adjacent active wires 1 in the area is 3um; 2 ground source lines 2 are arranged in the area, the 2 ground source lines 2 are arranged in parallel in the area, and the interval between two adjacent ground source lines 2 in the area is 3um. The distance between the adjacent active line regions and the inactive line regions is 1.3 times the first preset value, and specifically, when the first preset value is 12um, the distance between the adjacent active line regions and the inactive line regions is 15.6um.

When the first preset value is more than or equal to 20um, the number of active line areas in the first area and the number of passive line areas in the second area are 3 groups, namely three first areas and three second areas are respectively; 2 active wires 1 are arranged in the area, the 2 active wires 1 are arranged in parallel in the area, and the interval between two adjacent active wires 1 in the area is 4um; 2 ground source lines 2 are arranged in the area, the 2 ground source lines 2 are arranged in parallel in the area, and the interval between two adjacent ground source lines 2 in the area is 4um. The distance between the adjacent active line regions and the inactive line regions is 1.5 times the first preset value, and specifically, when the first preset value is 20um, the distance between the adjacent active line regions and the inactive line regions is 30um.

The active line area and the passive line area are arranged at intervals, and meanwhile, the arrangement distance between the active line area and the passive line area is increased, so that the realization of the chip function is not affected, and the probability that a defect falls between the active line 1 and the passive line is reduced; even if the defect falls between the active line region and the inactive line region, the risk of the active line region and the inactive line region being shorted is reduced; the defects between the active wires 1 and the ground source wires 2 are accommodated in a larger space, the adjacent active wires 1 and the adjacent ground source wires 2 are not short-circuited, and the yield of the chip is improved.

Example 4

The chip circuit structure of the present embodiment, which is formed on the basis of embodiment 2, includes a first region and a second region, wherein the first region is provided with one or more active wire regions and one or more active hole regions, and the second region is provided with one or more inactive wire regions and one or more inactive hole regions.

The spacing between the active via 3 and the passive via 4 adjacent thereto is 1.1-1.5 times the second preset value. Specifically, the increase may be 1.1 times, 1.2 times, 1.3 times, 1.4 times or 1.5 times.

Wherein the number of active vias 3 in the first area and/or the number of passive vias 4 in the second area is determined based on a second preset value:

referring to fig. 4, the active vias 3 and the passive vias 4 in the passivation layer 6 are spaced apart, and defects around adjacent active vias 3 and passive vias 4 may cause short circuits between the active vias 3 and passive vias 4, reducing the yield of the chip.

Referring to fig. 5, when the second preset value is less than 10um, the number of active through holes 3 in the first area and the number of passive through holes 4 in the second area are 1 group, i.e. the first area and the second area are respectively provided with 6 active through holes 3, the 6 active through holes 3 are arranged in parallel in the area, and the interval between two adjacent active through holes 3 in the area is 2um; the area is provided with 6 passive through holes 4, the 6 passive through holes 4 are arranged in parallel in the area, and the interval between two adjacent passive through holes 4 in the area is 2um; the spacing between adjacent active and inactive via regions is 1.2 times the second preset value, specifically, when the second preset value is 8um, the spacing between adjacent active and inactive via regions is 9.6um.

Referring to fig. 6, when the second preset value is equal to or greater than 10um and less than 20um, the number of active through holes 3 in the first area and the number of passive through holes 4 in the second area are 2 groups, namely, the first area and the second area are respectively two, 3 active through holes 3 are arranged in the area, 3 active through holes 3 are arranged in parallel in the area, and the interval between two adjacent active through holes 3 in the area is 3um; 3 passive through holes 4 are arranged in the area, the 3 passive through holes 4 are arranged in parallel in the area, and the interval between two adjacent passive through holes 4 in the passive through hole area is 3um; the distance between adjacent active and inactive via regions is 1.3 times the second preset value, specifically, when the second preset value is 12um, the distance between adjacent active and inactive via regions is 15.6um.

When the second preset value is more than or equal to 20um, the number of the active through holes 3 in the first area and the number of the passive through holes 4 in the second area are 3 groups, namely, two active through holes 3 are arranged in the first area and the second area respectively, 2 active through holes 3 are arranged in parallel in the area, and the interval between two adjacent active through holes 3 in the area is 5um; 2 passive through holes 4 are arranged in the area, the 2 passive through holes 4 are arranged in parallel in the area, and the interval between every two adjacent passive through holes 4 in the area is 5um; the spacing between adjacent active and inactive via regions is 1.5 times the second preset value, specifically, when the second preset value is 20um, the spacing between adjacent active and inactive via regions is 30um.

The active through hole area and the passive through hole area are arranged at intervals, and meanwhile, the arrangement distance between the active through hole area and the passive through hole area is increased, so that the realization of the chip function is not affected, and the probability that defects fall between the active through hole 3 and the passive through hole 4 can be reduced; even if a defect falls between the active and inactive via regions, the risk of the active and inactive via regions being shorted is reduced. The defects between the active through holes 3 and the passive through holes 4 are contained in a larger space, the adjacent active through holes 3 and passive through holes 4 cannot be short-circuited, and the yield of chips is improved.

Example 5

The chip circuit structure of this embodiment is formed on the basis of embodiment 4; referring to fig. 7, currently, for the connection between adjacent metal layers 5, a single channel design is mostly adopted, and the metal migration is caused by the single channel due to the factors of the stress of the process, and the disconnection occurs between the active line 1 in the active through hole 3 and the ground source line 2 of the passive through hole 4, so that the chip fails.

The aperture of the active via 3 in the first region and/or the aperture of the passive via 4 in the second region is larger than a third preset value. The third preset value refers to the widths of the active through holes 3 and the passive through holes 4 on the passivation layer 6 of the chip.

The number of active vias 3 in the first area and/or the number of passive vias 4 in the second area is greater than a fourth preset value. The fourth preset value refers to the number of active through holes 3 and passive through holes 4 on the passivation layer 6 of the chip.

Referring to fig. 8 and 9, the aperture of the active via 3 is greater than a third preset value and/or the number of active vias 3 is greater than a fourth preset value; the aperture of the passive vias 4 is larger than a third preset value and/or the number of passive vias 4 is larger than a third preset value. The aperture of the active via 3 is increased, for example: increasing the aperture of the active through holes 3 to two active wires 1 corresponding to each active through hole 3; the number of active vias 3 is increased, for example: increasing the number of active vias 3 to 1.1 times or 1.2 times before, so that there are more active vias 3 to accommodate active wires 1; the aperture of the passive via 4 is increased, for example: increasing the aperture of the passive vias 4 to correspond to two ground source lines 2 within each passive via 4 increases the number of passive vias 4, for example: increasing the number of passive vias 4 to 1.1 times or 1.2 times before; the active via 3 includes a power line via/signal line via.

In this embodiment, by increasing the number and aperture of the power line through holes, the number and aperture of the signal line through holes, and the number and aperture of the passive through holes 4, the arrangement prevents the disconnection of one or more power line through holes, one or more signal line through holes, and one or more passive through holes 4, and other power line through holes, signal line through holes, and passive through holes 4 are not disconnected, thereby reducing the failure rate of the chip. The problem of open circuit caused by metal migration is reduced, so that the yield of the product is effectively improved from the design end.

Claims (10)

1. Chip circuit structure, its characterized in that, chip circuit structure includes:

the metal layer (5), metal layer (5) include active line district and passive line district, active line district with distance between the passive line district is greater than first default, first default is spacing between active line (1) and ground source line (2) on chip primitive metal layer (5), wherein, first default is < 10um, or first default is not less than 10um and < 20um, or first default is not less than 20um.

2. The chip circuit structure of claim 1, wherein the chip circuit structure further comprises: at least two metal layers (5) which are arranged in a stacked manner and a passivation layer (6) which is arranged between the adjacent two metal layers (5);

the metal layer (5) comprises an active wire region and a passive wire region, the passivation layer (6) comprises an active through hole (3) and a passive through hole (4), the active wire region is electrically connected with the active through hole (3), and the passive wire region is electrically connected with the passive through hole (4);

the distance between the active through hole (3) and the passive through hole (4) is larger than a second preset value, wherein the second preset value refers to the distance between the active through hole (3) and the passive through hole (4) on the original passivation layer (6) of the chip.

3. The chip circuit structure of claim 2 wherein said active line area is spaced apart from said passive line area;

the active hole area and the passive hole area are arranged at intervals.

4. The chip circuit structure of claim 3, wherein the chip circuit structure further comprises: a first region and a second region, wherein the first region is provided with one or more active line regions and one or more active hole regions, and the second region is provided with one or more inactive line regions and one or more inactive hole regions.

5. The chip circuit structure of claim 4, wherein a spacing between the active wire region and the inactive wire region adjacent thereto is 1.1-1.5 times a first predetermined value.

6. The chip circuit structure according to claim 5, wherein the number of active wire areas in the first area and/or the number of inactive wire areas in the second area is determined based on a first preset value:

when the first preset value is less than 10um, the number of the active line areas in the first area and/or the number of the passive line areas in the second area are 1 group;

when the first preset value is more than or equal to 10um and less than 20um, the number of the active line areas in the first area and/or the number of the passive line areas in the second area are 2 groups;

when the first preset value is more than or equal to 20um, the number of the active line areas in the first area and/or the number of the passive line areas in the second area are 3 groups.

7. Chip circuit structure according to claim 4, characterized in that the spacing between the active via (3) and the passive via (4) adjacent thereto is 1.1-1.5 times the second preset value.

8. Chip circuit configuration according to claim 7, characterized in that the number of active vias (3) in the first area and/or the number of passive vias (4) in the second area is determined based on a second preset value:

when the second preset value is less than 10um, the number of the active through holes (3) in the first area and/or the number of the passive through holes (4) in the second area are 1 group;

when the second preset value is more than or equal to 10um and less than 20um, the number of the active through holes (3) in the first area and/or the number of the passive through holes (4) in the second area are 2 groups;

when the second preset value is more than or equal to 20um, the number of the active through holes (3) in the first area and/or the number of the passive through holes (4) in the second area are 3 groups.

9. Chip circuit structure according to claim 8, characterized in that the aperture of the active via (3) in the first area and/or the aperture of the passive via (4) in the second area is larger than a third preset value, which is the width of the active via (3) and the passive via (4) on the passivation layer (6) of the chip origin.

10. Chip circuit structure according to claim 8, characterized in that the number of active vias (3) in the first area and/or the number of passive vias (4) in the second area is greater than a fourth preset value, which refers to the number of active vias (3) and passive vias (4) on the original passivation layer (6) of the chip.

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