CN219107298U - Boost circuit capable of effectively improving boost efficiency - Google Patents
Boost circuit capable of effectively improving boost efficiency Download PDFInfo
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- CN219107298U CN219107298U CN202320123711.2U CN202320123711U CN219107298U CN 219107298 U CN219107298 U CN 219107298U CN 202320123711 U CN202320123711 U CN 202320123711U CN 219107298 U CN219107298 U CN 219107298U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The utility model relates to a boost circuit for effectively improving boost efficiency, which comprises a chip U1 and an ideal diode U2, wherein the inside of the ideal diode U2 comprises a MOSFET (metal-oxide-semiconductor field-effect transistor), a charge pump, a gate amplifier and a fast pull-down comparator. The booster circuit reduces the electric energy loss, simultaneously reduces the heating of the circuit, can effectively improve the efficiency, and can reduce the layout space in the practical circuit application.
Description
Technical Field
The application belongs to the technical field of booster circuits, and more particularly relates to a booster circuit capable of effectively improving boosting efficiency.
Background
At present, as shown in fig. 1, when 12V is input, a 5 th pin of a boost chip U1 outputs a signal to perform switch control on a MOS transistor Q1, when Q1 is turned on, an inductor L1 is charged for energy storage, and when Q1 is turned off, since current cannot be suddenly changed through the upper surface of the inductor L1, the current flows to a load through a schottky diode D1; the output voltage is divided by the resistors R3 and R7 to obtain a sampling voltage to the FB pin, and the sampling voltage is compared with the reference voltage Vref; the boost chip U1 can control the on-off time of the Q1 by adjusting the pulse width output by the 5 th pin, namely control the charging current of the inductor L1, so that a stable voltage can be output. It can be found that a certain loss occurs through the common schottky diode D1 (when the current reaches 1A, there is a voltage drop of about 1.3V), and meanwhile, the circuit heats up, which is unacceptable.
Disclosure of Invention
The utility model aims to provide a boosting circuit capable of effectively improving boosting efficiency and avoiding loss.
In order to solve the problems, the utility model adopts the following technical scheme:
the booster circuit comprises a chip U1 and an ideal diode U2, wherein an input signal Vin is connected with a 1 pin of a resistor R1, and a 2 pin of the resistor R1 is respectively connected with an electrolytic capacitor E2, a capacitor C3, a 3 pin of the chip U1 and an inductor L1; the 2 pin of the chip U1 is connected with the GND pin through the capacitor C2, the 4 pin of the chip U1 is connected with the GND pin through the resistor R5, the 8 pin of the chip U1 is connected with the capacitor C1, the other end of the capacitor C1 is respectively connected with the 6 pin and the GND pin of the chip U1, the 7 pin of the chip U1 is respectively connected with the capacitor C7 and the resistor R8, and the other end of the electrolytic capacitor E2, the other end of the capacitor C3, the other end of the capacitor C7 and the other end of the resistor R8 are respectively connected with the GND pin; the 5 pin of the chip U1 is connected with the 1 pin of the MOS tube Q1 through a resistor R6, and the 2 pin of the MOS tube Q1 is connected with the GND pin and the 3 pin of the MOS tube Q1 is connected with the other end of the inductor L1;
the other end of the inductor L1 is connected with a plurality of IN pins of an ideal diode U2, 7 pins of the ideal diode U2 are connected with GND pins, the OUT pin and the DRAIN pin of the ideal diode U2 are connected with a terminal T through a resistor R2, the VDD pin of the ideal diode U2 is respectively connected with a resistor R4 and a capacitor C6, and the other end of the resistor R4 is connected with the DRAIN pin; the DRAIN pin of the ideal diode U2 is also connected with a resistor R3 and a resistor R7 in series in sequence, and the pin 1 of the chip U1 is connected between the resistor R3 and the resistor R7; the other end of the capacitor C6 and the other end of the resistor R7 are connected with the GND pin.
Further, the ideal diode U2 is LTC4358CDE.
Further, an electrolytic capacitor E1, a capacitor C4 and a capacitor C5 are connected in parallel between the DRAIN pin and the GND pin of the ideal diode U2.
Further, the number of IN pins of the ideal diode U2 is 8, and 1 to 4 pins and 11 to 14 pins of the ideal diode U2 are respectively.
Further, the ideal diode U2 includes an N-channel MOSFET, a Charge Pump, a gate amplifier gate amp, and a fast pull-down comparator FPD COMP, where the Charge Pump is connected to the positive post-output of the gate amplifier gate amp as an IN pin, the negative pole of the gate amplifier gate amp is connected to the positive pole of the fast pull-down comparator FPD COMP on the one hand, and is connected to the OUT pin on the other hand, and the negative pole of the fast pull-down comparator FPD COMP is connected to the IN pin; the output end of the fast pull-down comparator FPD COMP is connected with the base electrode of the diode, the emitter electrode of the diode is connected with the IN pin, the IN pin is connected with the source electrode of the MOSFET tube, the collector electrode of the diode is connected with the output end of the GATE amplifier GATE amp, the output end of the GATE amplifier GATE amp is connected with the grid electrode of the MOSFET tube on the one hand and is used as a GATE pin on the other hand, the two ends of the GATE pin are respectively led OUT of a DRAIN pin and an OUT pin, the DRAIN pin is respectively connected with the DRAIN electrode of the MOSFET tube, the GATE pin is connected with the OUT pin, the OUT pin is led OUT of the VDD pin, the VDD pin is connected with the GND pin, and the GND pin is connected with the IN pin.
Further, when the current reaches 5A, the loss internal resistance is 20 mOhm
Due to the adoption of the technical scheme, the beneficial effects obtained by the utility model are as follows:
when the current of the common Schottky diode is 1A, about 1.3V of loss exists; the booster circuit adopting the ideal diode has only 20 milliohms of internal resistance when the current is 5A, and the internal resistance is compared with the internal resistance, so that the loss is much smaller.
Drawings
Fig. 1 is a conventional boost circuit diagram.
Fig. 2 is a diagram of a boost circuit employing an ideal diode.
Fig. 3 is an internal block diagram of an ideal diode.
Detailed Description
The present utility model will be described in further detail with reference to examples.
The booster circuit comprises a chip U1 and an ideal diode U2, wherein an input signal Vin is connected with a 1 pin of a resistor R1, and a 2 pin of the resistor R1 is respectively connected with an electrolytic capacitor E2, a capacitor C3, a 3 pin of the chip U1 and an inductor L1; the 2 pin of the chip U1 is connected with the GND pin through the capacitor C2, the 4 pin of the chip U1 is connected with the GND pin through the resistor R5, the 8 pin of the chip U1 is connected with the capacitor C1, the other end of the capacitor C1 is respectively connected with the 6 pin and the GND pin of the chip U1, the 7 pin of the chip U1 is respectively connected with the capacitor C7 and the resistor R8, and the other end of the electrolytic capacitor E2, the other end of the capacitor C3, the other end of the capacitor C7 and the other end of the resistor R8 are respectively connected with the GND pin; the 5 pin of the chip U1 is connected with the 1 pin of the MOS tube Q1 through a resistor R6, and the 2 pin of the MOS tube Q1 is connected with the GND pin and the 3 pin of the MOS tube Q1 is connected with the other end of the inductor L1;
the other end of the inductor L1 is connected with a plurality of IN pins of an ideal diode U2, 7 pins of the ideal diode U2 are connected with GND pins, the OUT pin and the DRAIN pin of the ideal diode U2 are connected with a terminal T through a resistor R2, the VDD pin of the ideal diode U2 is respectively connected with a resistor R4 and a capacitor C6, and the other end of the resistor R4 is connected with the DRAIN pin; the DRAIN pin of the ideal diode U2 is also connected with a resistor R3 and a resistor R7 in series in sequence, and the pin 1 of the chip U1 is connected between the resistor R3 and the resistor R7; the other end of the capacitor C6 and the other end of the resistor R7 are connected with the GND pin.
In fig. 2, the ideal diode U2 model is LTC4358CDE. An electrolytic capacitor E1, a capacitor C4 and a capacitor C5 are connected in parallel between the DRAIN pin and the GND pin of the ideal diode U2. The number of the IN pins of the ideal diode U2 is 8, and the IN pins of the ideal diode U2 are respectively 1 to 4 pins and 11 to 14 pins.
As shown IN fig. 3, the ideal diode U2 includes a MOSFET (N-channel MOSFET), a Charge Pump, a gate amplifier gate amp, and a fast pull-down comparator FPD COMP, wherein the positive post-output of the Charge Pump is an IN pin, the negative pole of the gate amplifier gate amp is connected to the positive pole of the fast pull-down comparator FPD COMP, the output thereof is an OUT pin, and the negative pole of the fast pull-down comparator FPD COMP is connected to the IN pin; the output end of the fast pull-down comparator FPD COMP is connected with the base electrode of the diode, the emitter electrode of the diode is connected with the IN pin, the IN pin is connected with the source electrode of the MOSFET tube, the collector electrode of the diode is connected with the output end of the GATE amplifier GATE amp, the output end of the GATE amplifier GATE amp is connected with the grid electrode of the MOSFET tube on the one hand and is used as a GATE pin on the other hand, the two ends of the GATE pin are respectively led OUT of a DRAIN pin and an OUT pin, the DRAIN pin is respectively connected with the DRAIN electrode of the MOSFET tube, the GATE pin is connected with the OUT pin, the OUT pin is led OUT of the VDD pin, the VDD pin is connected with the GND pin, and the GND pin is connected with the IN pin.
The booster circuit has good performance, and when the current reaches 5A, the loss internal resistance is 20 milliohms
First, an ideal diode, which is an electrical component, behaves like an ideal conductor when a voltage is applied in a forward bias, and behaves like an ideal insulator when a voltage is applied in a reverse bias, is described. Thus, when a +ve voltage is applied across the anode to the cathode, the diode immediately performs forward current.
The model of the ideal diode U2 is LTC4358CDE, and the LTC4358CDE has the following advantages:
1) A power schottky diode can be replaced;
2) An internal 20mΩ, N-channel MOSFET;
3) An off time of 0.5 mus to limit peak fault current;
4) Operating voltage range: 9V to 26.5V;
5) Smooth switching without oscillation is realized;
6) No reverse DC current;
7) A 14 pin (4 mm x 3 mm) DFN and a 16 pin TSSOP package were used.
IN the circuit, the inside of an ideal diode is mainly used for replacing a common Schottky diode by driving an N-channel MOSFET, and an IN pin and a DRAIN pin form an anode and a cathode of the ideal diode; VDD is the power supply of LTC4358, when powered on, the load current will flow through the body diode of the internal MOSFET, the MOSFET will be turned on gradually, the amplifier will drop the IN and OUT pins to 25mV, if the load current causes a drop of more than 25mV, the MOSFET will be turned on completely, the dropped voltage will be: RDS (on). ILOAD; if the load current decreases causing the forward voltage to drop below 25mV, the internal MOSFET maintains the drop at 25mV by weak pull-down; if the load current is reversed, the MOSFET is turned off by a strong pull-down.
In the event of a power failure, reverse current will temporarily flow through the open LTC4358 ideal diode, which will turn off within 500ns, preventing reverse current from damaging other components and minimizing disturbances on the output.
Claims (6)
1. The utility model provides an effectively improve boost circuit of boost efficiency which characterized in that: the device comprises a chip U1 and an ideal diode U2, wherein an input signal Vin is connected with a 1 pin of a resistor R1, and a 2 pin of the resistor R1 is respectively connected with an electrolytic capacitor E2, a capacitor C3, a 3 pin of the chip U1 and an inductor L1; the 2 pin of the chip U1 is connected with the GND pin through the capacitor C2, the 4 pin of the chip U1 is connected with the GND pin through the resistor R5, the 8 pin of the chip U1 is connected with the capacitor C1, the other end of the capacitor C1 is respectively connected with the 6 pin and the GND pin of the chip U1, the 7 pin of the chip U1 is respectively connected with the capacitor C7 and the resistor R8, and the other end of the electrolytic capacitor E2, the other end of the capacitor C3, the other end of the capacitor C7 and the other end of the resistor R8 are respectively connected with the GND pin; the 5 pin of the chip U1 is connected with the 1 pin of the MOS tube Q1 through a resistor R6, and the 2 pin of the MOS tube Q1 is connected with the GND pin and the 3 pin of the MOS tube Q1 is connected with the other end of the inductor L1;
the other end of the inductor L1 is connected with a plurality of IN pins of an ideal diode U2, 7 pins of the ideal diode U2 are connected with GND pins, the OUT pin and the DRAIN pin of the ideal diode U2 are connected with a terminal T through a resistor R2, the VDD pin of the ideal diode U2 is respectively connected with a resistor R4 and a capacitor C6, and the other end of the resistor R4 is connected with the DRAIN pin; the DRAIN pin of the ideal diode U2 is also connected with a resistor R3 and a resistor R7 in series in sequence, and the pin 1 of the chip U1 is connected between the resistor R3 and the resistor R7; the other end of the capacitor C6 and the other end of the resistor R7 are connected with the GND pin.
2. The boost circuit of claim 1, wherein the boost circuit is effective to increase boost efficiency, wherein: the ideal diode U2 is LTC4358CDE.
3. The boost circuit of claim 2, wherein the boost circuit is effective to increase boost efficiency, wherein: an electrolytic capacitor E1, a capacitor C4 and a capacitor C5 are connected in parallel between the DRAIN pin and the GND pin of the ideal diode U2.
4. The boost circuit of claim 2, wherein the boost circuit is effective to increase boost efficiency, wherein: the number of the IN pins of the ideal diode U2 is 8, and the IN pins of the ideal diode U2 are respectively 1 to 4 pins and 11 to 14 pins.
5. A boost circuit effective for enhancing boost efficiency according to any one of claims 1-4, wherein: the ideal diode U2 comprises a MOSFET (metal-oxide-semiconductor field effect transistor) tube, a charge pump, a gate amplifier and a quick pull-down comparator, wherein the charge pump is connected with the positive pole of the gate amplifier and then outputs as an IN pin, the negative pole of the gate amplifier is connected with the positive pole of the quick pull-down comparator, the output of the gate amplifier is connected with the OUT pin, and the negative pole of the quick pull-down comparator is connected with the IN pin; the output end of the fast pull-down comparator is connected with the base electrode of the diode, the emitter electrode of the diode is connected with the IN pin, the IN pin is connected with the source electrode of the MOSFET, the collector electrode of the diode is connected with the output end of the GATE amplifier, the output end of the GATE amplifier is connected with the grid electrode of the MOSFET on the one hand, and is used as a GATE pin on the other hand, the two ends of the GATE pin are respectively led OUT of the DRAIN pin and the OUT pin, the DRAIN pin is respectively connected with the IN pin and the DRAIN electrode of the MOSFET, the GATE pin is connected with the OUT pin, the OUT pin is led OUT of the VDD pin, and the VDD pin is connected with the GND pin.
6. The boost circuit of claim 5, wherein the boost circuit is effective to increase boost efficiency, wherein: when the current reaches 5A, the internal resistance of the loss is 20 milliohms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320123711.2U CN219107298U (en) | 2023-01-12 | 2023-01-12 | Boost circuit capable of effectively improving boost efficiency |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320123711.2U CN219107298U (en) | 2023-01-12 | 2023-01-12 | Boost circuit capable of effectively improving boost efficiency |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219107298U true CN219107298U (en) | 2023-05-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320123711.2U Active CN219107298U (en) | 2023-01-12 | 2023-01-12 | Boost circuit capable of effectively improving boost efficiency |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219107298U (en) |
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2023
- 2023-01-12 CN CN202320123711.2U patent/CN219107298U/en active Active
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