CN219085982U - Insulated gate bipolar transistor, power electronic device and power vehicle - Google Patents

Abstract

The utility model discloses an insulated gate bipolar transistor, power electronic equipment and a power vehicle, wherein the insulated gate bipolar transistor comprises: the device comprises a main body region, a drift region and an N-type FS region; an emitter and a grid are arranged above the main body region; a P-type collector region is arranged below the N-type FS region, and a collector electrode is arranged below the P-type collector region; a gate pad is disposed above the gate region, a p+ well region is disposed below the gate pad, and a hole bypass for transporting hole current is disposed in the p+ well region. By arranging the hole current path, the utility model realizes lower hole current density of active units around the grid electrode bonding pad.

Description

Insulated gate bipolar transistor, power electronic device and power vehicle

Technical Field

The present utility model relates to the field of semiconductors, and in particular to an insulated gate bipolar transistor, power electronics, and a power vehicle.

Background

The insulated gate bipolar transistor IGBT (Insulated Gate Bipolar Transistor) is the most widely used power device in power electronics applications such as household appliances, industry, renewable energy sources, UPS, railways, motor drives, and EV and HEV applications, and has a very high current handling capability in its structure, on the order of hundreds of amps, with a blocking voltage of 6500V due to the presence of the bipolar transistor. These IGBTs can control loads of hundreds of kilowatts, and are suitable for many applications. The IGBT is particularly suitable for duty cycle, low frequency, high voltage and load variations, enabling it to be used in locomotive trains, electric vehicles and hybrid electric vehicles. Applications of IGBTs in Electric Vehicles (EVs) and Hybrid Electric Vehicles (HEVs) include their use in drivetrains and chargers for delivering and controlling electrical power to electric machines. The IGBT market for EV/HEVs is expected to increase by a factor of two over the prediction period, accounting for more than 50% of the total market.

However, IGBTs have an inherent disadvantage, such as that Vce (sat) increases rapidly with increasing blocking voltage, and thus the IEGT concept was developed to reduce the on-state voltage drop. The trench gate power device reduces channel resistance and eliminates JFET effects and can reduce on-state voltage drop. Furthermore, the IEGT (injection enhanced IGBT) concept increases the stored carriers on the upper side of the n drift region by using a floating p-region between trench gate cells, thus significantly reducing Vce (sat) for relatively high voltage IGBTs.

These power devices applied to hybrid vehicles and electric vehicles are forced to frequently face severe environments, and it is very useful to analyze failure mechanisms and innovate main measures for failure and destruction according to the failure mechanisms from the viewpoint of device failure and protection. One of the most important damage phenomena is damage under short circuit conditions in inverter applications. In general, it can be said that the most severe condition for the destructiveness is under high power switching. The IGBT structure must be able to operate over the entire area covering these tracks without damaging failure. In the course of the IGBT structure being subjected to both high currents and voltages, a phenomenon known as avalanche induced secondary breakdown occurs, resulting in destructive failure. This phenomenon can be triggered during both the on-transient and the off-transient. During an on transient, the Forward Biased Safe Operating Area (FBSOA) is said to be limited. During a shutdown transient, the Reverse Bias Safe Operating Area (RBSOA) is said to be limited. Very severe stresses, including FBSOA and RBSOA, occur under short circuit conditions, and the failure mechanism of the short circuit operation can be considered to be divided into four modes.

Mode a is a breakdown that occurs within a few microseconds after conduction due to the parasitic bipolar transistor turning on when the collector current is large. Mode B is thermal damage caused by excessive power consumption. Mode C is the disruption observed during shutdown, and shortly before Ic reaches zero current level, dic/dt is increasing and a higher peak voltage occurs. If the Rg off resistance is reduced to a very small value and the parasitic inductance is large, dynamic avalanche can occur, which is a destructive event due to current filarization, and SSCM (switched self-clamping mode) can occur, clamping the peak voltage to the breakdown voltage. Mode D is a failure observed on the order of hundreds of microseconds after shutdown, which may be described as thermal runaway caused by a large leakage current.

Hole current flows into the emitter electrode through the p-region under the n+ emitter of length ln+ and a voltage drop (ip×rp) is generated. When the voltage drop exceeds the built-in voltage, the parasitic thyristor n+/p/n-/p may be activated. Therefore, how to effectively reduce the hole current density is a technical problem to be solved.

Disclosure of Invention

In view of this, the present utility model aims to provide an insulated gate bipolar transistor IGBT, a power electronic device, and a power vehicle capable of preventing current concentration.

Specifically, the present utility model provides an insulated gate bipolar transistor capable of preventing current concentration, the insulated gate bipolar transistor IGBT comprising: a body region, a drift region, and an N-type FS (Field Stop) region; an emitter and a grid are arranged above the main body region; a P-type collector region is arranged below the N-type FS region, and a collector electrode is arranged below the P-type collector region; a gate pad is disposed above the gate region, a p+ well region is disposed below the gate pad, and a hole bypass for transporting hole current is disposed in the p+ well region.

Further, the aperture bypasses the gate region.

Further, the number of the hole bypasses is a plurality, and the hole bypasses are symmetrically distributed below the grid electrode bonding pad.

Further, the insulated gate bipolar transistor is an injection enhanced IGBT.

The utility model also provides power electronic equipment comprising the insulated gate bipolar transistor.

Further, the power electronics device comprises a current transformer.

The utility model also provides a power vehicle comprising the insulated gate bipolar transistor.

Further, the power vehicle comprises a locomotive train, an electric vehicle or a hybrid electric vehicle.

According to the IGBT with the short circuit tolerance improving capability, through the cross-sectional layout and the carrier streamline around the aluminum gate pad IGBT, hole carriers directly enter the emitter through the p+ well with high doping concentration, so that larger current density can flow into the non-active region, and the effect that the hole current path causes lower hole current density entering the active unit around the gate pad is achieved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description, serve to explain the principles of the utility model. In the drawings, like reference numerals are used to identify like elements. The drawings, which are included in the description, illustrate some, but not all embodiments of the utility model. Other figures can be derived from these figures by one of ordinary skill in the art without undue effort.

FIG. 1 is a schematic diagram of electric field and current distribution non-uniformity in an IGBT chip in different local areas provided by an embodiment of the utility model;

fig. 2 is a schematic structural diagram of a conventional insulated gate bipolar transistor;

fig. 3 is a schematic structural diagram of an insulated gate bipolar transistor capable of preventing current concentration according to an embodiment of the present utility model.

Detailed Description

The exemplary embodiments of the present utility model will now be described with reference to the accompanying drawings, however, the present utility model may be embodied in many different forms and is not limited to the examples described herein, which are provided to fully and completely disclose the present utility model and fully convey the scope of the utility model to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the accompanying drawings is not intended to be limiting of the utility model. In the drawings, like elements/components are referred to by like reference numerals.

Unless otherwise indicated, terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. In addition, it will be understood that terms defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

The inventor of the application finds out through experimental tests and theoretical analysis that a plurality of fault points in a chip are caused by nonuniform electric fields and currents, wherein higher electric fields are concentrated at the bottom of a trench gate and four corners of the chip. Higher current densities concentrate around the gate pad and gate runner with higher lattice temperatures below the emitter pad region. As shown in particular in fig. 1, the circle No.1 indicates the point between the edge termination and the active cell region, no.2 indicates the point around the emitter pad region, no.3 indicates the point along the gate runner, and No.4 indicates the spot pad region around the gate.

Embodiments of the present utility model avoid the problem of hole current concentration around the cell caused by the structure under the conventional IGBT gate pad as shown in fig. 2, by-pass of the holes added in the p + well region under the gate pad. As shown in fig. 3, as an embodiment of an IGBT with improved short circuit resistance of the present utility model, the IGBT with improved short circuit resistance includes: the device comprises a main body region, a drift region and an N-type FS region; an emitter and a grid are arranged above the main body region; a P-type collector region is arranged below the N-type FS region, and a collector electrode is arranged below the P-type collector region; a gate pad is disposed above the gate region, a p+ well region is disposed below the gate pad, and a hole bypass for transporting hole current is disposed in the p+ well region.

Preferably, the aperture bypasses the gate region.

Further preferably, the number of the hole bypasses is a plurality, and the plurality of the hole bypasses are symmetrically distributed below the gate pad.

The embodiment has the IGBT capable of improving the short circuit tolerance, and hole carriers directly enter the emitter through the p+ well with high doping concentration through the cross-section layout and the carrier streamline around the aluminum gate pad IGBT, so that larger current density can flow into the non-active area, and the effect that the hole current path causes lower hole current density entering the active unit around the gate pad is achieved.

The application also provides power electronic equipment comprising the insulated gate bipolar transistor. In particular, the power electronics device may comprise a current transformer.

The application also provides a power vehicle comprising the insulated gate bipolar transistor. Specifically, the power vehicle comprises a locomotive train, an electric vehicle or a hybrid electric vehicle.

The power electronics and the power vehicle include the technical effects of the insulated gate bipolar transistor described above that enable hole carriers to be injected from the extra p+ region into the space charge region during a short turn-off transient, thereby compensating for the effective net charge density in the space charge to eliminate peak electric fields. Eventually, dynamic avalanche leading to a current filament can be avoided. The injected carriers can be rapidly removed through the additional n+ region, thereby shortening the turn-off time.

The utility model has been described with reference to a few embodiments. However, as is well known to those skilled in the art, other embodiments than the above disclosed utility model are equally possible within the scope of the utility model, as defined by the appended patent claims.

Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise therein. All references to "a/an/the [ means, component, etc. ]" are to be interpreted openly as referring to at least one instance of said means, component, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated.

Claims (8)

1. An insulated gate bipolar transistor capable of preventing current concentration, the insulated gate bipolar transistor comprising: the device comprises a main body region, a drift region and an N-type FS region;

an emitter and a grid are arranged above the main body region; a P-type collector region is arranged below the N-type FS region, and a collector electrode is arranged below the P-type collector region;

a gate pad is disposed above the gate region, a p+ well region is disposed below the gate pad, and a hole bypass for transporting hole current is disposed in the p+ well region.

2. The insulated gate bipolar transistor capable of preventing current concentration according to claim 1, wherein said aperture bypasses said gate region.

3. The insulated gate bipolar transistor capable of preventing current concentration according to claim 2, wherein the number of the via bypasses is plural, and the via bypasses are symmetrically distributed under the gate pad.

4. An insulated gate bipolar transistor capable of preventing current concentration according to any one of claims 1 to 3, wherein said insulated gate bipolar transistor is an injection enhanced insulated gate bipolar transistor.

5. A power electronic device comprising an insulated gate bipolar transistor capable of preventing current concentration according to any one of claims 1 to 4.

6. The power electronic device of claim 5, wherein the power electronic device comprises a current transformer.

7. A power vehicle comprising an insulated gate bipolar transistor capable of preventing current concentration according to any one of claims 1 to 4.

8. The power car of claim 7, wherein the power car comprises a locomotive train, an electric car, or a hybrid electric car.

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