CN218937168U - Distributed weapon damage tester capable of being stored in real time - Google Patents

Abstract

The utility model discloses a distributed weapon damage tester capable of being stored in real time, which comprises an FPGA data acquisition circuit and an ARM core board connected with the FPGA data acquisition circuit; the FPGA data acquisition circuit comprises an ADC (analog-to-digital converter) for receiving acquired data and a first DDR (double data rate) for caching the data; the ARM core board comprises a second DDR used for caching data and an eMMC used for storing the data; the output end of the ADC is connected with a first DDR, the first DDR is electrically connected with a second DDR, and the second DDR is electrically connected with the eMMC. The data is completely stored in the eMMC in a multi-level cache mode, so that the real-time storage of the distributed weapon damage tester is realized, and the reliability of data storage is improved.

Description

Distributed weapon damage tester capable of being stored in real time

Technical Field

The utility model relates to a distributed weapon damage tester, in particular to a distributed weapon damage tester capable of being stored in real time.

Background

The weapon damage effect test has the requirements of multiple kinds of tested signals, wide test point distribution, multiple test point channels, high synchronism requirement, high reliability requirement and the like. Meanwhile, the method also has the adverse factors of severe test environment, huge destructive performance, irreversible test process, high test instantaneity requirement and the like. The existing weapon damage effect tester is mainly divided into a centralized tester and a distributed tester. The centralized tester is large in volume, the outgoing lines are connected to different measuring points to store the damage measurement data in real time, but the outgoing lines are too long and have the risk of being broken or damaged, so that the measuring range is limited; the distributed tester is small in size, each measuring point is directly provided with one distributed tester, wiring is not needed, transient signals can be stored, but due to the limitation of volume and power consumption, real-time storage cannot be realized, data can be stored only when trigger conditions are met, and once false triggering occurs, key data cannot be recorded, so that data loss and test failure are caused. Therefore, how to improve the data storage reliability and real-time performance of the distributed weapon damage tester under the condition of meeting the volume and power consumption limitations is a problem to be solved.

Disclosure of Invention

The utility model provides a real-time storage distributed weapon damage tester, which improves the reliability of data storage under the miniaturization and low power consumption limitation of the distributed weapon damage tester, and is realized by the following technical scheme:

a distributed weapon damage tester capable of being stored in real time comprises an FPGA data acquisition circuit and an ARM core board connected with the FPGA data acquisition circuit; the FPGA data acquisition circuit comprises an ADC (analog-to-digital converter) for receiving acquired data and a first DDR (double data rate) for caching the data; the ARM core board comprises a second DDR used for caching data and an eMMC used for storing the data; the output end of the ADC is connected with a first DDR, the first DDR is electrically connected with a second DDR, and the second DDR is electrically connected with the eMMC.

In the existing distributed weapon damage tester, an ADC is directly controlled by an ARM core board, data enters the ARM core board through the ADC, the ARM core board stores the data into an eMMC, the eMMC has non-uniform blocking stagnation when storing the data, and because the ADC outputs standard clock data, when the eMMC is blocked, the data input by the ADC cannot be stored completely, and data loss occurs; because of the severe requirements for volume and power consumption of the distributed weapon damage tester applied to extremely severe test environments, only the reliability of a part of data can be selected in the past when measuring in a large range. Because the unit performance power consumption reduction is realized by the FPGA, the ARM core board and the DDR, the utility model realizes the real-time storage of the distributed weapon damage tester by additionally arranging the FPGA data acquisition circuit in the distributed weapon damage tester, controlling the ADC to receive data by the FPGA data acquisition circuit and carrying out primary high-capacity cache by the DDR, and additionally arranging the DDR in the ARM core board to carry out secondary high-capacity cache, and completely storing the data in the eMMC in a multi-level cache way, thereby realizing the real-time storage of the distributed weapon damage tester and improving the reliability of data storage.

Based on the scheme, the method further comprises the following steps: the distributed weapon damage tester further comprises a plurality of modularized conditioning circuits, wherein the output end of each modularized conditioning circuit is connected with an ADC (analog-to-digital converter) on the FPGA data acquisition circuit, and the input end of each modularized conditioning circuit is respectively connected with a sensor driving circuit.

Based on the scheme, the method further comprises the following steps: the sensor driving circuit includes: ICP measurement circuit, thermocouple temperature measurement circuit and strain measurement circuit. Because the test is carried out in the face of various signals to be tested, various different sensors need to be prepared, the test equipment sensors of a plurality of manufacturers are matched with the test equipment sensors, the equipment data formats of different manufacturers are mutually incompatible, and the data after the test are difficult to uniformly analyze and store and manage, so that the data are converted into uniform standard voltage signals through a modularized conditioning circuit and then are input to an FPGA data acquisition circuit.

Based on the scheme, the method further comprises the following steps: the first DDR is DDR2.

Based on the scheme, the method further comprises the following steps: the second DDR is DDR3L.

Based on the scheme, the method further comprises the following steps: the FPGA data acquisition circuit transmits data to the ARM core board through a QSPI interface. Since the QSPI interface uses a data queue with pointers and has a wrap-around mode, allowing continuous transfer of data to/from the queue without the need for a CPU, the peripheral acts as a memory mapped parallel device for the CPU; the transmission queue containing up to 16 8-bit or 16-bit data can be transmitted at one time, once transmission is started, CPU intervention is not needed until transmission is finished, transmission efficiency is greatly improved, and integrity of data transmission between two stages of DDR (double data rate) of the cross plate is guaranteed.

Based on the scheme, the method further comprises the following steps: the ARM core board is a double core board. One CPU is dedicated to the open source operating system and the other CPU is dedicated to real-time and low power task processing.

Based on the scheme, the method further comprises the following steps: the ARM core board adopts a mixed ARM Cortex-A7 core and Cortex-M4 core framework. The Cortex-A7 kernel is special for an open source operating system and is used for taking out and storing the data in the second DDR frame by frame into the eMMC; the Cortex-M4 kernel is special for real-time and low-power task processing.

Based on the scheme, the method further comprises the following steps: the low-pass filter module is arranged on the FPGA data acquisition circuit, and signals output by the modularized conditioning circuit are subjected to anti-aliasing filtering through the low-pass filter module and then are sent to the ADC for analog-to-digital conversion.

Based on the scheme, the method further comprises the following steps: and a zero calibration module is further connected between the modularized conditioning circuit and the low-pass filtering module, the zero calibration module is arranged on the FPGA data acquisition circuit, and signals output by the modularized conditioning circuit are fed into the low-pass filtering module for anti-aliasing filtering after offset of all channels are removed through the zero calibration module.

Compared with the prior art, the utility model has the following advantages and beneficial effects:

according to the utility model, the FPGA data acquisition circuit is additionally arranged in the distributed weapon damage tester, the FPGA data acquisition circuit controls the ADC to receive data and perform primary high-capacity cache through the DDR, then the DDR is additionally arranged in the ARM core board to perform secondary high-capacity cache, and the data is completely stored in the eMMC in a multi-stage cache manner, so that the real-time storage of the distributed weapon damage tester is realized, and the reliability of data storage is improved.

The utility model converts the data of the ICP measuring circuit, the thermocouple temperature measuring circuit and the strain measuring circuit into uniform standard voltage signals through the modularized conditioning circuit, and then inputs the uniform standard voltage signals to the FPGA data acquisition circuit, and unifies the data formats of a plurality of different sensor devices which are incompatible by different manufacturers, thereby being convenient for analysis and storage management.

Drawings

In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present utility model, the drawings that are needed in the examples will be briefly described below, it being understood that the following drawings only illustrate some examples of the present utility model and therefore should not be considered as limiting the scope, and that other related drawings may be obtained from these drawings without inventive effort for a person skilled in the art. In the drawings:

fig. 1 is a schematic structural view of embodiment 1;

fig. 2 is a schematic structural diagram of embodiment 2.

In the drawings, the reference numerals and corresponding part names: the temperature sensor comprises a 01-FPGA data acquisition circuit, a 02-ARM core board, a 03-ADC, a 04-first DDR, a 05-second DDR, a 06-eMMC, a 07-first modularized conditioning circuit, a 08-second modularized conditioning circuit, a 09-third modularized conditioning circuit, a 10-ICP measuring circuit, a 11-thermocouple temperature measuring circuit, a 12-strain measuring circuit, a 13-conditioning module and a 14-sensor module.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. The achievement of the objects, functional features and advantages of the present utility model will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

In order to make the objects, technical solutions and advantages of the present utility model more apparent, the technical solutions of the present utility model will be clearly and completely described with reference to fig. 1 to 2 of the drawings in the embodiments of the present utility model. It will be apparent that the described embodiments are some, but not all, of the embodiments of the utility model. All other embodiments, based on the embodiments of the utility model, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the utility model.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present utility model. However, it will be apparent to one of ordinary skill in the art that: no such specific details are necessary to practice the utility model. In other instances, well-known structures, circuits, materials, or methods have not been described in detail in order not to obscure the utility model.

Throughout the specification, references to "one embodiment," "an embodiment," "one example," or "an example" mean: a particular feature, structure, or characteristic described in connection with the embodiment or example is included within at least one embodiment of the utility model. Thus, the appearances of the phrases "in one embodiment," "in an example," or "in an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Moreover, those of ordinary skill in the art will appreciate that the illustrations provided herein are for illustrative purposes and that the illustrations are not necessarily drawn to scale. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

In the description of the present utility model, the terms "front", "rear", "left", "right", "upper", "lower", "vertical", "horizontal", "high", "low", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, merely to facilitate description of the present utility model and simplify description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the scope of the present utility model. In the present utility model, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present utility model, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

Example 1:

as shown in fig. 1, in this embodiment, a distributed weapon damage tester capable of being stored in real time includes an FPGA data acquisition circuit 01 and an ARM core board 02 connected with the FPGA data acquisition circuit 01; the FPGA data acquisition circuit 01 comprises an ADC03 for receiving acquired data and a first DDR04 for caching the data; the ARM core board 02 comprises a second DDR05 for caching data and an eMMC06 for storing the data; the output end of the ADC03 is connected with a first DDR04, the first DDR04 is electrically connected with a second DDR05, and the second DDR05 is electrically connected with the eMMC 06.

In the existing distributed weapon damage tester, an ADC03 is directly controlled by an ARM core board 02, data enters the ARM core board 02 through the ADC03, the ARM core board 02 stores the data into an eMMC06, the eMMC06 has non-uniform blocking stagnation when storing the data, and as the ADC03 outputs standard clock data, when the eMMC06 is blocked, the data input by the ADC03 cannot be stored completely, and data loss occurs; because of the severe requirements for volume and power consumption of the distributed weapon damage tester applied to extremely severe test environments, only the reliability of a part of data can be selected in the past when measuring in a large range. Because the unit performance power consumption reduction is realized by the FPGA, the ARM core board 02 and the DDR, the utility model realizes the real-time storage of the distributed weapon damage tester by adding the FPGA data acquisition circuit 01, controlling the ADC03 to receive data by the FPGA data acquisition circuit 01 and carrying out primary high-capacity cache by the DDR, then adding the DDR to the ARM core board 02 to carry out secondary high-capacity cache and completely storing the data into the eMMC06 in a multi-level cache mode, thereby realizing the real-time storage of the distributed weapon damage tester and improving the reliability of data storage.

Preferably: the distributed weapon damage tester further comprises a first modular conditioning circuit 07, a second modular conditioning circuit 08 and a third modular conditioning circuit 09, collectively referred to as conditioning modules 13. The output end of each modularized conditioning circuit is connected with an ADC03 on the FPGA data acquisition circuit 01, and the input end of each modularized conditioning circuit is respectively connected with a sensor driving circuit.

In order to further achieve the object of the utility model, a second embodiment is also proposed.

Example 2:

on the basis of embodiment 1, as shown in fig. 2, the sensor driving circuit includes: ICP measurement circuit 10, thermocouple temperature measurement circuit 11, and strain measurement circuit 12, collectively referred to as sensor module 14. Because a plurality of different sensors are required to be prepared for the test facing a plurality of signals to be tested, and the test is matched with the sensors by a plurality of manufacturers, the data formats of the equipment of the different manufacturers are mutually incompatible, and the data after the test are difficult to uniformly analyze and store and manage, so that the data are converted into uniform standard voltage signals through a modularized conditioning circuit and then are input to the FPGA data acquisition circuit 01.

Preferably: the first DDR04 is DDR2, and the second DDR05 is DDR3L.

Preferably: the FPGA data acquisition circuit 01 transmits data to the ARM core board 02 through a QSPI interface. Since the QSPI interface uses a data queue with pointers and has a wrap-around mode, allowing continuous transfer of data to/from the queue without the need for a CPU, the peripheral acts as a memory mapped parallel device for the CPU; the transmission queue containing up to 16 8-bit or 16-bit data can be transmitted at one time, once transmission is started, CPU intervention is not needed until transmission is finished, transmission efficiency is greatly improved, and integrity of data transmission between two stages of DDR (double data rate) of the cross plate is guaranteed.

Preferably: the ARM core board 02 is a mixed Arm Cortex-A7 core and Cortex-M4 core framework. The Cortex-A7 kernel is special for an open source operating system and is used for taking out and storing the data in the second DDR05 frame by frame into the eMMC06; the Cortex-M4 kernel is special for real-time and low-power task processing.

Preferably: the zero calibration module and the low-pass filter module are arranged on the FPGA data acquisition circuit 01, the offset bias of all channels of signals output by the modularized conditioning circuit is removed through the zero calibration module, and then the signals are sent to the low-pass filter module for anti-aliasing filtering, and finally sent to the ADC03 for analog-to-digital conversion.

The foregoing embodiments have been provided for the purpose of illustrating the general principles of the present utility model, including by way of example only, and not by way of limitation, the utility model may be embodied in any form and method for practicing the utility model, including as follows, in any form and method for practicing the utility model.

Claims (10)

1. The distributed weapon damage tester capable of being stored in real time is characterized by comprising an FPGA data acquisition circuit and an ARM core board connected with the FPGA data acquisition circuit; the FPGA data acquisition circuit comprises an ADC (analog-to-digital converter) for receiving acquired data and a first DDR (double data rate) for caching the data; the ARM core board comprises a second DDR used for caching data and an eMMC used for storing the data; the output end of the ADC is connected with a first DDR, the first DDR is electrically connected with a second DDR, and the second DDR is electrically connected with the eMMC.

2. The distributed weapon damage tester capable of being stored in real time according to claim 1, further comprising a plurality of modularized conditioning circuits, wherein the output end of each modularized conditioning circuit is connected with an ADC on the FPGA data acquisition circuit, and the input end of each modularized conditioning circuit is respectively connected with a sensor driving circuit.

3. The distributed weapon damage tester capable of being stored in real time according to claim 2, wherein the sensor driving circuit comprises: ICP measurement circuit, thermocouple temperature measurement circuit and strain measurement circuit.

4. The distributed weapon damage tester capable of being stored in real time according to claim 2, wherein a low-pass filter module is further connected between the output end of the modularized conditioning circuit and the ADC, and the low-pass filter module is arranged on the FPGA data acquisition circuit.

5. The distributed weapon damage tester capable of being stored in real time according to claim 3, wherein a zero calibration module is further connected between the modularized conditioning circuit and the low-pass filtering module, and the zero calibration module is arranged on the FPGA data acquisition circuit.

6. The real time storable distributed weapon damage tester of claim 1, wherein the first DDR is DDR2.

7. The real time storable distributed weapon damage tester of claim 1, wherein the second DDR is DDR3L.

8. The distributed weapon damage tester capable of being stored in real time according to claim 1, wherein the FPGA data acquisition circuit transmits data to the ARM core board through the QSPI interface.

9. The distributed weapon damage tester capable of being stored in real time according to claim 1, wherein the ARM core board is a dual core board.

10. The distributed weapon damage tester capable of being stored in real time according to claim 9, wherein the ARM core board is a mixed Arm Cortex-A7 core and Cortex-M4 core architecture.

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