CN218767201U

CN218767201U - Testing device

Info

Publication number: CN218767201U
Application number: CN202222267148.4U
Authority: CN
Inventors: 张博
Original assignee: Loongson Zhongke Chengdu Technology Co ltd
Current assignee: Loongson Zhongke Chengdu Technology Co ltd
Priority date: 2022-08-26
Filing date: 2022-08-26
Publication date: 2023-03-28
Anticipated expiration: 2032-08-26

Abstract

The utility model provides a testing device, which is used for testing the startup and shutdown of a board, and comprises a processor, a control switch and a memory; the control switch is connected between the processor and the board card and is used for controlling the on-off of a circuit between the processor and the board card so as to realize the power-on or power-off of the board card; the processor is provided with a first interface and a second interface, the first interface is electrically connected with the board card, the second interface is electrically connected with the memory, and the memory is used for storing power-on or power-off information of the board card. The utility model discloses a testing arrangement can remain the integrated circuit board and go up the electricity or the scene of makeing mistakes when the electricity is unusual down, the tester's of being convenient for location integrated circuit board reason of going up the electricity unusually.

Description

Testing device

Technical Field

The utility model relates to a switching on and shutting down test technical field especially relates to a testing arrangement.

Background

The computer board card needs to be tested for reliability, stability and the like in the production debugging stage, and the startup and shutdown test is one of important test links, and aims to detect whether the card is clamped to other interfaces or is halted easily in the startup and shutdown process.

The magnetic attraction relay and the master control scheme are basically adopted in the startup and shutdown test, and the processor controls the magnetic attraction relay to act, so that the test of the board card is realized. However, in the existing testing process, the tested computer board card and the processor cannot communicate with each other, so that the error site when the board card is abnormally started cannot be reserved, the tester is inconvenient to locate the fault reason, a large amount of manpower and material resources are consumed in the later period, and the finally obtained testing result is low in accuracy.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model provides a testing arrangement to solve the switching on and shutting down test at least and can't remain the scene of makeing mistakes, lead to being difficult to the problem of location integrated circuit board abnormal start reason.

In order to achieve the above purpose, the technical scheme of the utility model is realized like this:

the utility model discloses a testing device, which is used for testing the startup and shutdown of a board, and comprises a processor, a control switch and a memory; the control switch is connected between the processor and the board card and is used for controlling the on-off of a circuit between the processor and the board card so as to realize the power-on or power-off of the board card; the processor is provided with a first interface and a second interface, the first interface is electrically connected with the board card, the second interface is electrically connected with the memory, and the memory is used for storing power-on or power-off information of the board card.

Optionally, the control switch includes an input terminal, an output terminal, and a control terminal; the input end is electrically connected with an external power supply and used for receiving signals of the external power supply; the output end is electrically connected with the board card and is used for outputting a signal of the external power supply to the board card; the control end is electrically connected with the processor and used for controlling the connection or disconnection of the input end and the output end so as to realize the power-on or power-off of the board card.

Optionally, the device further includes a feedback circuit, connected between the output end of the control switch and the processor, for feeding back the on-off state of the control switch to the processor.

Optionally, the feedback circuit comprises a rectifier and a voltage reducer, the rectifier being electrically connected with the voltage reducer; the output end of the control switch is electrically connected with the rectifier, and the processor is electrically connected with the voltage reducer.

Optionally, the processor includes a timer module, and the timer module is configured to control the memory to store the power-on or power-off information of the board card after a preset time period.

Optionally, the processor is provided with a network port, and the network port is used for transmitting the power-on or power-off information of the board card to the remote terminal.

Optionally, the processor is provided with at least two first interfaces, and each first interface is connected with one board card.

Optionally, the number of the control switches is at least two, and one control switch is independently connected between each first interface and the board card.

Optionally, the apparatus further includes a display module, the processor is provided with a third interface, and the third interface is electrically connected to the display module; the display module is used for displaying the on-off times of the control switch.

Optionally, the device further includes an operation panel, the processor is provided with a fourth interface, and the fourth interface is electrically connected to the operation panel; the operation panel is used for selecting the on-off times of the control switch.

Compared with the prior art, testing arrangement have following advantage:

the utility model discloses a testing arrangement can establish the communication between treater and the integrated circuit board, makes the memory can acquire the last electricity of integrated circuit board or electric information down and save to can remain the integrated circuit board and go up the electricity or the scene of makeing mistakes when the electricity is unusual down, the tester of being convenient for fixes a position the integrated circuit board reason of electricity about unusual.

Drawings

The accompanying drawings, which form a part hereof, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention without undue limitation. In the drawings:

fig. 1 is a schematic view of a testing apparatus of the present invention;

FIG. 2 is a schematic view of another testing device of the present invention;

fig. 3 is a schematic diagram of the testing device for testing a plurality of boards of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

The terms "first," "second," and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that embodiments of the invention can be practiced in sequences other than those illustrated or described herein, and the terms "first," "second," and the like are generally used herein in a generic sense without limitation to the number of terms, e.g., the first term can be one, or more than one. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/", and generally means that the former and latter related objects are in an "or" relationship.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrase "in one embodiment" appearing in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Introduce in detail through enumerating specific embodiment below the utility model provides a pair of testing arrangement is applied to the on & off test to the integrated circuit board.

Referring to fig. 1, the apparatus comprises a processor 1, a control switch 2 and a memory 4; the control switch 2 is connected between the processor 1 and the board card 3 and is used for controlling the on-off of a circuit between the processor 1 and the board card 3 so as to realize the power-on or power-off of the board card 3; the processor 1 is provided with a first interface 11 and a second interface 12, the first interface 11 is electrically connected with the board card 3, the second interface 12 is electrically connected with the memory 4, and the memory 4 is used for storing power-on or power-off information of the board card 3.

Particularly, the utility model discloses startup and shutdown testing arrangement is a test module in essence, including treater 1, control switch 2 and memory 4, through the last electricity or the outage of the on-off control integrated circuit board 3 of treater 1, realize the startup and shutdown test of integrated circuit board 3. The board card 3 can be any type of card such as a computer motherboard, an acquisition card, a sound card, a display card and the like, the control switch 2 is an electronic switch and is connected between the processor 1 and the board card 3, and the on-off of a circuit between the processor 1 and the board card 3 can be controlled by controlling the on-off of the control switch 2, so that the power-on or power-off of the board card 3 is realized.

The processor 1 is provided with a first interface 11 and a second interface 12, and the board 3 is electrically connected to the first interface 11, so that communication between the processor 1 and the board 3 is established through the first interface 11. The memory 4 is electrically connected to the second interface 12 such that communication between the processor 1 and the memory 4 is established via the second interface 12. The types of the first interface 11 and the second interface 12 can be freely set according to the type of data to be transmitted, for example, the first interface 11 can be a UART (Universal Asynchronous Receiver/Transmitter) interface, and the data to be transmitted between the processor 1 and the board 3 can be converted between serial communication and parallel communication through the UART interface, so as to realize the communication between the processor 1 and the board 3. The second interface 12 may be a serial port on the processor 1, a transmission line is connected between the serial port and the memory 4, and information on the processor 1 may be burned into the memory 4 through the transmission line to store data information.

In the test process, the board 3 can send an instruction to the processor 1 through the first interface 11, and indicate the power-on or power-off state of the board 3 to the processor 1 through the instruction. The instruction is usually a string of field codes, and includes an operation code field for indicating the next action to be performed by the processor 1 and an address code field for indicating the object of the next action to be performed by the processor 1. For example, in the process of testing the board card 3, if the board card 3 completes normal startup, an instruction containing a hexadecimal number code is sent to the processor 1, and when the processor 1 receives the instruction, the next repetitive switching is executed; if the board 3 is not normally started, the instruction including the hexadecimal number code is not sent to the processor 1, the processor 1 cannot receive the instruction, and at this time, the processor 1 keeps the current state and does not perform the next switching. Under the condition that the board card 3 is not normally started, the memory 4 can store information under the abnormal condition of power-on or power-off of the board card 3, so that a fault site when the power-on or power-off is abnormal is reserved, and a tester can conveniently locate the reason of the abnormal condition of the power-on or power-off of the board card 3. Certainly, the memory 4 can also retain information of the board card 3 under normal power-on or power-off conditions, so that a tester can check error reasons in comparison.

The utility model discloses a communication between treater 1 and integrated circuit board 3 can be established to the switching on and shutting down testing arrangement, makes memory 4 can acquire the last electricity of integrated circuit board 3 or down electric information and save to can remain the scene of makeing mistakes when 3 electricity of integrated circuit boards or the electricity is unusual down, the tester of being convenient for fixes a position 3 reasons of the unusual electricity of going up and down of integrated circuit board.

Alternatively, referring to fig. 2, the control switch 2 includes an input terminal 21, an output terminal 22, and a control terminal 23; the input end 21 is electrically connected with an external power supply and used for receiving signals of the external power supply; the output end 22 is electrically connected with the board card 3 and is used for outputting a signal of the external power supply to the board card 3; the control end 23 is electrically connected to the processor 1, and is configured to control the input end 21 and the output end 22 to be turned on or off, so as to power on or power off the board card 3.

Specifically, the control switch 2 includes three ports, i.e., an input terminal 21, an output terminal 22, and a control terminal 23, the input terminal 21 is electrically connected to an external power source, the output terminal 22 is electrically connected to the board 3, and the input terminal 21 and the output terminal 22 can transmit 220V of ac voltage, thereby ensuring that the power-on voltage of the board 3 is satisfied. Of course, a voltage reducer is usually connected between the output terminal 22 and the board 3 to prevent the board 3 from being burned out by an excessive voltage. The control end 23 is electrically connected with the processor 1, the control end 23 controls the connection or disconnection of the input end 21 and the output end 22, the power-on of the board card 3 is realized under the condition that the input end 21 is connected with the output end 22, and the power-off of the board card 3 is realized under the condition that the input end 21 is disconnected with the output end 22. Preferably, the control switch 2 of the present embodiment may be a solid-state relay, and the solid-state relay is a contactless switch element which is composed of solid-state electronic elements, and can flexibly turn on or off a controlled circuit, and has strong anti-interference capability and long service life. When the control switch 2 is a solid-state relay, the output end 22 of the solid-state relay needs to be connected with a converter, and the converter is electrically connected with the board card 3, so that the control of power-on and power-off of the board card 3 is realized.

Optionally, referring to fig. 2, the apparatus further includes a feedback circuit (not shown in the figure), connected between the output terminal 22 of the control switch 2 and the processor 1, for feeding back the on/off state of the control switch 2 to the processor 1.

Specifically, the feedback circuit is connected between the output terminal 22 of the control switch 2 and the processor 1, and can feed back the on/off state of the control switch 2 to the processor 1. In some embodiments, the processor 1 already controls the control switch 2 to be turned on through the control terminal 23, but actually, due to poor contact or response failure of the control switch 2, there may not be real conduction, so that the board 3 cannot be normally powered up. In the test process, the performance problem of the board card 3 can be mistakenly considered, and the test result is influenced. Therefore, the feedback circuit is designed to feed back the on-off state of the control switch 2 to the processor 1, and when the control switch 2 is not really turned on, the signal input to the control terminal 23 is repeated to ensure that the control switch 2 is really turned on and the circuit between the processor 1 and the board card 3 smoothly circulates. If the control switch 2 has a problem of multiple conduction faults, the control switch 2 can be replaced in time, and subsequent test results are prevented from being influenced.

Specifically, the rectifier can convert alternating current output by the control switch 2 into direct current for the processor 1 to use, the voltage reducer can reduce higher voltage to ideal voltage suitable for normal use of the processor 1, such as 3.3V,1.2V and the like, the voltage reducer performs rectification and then reduces voltage, the circuit structure is simple, transmission efficiency is high, a feedback circuit can be effectively prevented from burning out the processor 1, and safety of the device is improved.

Optionally, the processor 1 includes a timer module, and the timer module is configured to control the memory 4 to store the power-on or power-off information of the board card 3 after a preset time period.

Specifically, the timer module may be a high-precision RTC module (Real _ Time Clock) integrated on the processor 1, so that the processor 1 has a timing function. Under the condition that the board card 3 is not normally started, the processor 1 can control the memory 4 to store abnormal power-on and power-off information of the board card 3 after a preset time length. The preset duration is determined according to the RTC module, and the RTC module can be freely selected according to actual test requirements, which is not limited in this embodiment. The memory 4 is used for storing in a delayed mode, so that misoperation caused by slow response of the board card 3 connecting circuit can be avoided, and the testing accuracy is improved.

Optionally, the processor 1 is provided with a network port, and the network port is configured to transmit power-on or power-off information of the board card to a remote terminal.

Particularly, the processor 1 is provided with a network port with a remote communication function, and the stored board card 3 in the memory 4 can be sent to a remote terminal through the network port, so that the remote regulation and control of testers are facilitated, the necessity of field regulation and control is reduced, the flexibility of testing is effectively improved, and the testing workload is reduced.

Optionally, the processor 1 is provided with at least two first interfaces 11, and each first interface 11 is connected to one board card 3.

Specifically, processor 1 can set up two or more than two first interfaces 11, and every first interface 11 all connects a integrated circuit board 3 to realized the communication between processor 1 and a plurality of integrated circuit boards 3, under the state of control switch 2 switch-on, processor 1 can control the power-on or the power-off of a plurality of integrated circuit boards 3 simultaneously, and memory 4 also can be saved the last telegram information of a plurality of integrated circuit boards 3, promotes the efficiency of software testing of integrated circuit board 3 to a large extent.

Optionally, referring to fig. 3, at least two control switches 2 are provided, and one control switch 2 is independently connected between each first interface 11 and the board card 3.

Specifically, on the basis that the processor 1 is provided with the plurality of first interfaces 11, the control switches 2 may be provided in plurality, the number of the control switches 2 is the same as that of the board cards 3, and one control switch 2 is independently connected between each first interface 11 and each board card 3, so that independent control of the plurality of board cards 3 is realized. Fig. 3 shows a schematic connection diagram of the device comprising two control switches 2 and two boards 3, which are independent of each other. When the number of the control switches 2 and the boards 3 is plural, the memory 4 may be one, and store the power-on and power-off information of all the boards 3, or may be plural, and store the power-on and power-off information of the corresponding boards 3.

Optionally, referring to fig. 2, the apparatus further includes a display module 5, the processor 1 is provided with a third interface 13, and the third interface 13 is electrically connected to the display module 5; the display module 5 is used for displaying the on-off times of the control switch 2.

Specifically, treater 1 is provided with third interface 13, and third interface 13 is connected with display module 5 electricity, realizes the communication between treater 1 and the display module 5, and display module 5 can be electronic display screen etc. can show control switch 2's break-make number of times, and the record is looked over to the tester of being convenient for.

Optionally, referring to fig. 2, the apparatus further includes an operation panel 6, the processor 1 is provided with a fourth interface 14, and the fourth interface 14 is electrically connected to the operation panel 6; the operation panel 6 is used for selecting the on-off times of the control switch 2.

Specifically, the processor 1 is provided with the fourth interface 14, the fourth interface 14 is electrically connected with the operation panel 6, so that communication between the processor 1 and the operation panel 6 is realized, the operation panel 6 may be an electronic touch screen, a mechanical key or the like, and the on-off times of the control switch 2 can be selected, for example, a tester can directly click the operation panel 6 and select the on-off of the control switch 2 for 10 times, 20 times or the like, and the control switch 2 stops operating after being turned on and off for 50 times, and is in an off state, so that the operation steps of the tester are simplified.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or terminal apparatus that comprises the element.

The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A testing device is used for performing on-off test on a board, and is characterized by comprising a processor, a control switch and a memory;

the control switch is connected between the processor and the board card and is used for controlling the on-off of a circuit between the processor and the board card so as to realize the power-on or power-off of the board card;

the processor is provided with a first interface and a second interface, the first interface is electrically connected with the board card, the second interface is electrically connected with the memory, and the memory is used for storing power-on or power-off information of the board card.

2. The test device of claim 1, wherein the control switch comprises an input terminal, an output terminal, and a control terminal;

the input end is electrically connected with an external power supply and used for receiving signals of the external power supply; the output end is electrically connected with the board card and is used for outputting a signal of the external power supply to the board card; the control end is electrically connected with the processor and used for controlling the connection or disconnection of the input end and the output end so as to realize the power-on or power-off of the board card.

3. The test device of claim 2, further comprising a feedback circuit connected between the output of the control switch and the processor for feeding back the on/off state of the control switch to the processor.

4. The test device of claim 3, wherein the feedback circuit comprises a rectifier and a buck, the rectifier being electrically connected to the buck;

the output end of the control switch is electrically connected with the rectifier, and the processor is electrically connected with the voltage reducer.

5. The test device as claimed in any one of claims 1 to 4, wherein the processor includes a timer module, and the timer module is configured to control the memory to store power-on or power-off information of the board after a preset time period.

6. The test device as claimed in any one of claims 1 to 4, wherein the processor is provided with a network port for transmitting power-on or power-off information of the board card to a remote terminal.

7. A test device as claimed in any one of claims 1 to 4, wherein the processor is provided with at least two first interfaces, one of said boards being connected to each of said first interfaces.

8. The test device of claim 7, wherein there are at least two control switches, and one control switch is independently connected between each first interface and the board card.

9. The testing device of any one of claims 1-4, wherein the device further comprises a display module, the processor is provided with a third interface, and the third interface is electrically connected with the display module;

the display module is used for displaying the on-off times of the control switch.

10. The testing device of any one of claims 1-4, wherein the device further comprises an operating panel, the processor is provided with a fourth interface, and the fourth interface is electrically connected with the operating panel;

the operation panel is used for selecting the on-off times of the control switch.