CN218730910U - Chip packaging structure - Google Patents
Chip packaging structure Download PDFInfo
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- CN218730910U CN218730910U CN202222973181.9U CN202222973181U CN218730910U CN 218730910 U CN218730910 U CN 218730910U CN 202222973181 U CN202222973181 U CN 202222973181U CN 218730910 U CN218730910 U CN 218730910U
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- metal layer
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- welding metal
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Abstract
The embodiment of the disclosure provides a chip packaging structure, which comprises a substrate, a chip, a welding metal layer, at least one blocking structure and a radiating fin; the chip is arranged on a substrate; the welding metal layer is arranged on one side of the chip, which is far away from the substrate; the blocking structure is embedded at one side of the welding metal layer, which is far away from the chip, and is used for blocking the flow of the welding metal layer in a molten state; the radiating fin cover is arranged on one side of the blocking structure, which is far away from the welding metal layer, and the edge area of the radiating fin is fixed on the substrate. The packaging structure is used for blocking the flow of the welding metal layer in a molten state, so that the flow resistance of the molten welding metal layer in a reflow process can be increased, and the loss of the welding metal layer in the reflow process is reduced; the contact area between the welded metal layer and the radiating fin after welding is increased, and the heat diffusion capacity is increased; the coating area of the soldering flux can be increased, the accumulation amount of the soldering flux at a single-point position is reduced, and the generation of cavities of a soldering metal layer in a high-temperature state is reduced.
Description
Technical Field
The embodiment of the disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a chip packaging structure.
Background
However, as the package size increases and the number of chips increases, the bonding of the bonding metal layer also poses challenges. When the conventional gold-plated heat sink is used for soldering, abnormal phenomena such as missing of a soldering metal layer, bridging of the soldering metal layer and the like often occur after reflow, which can cause reliability problems and quality damage to electronic components except for a chip.
In view of the above problems, there is a need for a chip package structure with a reasonable design and capable of effectively improving the above problems.
SUMMERY OF THE UTILITY MODEL
The disclosed embodiment aims to solve at least one of the technical problems in the prior art, and provides a chip packaging structure.
An embodiment of the present disclosure provides a chip package structure, including:
substrate (ii) a;
the chip is arranged on the substrate;
the welding metal layer is arranged on one side of the chip, which is far away from the substrate;
the blocking structure is embedded at one side of the welding metal layer, which is far away from the chip, and is used for blocking the flow of the welding metal layer in a molten state;
the heat radiating fin is covered on one side of the blocking structure, which deviates from the welding metal layer, and the edge area of the heat radiating fin is fixed on the substrate.
Optionally, the blocking structure comprises a connector and a plurality of first blocking members;
the connecting piece is arranged on the surface of the welding metal layer, and the plurality of first blocking pieces are arranged at intervals along the length direction of the connecting piece; the first end of the first blocking piece is connected with the connecting piece, and the second end of the first blocking piece is inserted in the welding metal layer.
Optionally, the chip packaging structure includes a plurality of blocking structures, and the plurality of blocking structures are distributed at intervals along the first direction of the solder metal layer.
Optionally, the plurality of first blocking parts in two adjacent blocking structures are distributed in a staggered manner.
Optionally, a gap is formed between each first blocking element and the opposite connecting element in two adjacent blocking structures, so as to form a flow guide channel.
Optionally, the package structure further includes an insulating adhesive layer disposed at an edge region of the substrate;
the insulating adhesive layer is provided with a plurality of openings, and the openings correspond to the passage openings of the flow guide passages.
Optionally, the barrier structure located at the edge region of the weld metal layer further includes a plurality of second barriers;
the plurality of second blocking pieces are arranged at intervals outside the corresponding connecting pieces; the first end of the second blocking piece is connected with the corresponding first blocking piece, and the second end of the second blocking piece is inserted in the welding metal layer.
Optionally, the blocking structure includes a plurality of bosses, and the plurality of bosses are embedded in the welding metal layer at intervals.
Optionally, the solder metal layer is a solder thermal interface material layer.
Optionally, the barrier structure is formed by using copper metal.
According to the chip packaging structure disclosed by the embodiment of the disclosure, the at least one blocking structure is embedded on the side, away from the chip, of the welding metal layer and is used for blocking the flow of the welding metal layer in a molten state, so that the flow resistance of the molten welding metal layer in a reflow process can be increased, and the loss of the welding metal layer in the reflow process is reduced; the splashing of the welding metal layer is reduced, the quality damage to electronic elements outside the chip is prevented, and the reliability of the chip packaging structure is improved; meanwhile, the contact area between the welded metal layer and the radiating fins after welding is increased, the heat dissipation interface is improved from unidirectional vertical heat conduction to multidirectional efficient heat conduction, and the heat diffusion capacity is increased; the coating area of the soldering flux can be increased, the accumulation amount of the soldering flux at a single-point position is reduced, and the generation of cavities of a soldering metal layer in a high-temperature state is reduced.
Drawings
Fig. 1 is a schematic cross-sectional structure diagram of a chip package structure in an embodiment of the disclosure;
FIG. 2 is a top view of a barrier structure in another embodiment of the present disclosure;
fig. 3 is a top view of a flow guide channel and an insulating adhesive layer according to another embodiment of the disclosure;
fig. 4 is a schematic cross-sectional structure diagram of a chip package structure according to another embodiment of the disclosure.
Detailed Description
In order to better understand the technical solutions of the embodiments of the present disclosure, those skilled in the art will now describe the embodiments of the present disclosure in further detail with reference to the accompanying drawings and detailed description.
As shown in fig. 1, an embodiment of the present disclosure provides a chip package structure 100, including: substrate 110, chip 120, solder metal layer 130, at least one barrier structure 140, and heat sink 150. The chip 120 is disposed on the substrate 110, in this embodiment, the chip 120 is flip-chip mounted on the substrate 110 through a plurality of solder balls 121, an underfill layer 122 is disposed between the chip 120 and the substrate 110, and the underfill layer 122 wraps the plurality of solder balls 121, so as to fix the chip 120 and protect the plurality of solder balls. It should be noted that the chip 120 may also be disposed on the substrate 110 in other manners, and this embodiment is not limited in particular.
The solder metal layer 130 is disposed on a side of the chip 120 away from the substrate 110. In the present embodiment, the solder metal layer 130 is a solder thermal interface material layer, that is, the solder metal layer 130 is made of a solder thermal interface material. The solder thermal interface material has high thermal conductivity, and the heat dissipation capacity is improved. Further preferably, in the present embodiment, an indium sheet is used as the solder metal layer 130. The indium sheet is a solder thermal interface material with high thermal conductivity, and can increase the heat dissipation of the chip packaging structure.
The blocking structure 140 is embedded in a side of the solder metal layer 130 facing away from the chip 120, and is used for blocking the flow of the solder metal layer 130 in a molten state. In the present embodiment, the barrier structure 140 is in the shape of a dam, and the barrier structure 140 is formed by using copper metal. The barrier structure 140 using copper metal can increase the heat dissipation of the chip package structure.
It should be noted that, in the present embodiment, the shape and the material of the blocking structure 140 are not particularly limited, and may be selected according to the needs.
The heat sink 150 covers a side of the blocking structure 140 facing away from the solder metal layer 130, and an edge region of the heat sink 150 is fixed to the substrate 110. As illustrated in fig. 1, in the present embodiment, the size of the heat sink 150 is larger than that of the chip 120, and an edge area of the heat sink 150 is fixed to the substrate 110 by the adhesive layer 151. The material of the heat sink 150 may be a metal material such as elemental indium, indium alloy, silver alloy, etc., and this embodiment is not particularly limited. The heat sink 150 is provided to help the package structure to dissipate heat integrally, thereby improving the heat dissipation performance of the package structure.
According to the chip packaging structure disclosed by the embodiment of the disclosure, the at least one blocking structure is embedded on the side, away from the chip, of the welding metal layer and is used for blocking the flow of the welding metal layer in a molten state, so that the flow resistance of the molten welding metal layer in a reflow process can be increased, and the loss of the welding metal layer in the reflow process is reduced; the splashing of the welding metal layer is reduced, the quality damage to electronic elements outside the chip is prevented, and the reliability of the chip packaging structure is improved; meanwhile, the contact area between the welded metal layer and the radiating fins after welding is increased, the heat dissipation interface is improved from unidirectional vertical heat conduction to multidirectional efficient heat conduction, and the heat diffusion capacity is increased; the coating area of the soldering flux can be increased, the accumulation amount of the soldering flux at a single-point position is reduced, and the generation of cavities of a soldering metal layer in a high-temperature state is reduced.
Illustratively, as shown in fig. 2 and 3, the blocking structure 140 includes a connecting member 141 and a plurality of first blocking members 142. The connection member 141 is disposed on the surface of the solder metal layer 130, and the plurality of first blocking members 142 are disposed at intervals along a length direction of the connection member 141. A first end of the first blocking member 142 is connected to the connection member 141, and a second end of the first blocking member 142 is inserted into the solder metal layer 130. That is, the blocking structure 140 formed by the connecting member 141 and the plurality of first blocking members 142 has a dam shape or a rail shape.
In the above embodiment, the plurality of first blocking members can increase the flow resistance of the molten solder metal layer in the reflow process, and reduce the loss of the solder metal layer in the reflow process.
Illustratively, as shown in fig. 2 and 3, the chip package structure 100 includes a plurality of barrier structures 140, and the plurality of barrier structures 140 are spaced along the first direction of the solder metal layer 130. In the present embodiment, the plurality of barrier structures 140 are spaced apart along the width direction of the solder metal layer 130. That is, the first direction is a width direction of the solder metal layer 130, and of course, the first direction may also be a length direction of the solder metal layer 130 or other directions, and the embodiment is not limited in particular.
Specifically, in the present embodiment, the plurality of first stoppers 142 are disposed at intervals along the length direction of the connection member 141. The first blocking members 142 may be disposed at equal intervals or at unequal intervals, and this embodiment is not limited in particular. Further, in the present embodiment, four first stoppers 142 are disposed on each of the connectors 141, wherein the first stoppers 142 are disposed at both ends of the connector 141.
It should be noted that the number of the first blocking members 142 is not specifically limited in this embodiment, and can be selected as needed.
In the above embodiment, the blocking structure is provided with the connecting piece and the plurality of first blocking pieces distributed at intervals along the length direction of the connecting piece, and the plurality of first blocking pieces can block the flow of the welding metal layer in a molten state, so that the flow resistance of the molten welding metal layer in the reflow process is increased, and the loss of the welding metal layer in the reflow process is reduced; the splashing of the welding metal layer is reduced, the quality damage to electronic elements outside the chip is prevented, and the reliability of the chip packaging structure is improved; meanwhile, the contact area between the welded metal layer and the radiating fins after welding is increased, the heat dissipation interface is improved from unidirectional vertical heat conduction to multidirectional efficient heat conduction, and the heat diffusion capacity is increased; the coating area of the soldering flux can be increased, the accumulation amount of the soldering flux at a single-point position is reduced, and the generation of cavities of a soldering metal layer in a high-temperature state is reduced.
Illustratively, the first blocking members 142 in two adjacent blocking structures 140 are staggered. That is, as shown in fig. 2 and 3, the first blocking members 142 of the two adjacent blocking structures 140 are not aligned but staggered.
Illustratively, each first blocking member 142 and the opposite connecting member 141 of two adjacent blocking structures 140 have a gap therebetween to form a flow guide channel 160.
Specifically, as shown in fig. 2 and 3, gaps are provided between the upper connecting member 141 and the plurality of first blocking members 142 on the lower connecting member 141 of two adjacent blocking structures 140, and gaps are provided between the lower connecting member 141 and the plurality of first blocking members 142 on the upper connecting member 141, so that the air guide passage 160 is formed.
In the above embodiment, the flow guide channel is formed between two adjacent first blocking members, so that when the soldering metal layer is subjected to vacuum reflow soldering, gas generated by the soldering flux at high temperature can be pumped out along the flow guide channel, thereby reducing the aggregation of soldering cavities on the soldering metal layer.
Illustratively, as shown in fig. 3, the package structure 100 further includes an insulating adhesive layer 170 disposed on the edge region of the substrate 110. The insulation layer 170 is provided with a plurality of openings 171, and the openings 171 correspond to the channel openings 161 of the flow guide channels 160.
In the above embodiment, the design of the patterns of the insulating adhesive layer is optimized, so that the opening of the insulating adhesive layer corresponds to the passage opening of the diversion channel, the vacuumizing force at the position of the passage opening is enhanced, the welded cavity of the welded metal layer is reduced, and meanwhile, due to the existence of the dam-shaped blocking structure, the splashing of the welded metal layer can be reduced.
Illustratively, as shown in fig. 2 and 3, the barrier structure 140 at the edge region of the solder metal layer 130 further includes a plurality of second barriers 143. The second stoppers 143 are disposed at intervals outside the corresponding connectors 141. A first end of the second blocking member 143 is connected to the corresponding first blocking member 142, and a second end of the second blocking member 143 is interposed in the solder metal layer 130.
Specifically, as shown in fig. 2 and 3, the second stoppers 142 are disposed outside the first stoppers 141 on the top and bottom stopper structures, the first ends of the second stoppers 143 are connected to the corresponding first stoppers 142, and the second ends of the second stoppers 143 are inserted into the solder metal layer 130, so that the flow resistance of the molten solder metal layer during the reflow process can be increased, the spatter of the solder metal layer can be reduced, and the quality damage to the electronic components other than the chip can be prevented.
Illustratively, as shown in fig. 4, in another embodiment, the blocking structure 140 includes a plurality of bosses 144, and the plurality of bosses 144 are embedded in the solder metal layer 130 at intervals. In this embodiment, the shape of the plurality of bosses 144 is not particularly required, and the longitudinal section of the boss 144 may be trapezoidal, rectangular, or the like, which may be selected according to actual needs. The plurality of bosses 144 may or may not be distributed in an array, and may be selected according to actual needs. In this embodiment, the boss 144 is also made of a metal copper material, and the material of the boss 144 is not particularly limited and may be selected according to actual needs.
In the above embodiment, the blocking structure is designed into a plurality of bosses, so that the overflow resistance during the melting of the welding metal layer can be increased, and the stabilizing effect is achieved. The contact area between the welding metal layer and the radiating fin can be increased, and the heat dissipation interface is improved from unidirectional vertical heat conduction to multidirectional efficient heat conduction. The coating area of the soldering flux can be increased, the accumulation amount of the soldering flux at a single-point position is reduced, and the generation of cavities of a soldering metal layer in a high-temperature state is reduced.
As shown in fig. 1 and 4, the package structure 100 further includes a plated metal layer 191, the plated metal layer 191 being sandwiched between the heat sink 150 and the barrier structure 140. In this embodiment, the electroplated metal layer 191 is a gold plating layer, and the gold plating layer can increase the thermal conductivity of the chip.
As shown in fig. 1 and fig. 4, the package structure 100 further includes a plurality of package solder balls 192, the plurality of package solder balls 192 are disposed on a side of the substrate 110 away from the chip 120, and the package structure 100 is electrically connected to the outside through the package solder balls 192.
It is to be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the disclosed embodiments, and that the disclosed embodiments are not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and scope of the embodiments of the present disclosure, and such modifications and improvements are also considered to be within the scope of the embodiments of the present disclosure.
Claims (10)
1. A chip package structure, comprising:
a substrate;
the chip is arranged on the substrate;
the welding metal layer is arranged on one side of the chip, which is far away from the substrate;
the blocking structure is embedded at one side of the welding metal layer, which is far away from the chip, and is used for blocking the flow of the welding metal layer in a molten state;
and the radiating fin is covered on one side of the blocking structure departing from the welding metal layer, and the edge area of the radiating fin is fixed on the substrate.
2. The chip package structure according to claim 1, wherein the blocking structure comprises a plurality of first blocking members and a connecting member;
the connecting piece is arranged on the surface of the welding metal layer, and the plurality of first blocking pieces are arranged at intervals along the length direction of the connecting piece; the first end of the first blocking piece is connected with the connecting piece, and the second end of the first blocking piece is inserted in the welding metal layer.
3. The chip package structure according to claim 2, wherein the chip package structure comprises a plurality of barrier structures, and the plurality of barrier structures are spaced along the first direction of the solder metal layer.
4. The chip package structure according to claim 3, wherein the plurality of first blocking members in two adjacent blocking structures are staggered.
5. The chip package structure according to claim 4, wherein a gap is formed between each first blocking element and the opposite connecting element in two adjacent blocking structures to form a flow guide channel.
6. The chip package structure according to claim 5, further comprising an insulating adhesive layer disposed at an edge region of the substrate;
the insulating adhesive layer is provided with a plurality of openings, and the openings correspond to the passage openings of the flow guide passages.
7. The chip package structure according to any one of claims 3 to 6, the barrier structure at the edge region of the weld metal layer further comprises a plurality of second barriers;
the plurality of second blocking pieces are arranged at intervals outside the corresponding connecting pieces; the first end of the second blocking piece is connected with the corresponding first blocking piece, and the second end of the second blocking piece is inserted in the welding metal layer.
8. The chip package structure according to claim 1, wherein the blocking structure comprises a plurality of bumps, and the plurality of bumps are embedded in the solder metal layer at intervals.
9. The chip package structure according to any one of claims 1 to 6, wherein the solder metal layer is a solder thermal interface material layer.
10. The chip package structure according to any one of claims 1 to 6, wherein the blocking structure is formed of copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222973181.9U CN218730910U (en) | 2022-11-08 | 2022-11-08 | Chip packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222973181.9U CN218730910U (en) | 2022-11-08 | 2022-11-08 | Chip packaging structure |
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| CN218730910U true CN218730910U (en) | 2023-03-24 |
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| CN202222973181.9U Active CN218730910U (en) | 2022-11-08 | 2022-11-08 | Chip packaging structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118073299A (en) * | 2024-01-29 | 2024-05-24 | 广东芯聚能半导体有限公司 | Heat dissipation structure and semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118073299A (en) * | 2024-01-29 | 2024-05-24 | 广东芯聚能半导体有限公司 | Heat dissipation structure and semiconductor device |
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