CN218450092U - Digital-to-analog conversion circuit for successive approximation type analog-to-digital converter - Google Patents
Digital-to-analog conversion circuit for successive approximation type analog-to-digital converter Download PDFInfo
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Abstract
The utility model discloses a digital analog conversion circuit for successive approximation type analog-to-digital converter, which is applied to the technical field of integrated circuits, a zooming capacitor array comprises a low-level supplementary capacitor, a high-level supplementary circuit and a bridging capacitor, and the low-level capacitor array is connected with one end of a comparator after being connected with the high-level capacitor array through the bridging capacitor; the other end of the comparator is connected with the energy storage capacitor array; the low-order capacitor, the low-order supplementary capacitor, the high-order capacitor and the high-order supplementary capacitor are all connected with the switch array; the low-order supplementary capacitor is connected with the low-order capacitor in parallel to adjust the common capacitance value of the low-order capacitor array and the low-order supplementary capacitor, so that the bridging capacitor is formed by connecting an integral number of unit capacitors in parallel. Through designing the scaling capacitor array, the capacitance value of the bridging capacitor is an integral multiple of a unit capacitance value, the bridging capacitor is better matched, the parasitic capacitor is smaller, and the analog-digital converter has the advantages of simple structure, reasonable layout, clear signal path and high matching degree and realizes an analog-digital converter with better performance.
Description
Technical Field
The utility model relates to an integrated circuit technical field especially relates to a digital analog conversion circuit for approaching type analog to digital converter one by one.
Background
With the development of science and technology, the cost of very large scale integrated circuits is continuously reduced, so that many analog functional modules are gradually converted into digital signals to be implemented, and therefore, the application of analog-to-digital converters has been widely popularized in many electronic systems, i.e., digital signal processing systems, however, signals in the real world are continuous analog signals all the time, and therefore, the analog-to-digital converters are required to convert the analog signals into digital signals. A successive approximation analog-to-digital converter (SAR ADC) is a low sampling rate (5 MSPS) medium and high precision application structure, and has wide application due to its simple structure, small size and low power consumption.
Among them, the capacitive DAC (digital-to-analog converter) is the most commonly used structure at present, and it implements digital-to-analog conversion based on the charge redistribution of the capacitor array. This structure can achieve higher accuracy because the matching between capacitors is higher than the matching of resistors in CMOS processes. In addition, since this structure is based on a switched capacitor method, there is no static power consumption, and thus, this structure has become a mainstream structure of the SAR ADC at present.
Since in high precision applications there is a large ratio between the lowest order capacitance and the highest order capacitance, for example for 12-bit precision the ratio of the maximum capacitance to the minimum capacitance is 2048. This takes up a large chip area. To solve this problem, a segmented capacitor array structure is employed. However, the conventional capacitive analog-to-digital converter circuit has low precision and cannot achieve high performance. Therefore, how to provide a high-precision digital-to-analog conversion circuit for a successive approximation analog-to-digital converter is a problem to be solved by those skilled in the art.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a digital analog conversion circuit for successive approximation type analog to digital converter has higher precision.
In order to solve the above technical problem, the present invention provides a digital-to-analog conversion circuit for a successive approximation analog-to-digital converter, which includes a high-order capacitor array, a scaling capacitor array, a low-order capacitor array, an energy storage capacitor array, and a switch array;
the low-order capacitor array comprises a low-order capacitor, and the high-order capacitor array comprises a high-order capacitor; the scaling capacitor array comprises a low-order supplementary capacitor, a high-order supplementary capacitor and a bridging capacitor, the low-order capacitor array is connected with one end of a comparator after being connected with the high-order capacitor array through the bridging capacitor, and the energy storage capacitor array is connected with the other end of the comparator; the low-order capacitor, the low-order supplementary capacitor, the high-order capacitor and the high-order supplementary capacitor are all connected with the switch array; the high-order supplementary capacitor is connected with the high-order capacitor in parallel; the low-order supplementary capacitor is connected with the low-order capacitor in parallel to adjust the common capacitance value of the low-order capacitor array and the low-order supplementary capacitor, so that the bridging capacitor is formed by connecting an integral number of unit capacitors in parallel.
Optionally, the low-order capacitor array includes a 5-bit low-order capacitor, and the high-order capacitor array includes a 7-bit high-order capacitor.
Optionally, the capacitance value of the bridge capacitor is 2 times of a unit capacitance value; the capacitance value of the low-order supplementary capacitor is 31 times of unit capacitance value.
Optionally, the capacitance value of the high-order supplemental capacitor is 16 times of the unit capacitance value.
Optionally, the unit capacitor is a mom capacitor.
Optionally, an isolation guard ring is disposed around the unit capacitor, and the isolation guard ring and the corresponding unit capacitor have the same level of metal.
Optionally, the unit capacitors corresponding to the high-order capacitor array, the unit capacitors corresponding to the scaling capacitor array, the unit capacitors corresponding to the low-order capacitor array, and the unit capacitors corresponding to the energy storage capacitor array are distributed to form a capacitor array layout, and the unit capacitors of the energy storage capacitors in the energy storage capacitor array are distributed to the outer ring of the capacitor array layout.
Optionally, the capacitance value of the energy storage capacitor is 62 times of the unit capacitance value.
The utility model provides a digital analog conversion circuit for successive approximation analog-to-digital converter, which comprises a high-order capacitor array, a scaling capacitor array, a low-order capacitor array, an energy storage capacitor array and a switch array; the low-order capacitor array comprises a low-order capacitor, and the high-order capacitor array comprises a high-order capacitor; the scaling capacitor array comprises a low-order supplementary capacitor, a high-order supplementary circuit and a bridging capacitor, and the low-order capacitor array is connected with one end of the comparator after being connected with the high-order capacitor array through the bridging capacitor; the other end of the comparator is connected with the energy storage capacitor array; the low-order capacitor, the low-order supplementary capacitor, the high-order capacitor and the high-order supplementary capacitor are all connected with the switch array; the low-order supplementary capacitor is connected with the low-order capacitor in parallel to adjust the common capacitance value of the low-order capacitor array and the low-order supplementary capacitor, so that the bridging capacitor is formed by connecting an integral number of unit capacitors in parallel.
By setting the low-order supplementary capacitor, the whole capacitance value of the low-order capacitor array and the low-order supplementary capacitor connected in parallel with the low-order supplementary capacitor array is adjusted, and the ratio of the capacitance value of the high-order capacitor array to the capacitance value of the low-order supplementary capacitor array can enable the bridging capacitor to be formed by connecting an integer number of unit capacitors in parallel, enable the capacitance value of the bridging capacitor to be integral multiple of the unit capacitance value, facilitate ingenious layout design and save the peripheral virtual capacitor of the original capacitor array. The design has the advantages of simple structure, reasonable layout, clear signal path and high matching degree, and realizes the analog-to-digital converter with better performance.
The utility model also provides an analog-to-digital conversion circuit has above-mentioned beneficial effect equally, no longer gives unnecessary details here.
Drawings
In order to clearly illustrate the embodiments or technical solutions of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a digital-to-analog conversion circuit for a successive approximation analog-to-digital converter in the prior art;
fig. 2 is a schematic structural diagram of a digital-to-analog conversion circuit for a successive approximation analog-to-digital converter according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a capacitor array layout provided in an embodiment of the present invention.
In the figure: 100. the capacitor array comprises a high-order capacitor array, a scaling capacitor array 200, a low-order capacitor array 300, an energy storage capacitor array 400 and a switch array 500.
Detailed Description
The core of the utility model is to provide a digital analog conversion circuit for successive approximation analog-to-digital converter. Referring to fig. 1, fig. 1 is a schematic structural diagram of a digital-to-analog conversion circuit for a successive approximation analog-to-digital converter in the prior art. In the prior art, as shown in fig. 1, in the structure, an upper seven-bit capacitor array and a lower five-bit capacitor array are cascaded through a bridging capacitor Cs, and assuming that a unit capacitor is C, then: c = 1/(1/Cs + 1/32C), thereby obtaining: 1/Cs =1/C-1/32C =31/32C, so that Cs =32C/31, thereby ensuring a twofold relationship between each bit from the upper to the lower.
The traditional capacitance analog-to-digital converter circuit can realize the digital-to-analog conversion function, but one of the main problems is that the bridging capacitance Cs is not an integral multiple of a unit capacitance, so that the matching is difficult in layout design, the precision is low, the weight relation of the analog-to-digital converter can be influenced, the nonlinearity is brought, and the traditional capacitance analog-to-digital converter circuit cannot overcome the problem and achieve high performance.
The utility model provides a digital-analog conversion circuit for digital-analog conversion circuit of successive approximation analog-digital converter, which comprises a high-order capacitor array, a scaling capacitor array, a low-order capacitor array, an energy storage capacitor array and a switch array; the low-order capacitor array comprises a low-order capacitor, and the high-order capacitor array comprises a high-order capacitor; the scaling capacitor array comprises a low-order supplementary capacitor, a high-order supplementary capacitor and a bridging capacitor, and the low-order capacitor array is connected with the high-order capacitor array through the bridging capacitor and then connected with one end of the comparator; the other end of the comparator is connected with the energy storage capacitor array; the low-order capacitor, the low-order supplementary capacitor, the high-order capacitor and the high-order supplementary capacitor are all connected with the switch array; the low-order supplementary capacitor is connected with the low-order capacitor in parallel to adjust the common capacitance value of the low-order capacitor array and the low-order supplementary capacitor, so that the bridging capacitor is formed by connecting an integral number of unit capacitors in parallel.
By setting the low-order supplementary capacitor, the whole capacitance value of the low-order capacitor array and the low-order supplementary capacitor connected in parallel with the low-order supplementary capacitor array is adjusted, and the ratio of the capacitance value of the high-order capacitor array to the capacitance value of the low-order supplementary capacitor array can enable the bridging capacitor to be formed by connecting an integer number of unit capacitors in parallel, enable the capacitance value of the bridging capacitor to be integral multiple of the unit capacitance value, facilitate ingenious layout design and save the peripheral virtual capacitor of the original capacitor array. The design has the advantages of simple structure, reasonable layout, clear signal path and high matching degree, and realizes the analog-to-digital converter with better performance.
In order to make the technical field better understand the solution of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings and the detailed description. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 2, fig. 2 is a schematic diagram of a digital-to-analog conversion circuit for a successive approximation type analog-to-digital converter according to an embodiment of the present invention.
Referring to fig. 2, in the embodiment of the present invention, the digital-to-analog conversion circuit includes a high-order capacitor array 100, a scaling capacitor array 200, a low-order capacitor array 300, an energy storage capacitor array 400, and a switch array 500; the low-order capacitor array 300 comprises low-order capacitors CL4 and CL3 \8230, CL1 and CL0, and the high-order capacitor array 100 comprises high-order capacitors CM6 and CM5 \8230, CM1 and CM0; the scaling capacitor array 200 comprises a low-order supplementary capacitor CL, a high-order supplementary capacitor CM and a bridge capacitor CS; the energy storage capacitor array 400 comprises energy storage capacitors CC; the switch array 500 comprises a plurality of single-pole triple-throw switches; the low-order capacitor array 300 is connected with the scaling capacitor array 200 and the switch array 500; the scaling capacitor array 200 is connected with the low-order capacitor array 300, the high-order capacitor array 100 and the switch array 500; the high-order capacitor array 100 is connected with the scaling capacitor array 200, the switch array 500 and the negative input end of the comparator; the switch array 500 is connected with the low-order capacitor array 300, the scaling capacitor array 200 and the high-order capacitor array 100; the energy storage capacitor array 400 is connected to the positive input of the comparator.
The high-order capacitor array 100 and the low-order capacitor array 300 mainly include capacitors corresponding to different weights in the whole digital-to-analog conversion circuit for the successive approximation analog-to-digital converter, for example, for a 12-bit successive approximation analog-to-digital converter, the high-order capacitor array 100 is designed as a seven-order capacitor array, that is, the high-order capacitor array 100 includes a 7-bit high-order capacitor; the corresponding low-order capacitor array 300 is designed as a low five-order capacitor array, that is, the low-order capacitor array 300 includes 5-bit low-order capacitors, so that the whole successive approximation type analog-to-digital converter respectively corresponds to 12-order capacitors with different weights. Of course, the number of capacitors specifically corresponding to the high-side capacitor array 100 and the low-side capacitor array 300 in the embodiment of the present invention is not specifically limited, as the case may be. In the embodiment of the present invention, it is necessary to ensure that the voltage of each capacitor from the high-order capacitor array 100 to the second-order capacitor array linearly changes in a twofold relationship, so as to function as a successive approximation type analog-to-digital converter.
Taking a 12-bit successive approximation type analog-to-digital converter as an example, the added low-order capacitor array 300 includes five capacitors from one capacitor to five capacitors, and the high-order capacitor array 100 includes seven capacitors from six capacitors to twelve capacitors, in order to ensure that the voltages of the twelve capacitors from one capacitor to twelve capacitors increase progressively with a twofold relationship, in the same capacitor array, for example, between the five capacitors from one capacitor to five capacitors of the low-order capacitor array 300, different numbers of unit capacitors can be set in parallel to realize the voltage increase progressively with a twofold relationship, for example, 1, 2, 4, 8, and 16 unit capacitors are set in parallel in sequence from one capacitor to five capacitors, and similarly, the high-order capacitor array 100 can set 1, 2, 4, 8, 16, 32, and 64 unit capacitors in parallel from six capacitors to twelve capacitors to realize the voltage increase progressively with a twofold relationship. The scaling capacitor array 200 is used to ensure that the voltages of the five, four, three, two, one-bit capacitors and the sixth-bit capacitor are decreased in a twofold relationship, thereby forming a successive approximation type analog-to-digital converter.
The scaling capacitor array 200 includes a low-level supplementary capacitor, a bridge capacitor and a high-level supplementary capacitor, and the low-level capacitor array 300 is connected to the high-level capacitor array 100 through the bridge capacitor and then connected to one end of the comparator. That is, the bridging capacitor is mainly used to realize the connection between the lower capacitor array 300 and the upper capacitor array 100, and the lower supplemental capacitor is mainly used to realize the adjustment of the capacitance corresponding to the bridging capacitor. The connected high-side capacitor array 100 and low-side capacitor array 300 are connected to an input terminal of the comparator, which is usually connected to the positive input terminal of the comparator; the other end of the comparator is connected to the storage capacitor array 400, which is usually connected to the negative input of the comparator. The storage capacitor array 400 is usually formed by a plurality of storage capacitors connected in parallel, and the storage capacitor array 400 is used for charging in the sampling phase and providing VCM voltage for the comparator in the comparison phase. The specific structure of the energy storage capacitor array 400 will be described in detail in the following embodiments, and will not be described herein again. For the specific structure of the comparator, reference may be made to the prior art, and details thereof are not repeated herein.
The high-order capacitor array 100, the scaling capacitor array 200, and the low-order capacitor array 300 are all required to be connected to the switch array 500, the switch array 500 generally includes a ground GND, a reference voltage signal line VREF, and an input/output voltage signal line VIN, each capacitor in the high-order capacitor array 100 and the low-order capacitor array 300 is required to be connected to a corresponding signal line in the switch array 500, and the specific connection manner thereof may be set according to the actual situation, and is not limited herein. The low-side supplemental capacitors are typically required to be connected to ground, while the bridge capacitors are typically not directly connected to the switch array 500.
Specifically, in the embodiment of the present invention, the energy storage capacitor array 400 includes energy storage capacitors; the switch array 500 includes a plurality of single pole, triple throw switches to perform its function; the low-order capacitor array 300 is connected with the scaling capacitor array 200 and the switch array 500; the scaling capacitor array 200 is connected with the low-order capacitor array 300, the high-order capacitor array 100 and the switch array 500; the high-order capacitor array 100 is connected with the scaling capacitor array 200, the switch array 500 and the negative input end of the comparator; the switch array 500 is connected with the low-order capacitor array 300, the scaling capacitor array 200 and the high-order capacitor array 100; the energy storage capacitor array 400 is connected to the positive input of the comparator.
In the embodiment of the present invention, the low-level supplementary capacitor is connected in parallel with the low-level capacitor to adjust the low-level capacitor array 300 and the common capacitance value of the low-level supplementary capacitor, so that the bridging capacitor is formed by connecting an integer number of unit capacitors in parallel, i.e. the capacitance value of the bridging capacitor is an integer multiple of the unit capacitance value. Details of the scaled capacitor array 200 will be described in the following embodiments, and will not be described herein.
Specifically, in the embodiment of the present invention, the scaling capacitor array 200 may further include a high-order supplementary capacitor, and the high-order supplementary capacitor is connected in parallel with the high-order capacitor. The high-order supplementary capacitor is specifically used for reducing each bit of capacitor, and comprises voltage changes of the first to twelfth bit of capacitors in the using process, so that the linearity is further optimized to a certain extent. The high-order supplementary capacitor needs to be connected with the high-order capacitor in parallel, and the high-order supplementary capacitor usually needs to be connected with a ground wire. The details of the high-side supplemental capacitor will be described in the following embodiments, and will not be described herein.
Specifically, in the embodiment of the present invention, the upper plates of the lower capacitors are connected together and connected to the upper plates of the lower supplementary capacitors and the upper plates of the bridging capacitors, and the lower plates of the lower capacitors are respectively connected to the external switch array 500 for distributing the charges with the lower weight; the upper pole plate of the low supplementary capacitor is connected with the upper pole plate of the bridging capacitor and the upper pole plate of the low capacitor, and the lower pole plate of the low supplementary capacitor is connected with the ground wire GND.
The upper plates of the high-order capacitors are usually connected together and connected with the lower plate of the bridging capacitor and the upper plate of the high-order supplementary capacitor, and the lower plates of the high-order capacitors are respectively connected with an external switch array 500 for distributing high-order weighted charges; the upper pole plate of the high-level supplementary capacitor is connected with the lower pole plate of the bridging capacitor and the upper pole plate of the high-level capacitor, and the lower pole plate of the high-level supplementary capacitor is connected with the ground wire GND.
The upper plate of the bridging capacitor is connected to the upper plate of the lower capacitor array 300 and the upper plate of the lower supplemental capacitor for adjusting the charge weight of the lower capacitor array 300 to maintain a double geometric array relationship with the upper capacitor array 100. The upper plate of the energy storage capacitor in the energy storage capacitor array 400 needs to be connected with the voltage of VCM, and the lower plate needs to be connected with the ground GND.
The embodiment of the utility model provides a digital analog conversion circuit for successive approximation analog to digital converter makes its bridging electric capacity be the integral multiple of unit electric capacity under the prerequisite of guaranteeing the weight relation of twice between every two digital analog converter to do benefit to ingenious domain design, saved the outlying virtual electric capacity of capacitor array originally. The design has the advantages of simple structure, reasonable layout, clear signal path and high matching degree, and realizes the analog-to-digital converter with better performance.
The present invention provides a specific structure of a digital-to-analog conversion circuit for a successive approximation analog-to-digital converter, which will be described in detail in the following embodiments of the present invention.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a capacitor array layout according to an embodiment of the present invention.
Be different from above-mentioned utility model embodiment, the embodiment of the utility model provides a on the basis of above-mentioned utility model embodiment, further prescribe a limit to the structure that is used for successive approximation analog-to-digital converter's digital analog conversion circuit. The rest of the contents have been described in detail in the above embodiments, and are not described again.
In the embodiment of the present invention, the low-order capacitor array 300 includes 5-bit low-order capacitor, and the high-order capacitor array 100 includes 7-bit high-order capacitor. That is, in the embodiment of the present invention, the low-order capacitor array 300 is a low five-order capacitor array, which includes low-order capacitors CL0 to CL4, and unit capacitors in the same bit are connected in parallel, and the number of unit capacitors per bit is 1, 2, 4, 8, and 16, respectively; correspondingly, the high-order capacitor array 100 is a high-order seven-order capacitor array, which comprises high-order capacitors CM 0-CM 6, unit capacitors in the same bit are connected in parallel, and the number of the unit capacitors per bit is 1, 2, 4, 8, 16, 32 and 64; correspondingly, the scaling capacitor array 200 includes a low-level supplementary capacitor CL, a bridging capacitor Cs and a high-level supplementary capacitor CM, in the embodiment of the present invention, the capacitance value of the bridging capacitor is 2 times the unit capacitance value; the capacitance value of the low-order supplementary capacitor is 31 times of unit capacitance value. That is, the bridge capacitor is formed by connecting two unit capacitors in parallel, and the ground complementary capacitor is formed by connecting 31 unit capacitors in parallel.
In the embodiment of the present invention, assume C mt The capacitance value of the capacitor array formed by the high-order capacitor array 100 and the high-order supplementary capacitor, i.e. C mt = high-order capacitor array 100+ high-order supplementary capacitor; cs is the capacitance value of the bridging capacitance, i.e., cs = bridging capacitance; c Lt The capacitance value of the capacitor array formed by the low-level capacitor array 300 and the low-level supplemental capacitor, i.e. C Lt = low-side capacitor array 300+ low-side supplemental capacitors; CM is the capacitance of high-order supplementary capacitor, CL is the capacitance of low-order supplementary capacitor, and the voltage change V of capacitor CM0 lower plate R Voltage change of CM0 upper plate to V o1 And the capacitance value of the unit capacitor is C, then:
V o1 ＝C(Cs+C Lt )×V R /(C mt ×(Cs+C Lt )+CsC Lt )；
if the voltage of the lower plate of the capacitor CL4 changes V R CL4 Upper plate Voltage variation V o2 Then, one can deduce:
V o2 ＝2 (5-1) ×Cs×C×V R /(C mt ×(Cs+C Lt )+CsC Lt )；
if it is desired to make V o1 ＝2V o2 And then:
Cs+C Lt ＝2×2 4 ×Cs×C；
when the bridge capacitance Cs is set to 2C, CL =31C can be obtained. At this time, the capacitance value of the bridging capacitor can be ensured to be integral multiple of the unit capacitor.
Further, the embodiment of the utility model provides a can be with the capacitance value design of high-order supplementary electric capacity CM for 16C, even make the capacitance value of high-order supplementary electric capacity 16 times unit capacitance value, form high-order supplementary electric capacity through 16 unit electric capacities are parallelly connected, it can be used for reducing the change of every electric capacity voltage, confirm through the emulation, increase behind the high-order supplementary electric capacity CM, every change of electric capacity has reduced about 100mv to the linearity has further been optimized to a certain extent.
Further, in the embodiment of the present invention, the unit capacitor is a mom capacitor. In the prior art, because the capacitance value of the bridge capacitor is not an integral multiple of the unit capacitor, a metal-insulator-metal (MIM) capacitor with low mismatch is generally selected in the prior art, but compared with a metal-oxide-metal (MOM) capacitor, the MIM capacitor has one layer of MASK (MASK) more than the MOM capacitor, and the manufacturing cost is increased. And because the embodiment of the utility model provides a can make bridging capacitance specifically to form by the parallelly connected of an integer unit electric capacity, consequently can specifically choose for use lower mom electric capacity of cost to effectively reduce successive approximation type analog to digital converter's cost of manufacture. Generally, mom capacitors as unit capacitors in the embodiments of the present invention are generally formed by using metal fingers of the same layer or different layers of metal, and the different layers of metal are connected by through holes at the ends of the plates.
Preferably, in the embodiment of the present invention, an isolation guard ring is disposed around the unit capacitor, and the isolation guard ring has the same metal level as that of the unit capacitor. That is, an isolation guard ring having the same level of metal as that of the surrounded unit capacitor may be further provided around the unit capacitor to surround the corresponding unit capacitor. So-called same level for example the embodiment of the present invention uses 5 layers of metal in a certain enclosed unit capacitor, and the isolation guard ring surrounding the unit capacitor also has 5 layers of metal to enclose the unit capacitor. The isolation guard ring needs to be connected with an independent ground potential to reduce the direct crosstalk of the capacitor and prevent the noise generated by other modules from being conducted to the digital-to-analog converter through a power supply and ground network.
In the embodiment of the present invention, the unit capacitor corresponding to the high-order capacitor array 100 is the unit capacitor corresponding to the scaling capacitor array 200 the unit capacitor corresponding to the low-order capacitor array 300 the unit capacitor corresponding to the energy storage capacitor array 400 is distributed to form the capacitor array layout, forming the unit capacitor of the energy storage capacitor in the energy storage capacitor array 400 is distributed in the outer ring of the capacitor array layout.
That is, in the embodiment of the present invention, each unit capacitor may be distributed in the form as shown in fig. 3, so as to form a capacitor array layout. It should be noted that, a certain distance is left between the rows of the capacitor array layout for placing the metal connection line as the connection line of the capacitor, the upper plate of each unit capacitor is usually used as the common terminal of the capacitor array, and the lower plate of each unit capacitor is usually used as the connection terminal of the capacitor. The embodiment of the utility model provides an in, form energy storage capacitor's unit capacitance distribution in energy storage capacitor array 400 in the outer lane of capacitor array territory, the outermost energy storage capacitor CC who has the round to connect VCM of capacitor array territory promptly.
In the prior art, in addition to the manufacturing cost increased by using the MIM capacitor, in the conventional capacitive digital-to-analog converter circuit, in order to ensure the consistency of the capacitor environment around the capacitor array, a circle of dummy capacitor generally needs to be drawn around the capacitor array, which increases the area of the capacitor array and also increases the manufacturing cost. The energy storage capacitor CC located at the outermost layer of the capacitor array layout can counteract charges introduced by a part of the negative end of the comparator due to clock feed-through effect in the sampling stage, can provide voltage with amplitude of VCM for the comparator in the conversion stage, and can be used as a virtual capacitor of the whole capacitor array on the layout, so that the consistency of the effective capacitor environment in the capacitor array layout is ensured.
As shown in fig. 3, the purpose of each capacitor setting in the embodiment of the present invention is to try to maintain the symmetry of the capacitor. Therefore, the bridging capacitor Cs is usually placed in the center, the low-level capacitors CL0 to CL4 are placed on the left side of the capacitor array layout, and the low-level supplementary capacitor CL surrounds the low-level capacitors CL0 to CL4 and is placed with the central axis of the bridging capacitor Cs as the symmetry axis; the high capacitors CM0 to CM6 are placed on the right side, and are also placed with the central axis of the bridging capacitor Cs as the symmetry axis, and since the number of the high capacitors is greater than that of the low capacitors, the capacitors at the position of CM6 surround the low capacitor array 300 and the high capacitor array 100. The outermost side of the capacitor array is provided with an energy storage capacitor CC, a part of the negative end of the comparator is offset by charges introduced due to the clock feed-through effect in the sampling stage, the voltage with the amplitude of VCM can be provided for the comparator in the conversion stage, and the capacitor array CC is used as a virtual capacitor of the capacitor array on the layout, so that the consistency of the effective capacitor environment in the layout of the capacitor array is ensured. Specifically, in the embodiment of the utility model, energy storage capacitor's capacitance value is 62 times unit capacitance value, and whole energy storage capacitor includes 62 unit electric capacity promptly, and it just in time can encircle the outmost a week of whole capacitor array territory to guarantee the uniformity of effective electric capacity environment in the capacitor array territory.
In the present specification, the embodiments are described in a progressive manner, and each embodiment focuses on differences from other embodiments, and the same or similar parts between the embodiments are referred to each other.
Finally, it should also be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
The present invention provides a digital-to-analog conversion circuit for successive approximation analog-to-digital converter, which is described in detail above. The principles and embodiments of the present invention have been explained herein using specific examples, and the above descriptions of the embodiments are only used to help understand the method and its core ideas of the present invention. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, the present invention can be further modified and modified, and such modifications and modifications also fall within the scope of the appended claims.
Claims (8)
1. A digital-to-analog conversion circuit for a successive approximation type analog-to-digital converter is characterized by comprising a high-order capacitor array, a scaling capacitor array, a low-order capacitor array, an energy storage capacitor array and a switch array;
the low-order capacitor array comprises a low-order capacitor, and the high-order capacitor array comprises a high-order capacitor; the scaling capacitor array comprises a low-order supplementary capacitor, a high-order supplementary capacitor and a bridging capacitor, the low-order capacitor array is connected with one end of a comparator after being connected with the high-order capacitor array through the bridging capacitor, and the energy storage capacitor array is connected with the other end of the comparator; the low-order capacitor, the low-order supplementary capacitor, the high-order capacitor and the high-order supplementary capacitor are all connected with the switch array; the high-order supplementary capacitor is connected with the high-order capacitor in parallel;
the low-order supplementary capacitor is connected with the low-order capacitor in parallel to adjust the common capacitance value of the low-order capacitor array and the low-order supplementary capacitor, so that the bridging capacitor is formed by connecting an integral number of unit capacitors in parallel.
2. The digital-to-analog conversion circuit for a successive approximation type analog-to-digital converter according to claim 1, wherein the lower capacitor array comprises a 5-bit lower capacitor, and the upper capacitor array comprises a 7-bit upper capacitor.
3. The DAC circuit of claim 2, wherein the bridge capacitor has a capacitance of 2 times the unit capacitance; the capacitance value of the low-order supplementary capacitor is 31 times of unit capacitance value.
4. The DAC circuit of claim 2 wherein the capacitance of the upper supplemental capacitor is 16 times the unit capacitance.
5. The digital-to-analog conversion circuit for a successive approximation type analog-to-digital converter according to claim 1, wherein the unit capacitance is a mom capacitance.
6. The digital-to-analog conversion circuit for a successive approximation type analog-to-digital converter according to claim 5, wherein an isolation guard ring is provided around the unit capacitor, the isolation guard ring having the same level of metal as that of the corresponding unit capacitor.
7. The digital-to-analog conversion circuit for a successive approximation type analog-to-digital converter according to claim 1, wherein the unit capacitors corresponding to the high-order capacitor array, the unit capacitors corresponding to the scaling capacitor array, the unit capacitors corresponding to the low-order capacitor array, and the unit capacitors corresponding to the energy storage capacitor array are distributed to form a capacitor array layout, and the unit capacitors forming the energy storage capacitors in the energy storage capacitor array are distributed to an outer ring of the capacitor array layout.
8. The digital-to-analog conversion circuit of claim 7, wherein the capacitance of the energy storage capacitor is 62 times the unit capacitance.
Priority Applications (1)
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