CN218160381U

CN218160381U - Display substrate and display device

Info

Publication number: CN218160381U
Application number: CN202221275781.1U
Authority: CN
Inventors: 倪柳松; 许程; 许晨; 赵策; 王明; 胡迎宾; 刘宁; 宋嘉文; 彭俊林; 何为
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2022-05-24
Filing date: 2022-05-24
Publication date: 2022-12-27
Anticipated expiration: 2032-05-24

Abstract

Provided are a display substrate and a display device. The display substrate includes: a plurality of pixel units arranged on the substrate; a first conductive layer disposed on the substrate; the buffer layer is arranged on one side, away from the substrate, of the first conducting layer; the semiconductor layer is arranged on one side of the buffer layer, which is far away from the substrate; the first insulating layer is arranged on one side, far away from the substrate, of the semiconductor layer; and the second conducting layer is arranged on one side, far away from the substrate, of the first insulating layer. The display substrate further comprises at least one conductive via and at least one conductive plug, the at least one conductive via at least penetrates through the first insulating layer, and the second conductive part is electrically connected with the first conductive part through the at least one conductive plug. The first conductive part comprises a first conductive sub-part and a second conductive sub-part, an orthographic projection of the first conductive sub-part on the substrate is at least partially overlapped with an orthographic projection of the at least one conductive via on the substrate, and the thickness of the first conductive sub-part along the third direction is larger than that of the second conductive sub-part along the third direction.

Description

Display substrate and display device

Technical Field

The disclosure relates to the technical field of display, in particular to a display substrate and a display device.

Background

An organic light emitting diode (abbreviated as OLED) display panel has the advantages of active light emission, good temperature characteristics, low power consumption, fast response, flexibility and the like, is gradually one of mainstream display technologies, and is increasingly widely applied to display devices such as mobile phones, computers, televisions and the like. In the design of the back plate of the OLED display panel, ensuring the transmittance of the light emitting region is one of the important issues for developers.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those skilled in the art.

SUMMERY OF THE UTILITY MODEL

In one aspect, there is provided a display substrate, including:

a substrate base plate;

a plurality of pixel units provided on the substrate, the plurality of pixel units being arranged in an array along a first direction and a second direction, at least one of the pixel units including a plurality of sub-pixels, at least one of the sub-pixels including a light emitting element and a pixel driving circuit for driving the light emitting element, wherein the first direction and the second direction intersect;

a first conductive layer disposed on the substrate base;

the buffer layer is arranged on one side, away from the substrate, of the first conducting layer;

the semiconductor layer is arranged on one side, away from the substrate, of the buffer layer;

the first insulating layer is arranged on one side, away from the substrate, of the semiconductor layer; and

a second conductive layer disposed on a side of the first insulating layer away from the substrate base,

wherein the pixel driving circuit comprises at least one transistor and a storage capacitor, the at least one transistor comprises a source electrode and a drain electrode, the storage capacitor comprises a first capacitor electrode and a second capacitor electrode which are oppositely arranged, one of the first capacitor electrode and the second capacitor electrode is positioned in the first conductive layer, and the source electrode and the drain electrode of the at least one transistor are positioned in the second conductive layer;

the display substrate comprises a first conductive part positioned in the first conductive layer and a second conductive part positioned in the second conductive layer, and the orthographic projection of the first conductive part on the substrate is at least partially overlapped with the orthographic projection of the second conductive part on the substrate;

the display substrate further comprises at least one conductive via and at least one conductive plug located in the at least one conductive via, the at least one conductive via at least penetrates through the first insulating layer, and the second conductive part is electrically connected with the first conductive part through the at least one conductive plug; and

the first conductive part comprises a first conductive sub-part and a second conductive sub-part, an orthographic projection of the first conductive sub-part on the substrate is at least partially overlapped with an orthographic projection of the at least one conductive via on the substrate, a thickness of the first conductive sub-part along a third direction is larger than a thickness of the second conductive sub-part along the third direction, and the third direction is perpendicular to a plane defined by the first direction and the second direction.

According to some exemplary embodiments, the first conductive sub-portion includes a first top surface remote from the base substrate, the second conductive sub-portion includes a second top surface remote from the base substrate, and the first top surface is further from the base substrate than the second top surface in the third direction.

According to some exemplary embodiments, the first conductive sub-portion includes a protrusion protruding toward the at least one conductive via relative to the second top surface of the second conductive sub-portion, and the at least one conductive plug contacts at least a portion of the first top surface of the first conductive sub-portion.

According to some exemplary embodiments, the buffer layer exposes at least a portion of the first conductive sub-portion; and/or, the buffer layer covers the second conductive sub-portion.

According to some exemplary embodiments, the buffer layer includes a third top surface remote from the substrate base plate, the first top surface of the first conductive sub-portion being substantially flush with a portion of the third top surface adjacent to the first conductive sub-portion.

According to some exemplary embodiments, the protrusion comprises a first side surface and a second side surface, the first side surface and the second side surface being located on opposite sides of the first top surface, the first top surface connecting the first side surface and the second side surface; and the buffer layer contacts and covers the second top surface, the first side surface, and the second side surface of the second conductive part.

According to some exemplary embodiments, the first conductive sub-portion includes a first bottom surface adjacent to the base substrate, the second conductive sub-portion includes a second bottom surface adjacent to the base substrate, and the first bottom surface and the second bottom surface are substantially flush in the third direction.

According to some exemplary embodiments, the second conductive portion includes a third bottom surface adjacent to the substrate base plate; a first distance is spaced in a third direction between the third bottom surface of the second conductive portion and the second top surface of the second conductive sub-portion at a location adjacent the at least one conductive via, the at least one conductive via having a depth in the third direction that is less than the first distance.

According to some exemplary embodiments, the first conductive part comprises a first conductive connection portion in the first conductive layer, at least a part of the first conductive connection portion serving as the second capacitance electrode; the second conductive part comprises a first conductive transfer part positioned in the second conductive layer; and the orthographic projection of the first conductive adapter part on the substrate base plate falls into the orthographic projection of the first conductive connecting part on the substrate base plate.

According to some exemplary embodiments, the at least one conductive via comprises a first conductive via, the at least one conductive patch comprises a first conductive patch, the first conductive patch is located in the first conductive via; the orthographic projection of the first conductive adapting part on the substrate base plate is at least partially overlapped with the orthographic projection of the first conductive through hole on the substrate base plate; and the orthographic projection of one part of the first conductive via hole on the substrate base plate is at least partially overlapped with the orthographic projection of the first sub-conductive part of the first conductive connecting part on the substrate base plate, one end of the first conductive plug is electrically connected with the first sub-conductive part of the first conductive connecting part, and the other end of the first conductive plug is electrically connected with the first conductive transfer part.

According to some exemplary embodiments, the at least one transistor comprises a driving transistor comprising a channel region; the display substrate further comprises a first semiconductor part positioned in the semiconductor layer, the first semiconductor part comprises a first source region, a first drain region and a channel region of the driving transistor, and the first source region and the first drain region are respectively positioned at two sides of the channel region of the driving transistor; an orthographic projection of the first conductive via on the substrate base plate at least partially overlaps an orthographic projection of one of the first source region and the first drain region on the substrate base plate; and one of the first source region and the first drain region is electrically connected to the first conductive via.

According to some exemplary embodiments, the first conductive part includes a second conductive connection part in the first conductive layer, the display substrate further includes a sensing signal line, and the second conductive connection part is electrically connected to the sensing signal line; the second conductive part comprises a second conductive transfer part positioned in the second conductive layer; and the orthographic projection of the second conductive adapting part on the substrate base plate is at least partially overlapped with the orthographic projection of the second conductive connecting part on the substrate base plate.

According to some exemplary embodiments, the at least one conductive via comprises a second conductive via, the at least one conductive patch comprises a second conductive patch, the second conductive patch being located in the second conductive via; the orthographic projection of the second conductive switching part on the substrate base plate is at least partially overlapped with the orthographic projection of the second conductive via hole on the substrate base plate; and the orthographic projection of one part of the second conductive via hole on the substrate base plate is at least partially overlapped with the orthographic projection of the first sub-conductive part of the second conductive connecting part on the substrate base plate, one end of the second conductive plug is electrically connected with the first sub-conductive part of the second conductive connecting part, and the other end of the second conductive plug is electrically connected with the second conductive transfer part.

According to some example embodiments, the at least one transistor comprises a sense transistor comprising a channel region; the display substrate further comprises a third semiconductor part positioned in the semiconductor layer, the third semiconductor part comprises a third source region, a third drain region and a channel region of the sensing transistor, and the third source region and the third drain region are respectively positioned at two sides of the channel region of the sensing transistor; an orthographic projection of the second conductive via on the substrate base plate at least partially overlaps with an orthographic projection of one of the third source region and the third drain region on the substrate base plate; and one of the third source region and the third drain region is electrically connected with the second conductive adapting part through the second conductive through hole.

According to some exemplary embodiments, the first conductive portion comprises a third conductive connection portion in the first conductive layer; the second conductive part comprises a third conductive transfer part positioned in the second conductive layer, the display substrate comprises a first power signal line positioned in the second conductive layer, and the third conductive connection part is a part of the first power signal line; and the orthographic projection of the third conductive adapter part on the substrate base plate is at least partially overlapped with the orthographic projection of the third conductive connecting part on the substrate base plate.

According to some exemplary embodiments, the at least one conductive via comprises a third conductive via, the at least one conductive patch comprises a third conductive patch, the third conductive patch being located in the third conductive via; an orthographic projection of the first power signal line on the substrate base plate is at least partially overlapped with an orthographic projection of the third conductive via on the substrate base plate; and the third conductive connecting portion includes two first sub-conductive portions, an orthographic projection of the third conductive via on the substrate base at least partially overlaps with an orthographic projection of one of the two first sub-conductive portions of the third conductive connecting portion on the substrate base, one end of the third conductive plug is electrically connected to one of the two first sub-conductive portions of the third conductive connecting portion, and the other end of the third conductive plug is electrically connected to the first power signal line.

According to some exemplary embodiments, the second conductive portion further comprises a fourth conductive interposer located in the second conductive layer; and the orthographic projection of the fourth conductive adapter part on the substrate base plate is at least partially overlapped with the orthographic projection of the third conductive connecting part on the substrate base plate.

According to some exemplary embodiments, the at least one conductive via comprises a fourth conductive via, the at least one conductive patch comprises a fourth conductive patch, the fourth conductive patch is located in the fourth conductive via; the orthographic projection of the fourth conductive adapting part on the substrate base plate is at least partially overlapped with the orthographic projection of the fourth conductive through hole on the substrate base plate; and the orthographic projection of the fourth conductive via hole on the substrate base plate is at least partially overlapped with the orthographic projection of the other of the two first sub-conductive parts of the third conductive connecting part on the substrate base plate, one end of the fourth conductive plug is electrically connected with the other of the two first sub-conductive parts of the third conductive connecting part, and the other end of the fourth conductive plug is electrically connected with the fourth conductive switching part.

According to some exemplary embodiments, the first conductive portion comprises a fourth conductive connection portion in the first conductive layer; the second conductive part comprises a fifth conductive transfer part positioned in the second conductive layer; and the orthographic projection of the fifth conductive adapting part on the substrate base plate is at least partially overlapped with the orthographic projection of the fourth conductive connecting part on the substrate base plate.

According to some exemplary embodiments, the at least one conductive via comprises a fifth conductive via, the at least one conductive plug comprises a fifth conductive plug, and the fifth conductive plug is located in the fifth conductive via; the orthographic projection of the fifth conductive adapter part on the substrate base plate is at least partially overlapped with the orthographic projection of the fifth conductive via hole on the substrate base plate; and the orthographic projection of the fifth conductive via hole on the substrate base plate is at least partially overlapped with the orthographic projection of the first sub-conductive part of the fourth conductive connecting part on the substrate base plate, one end of the fifth conductive plug is electrically connected with the first sub-conductive part of the fourth conductive connecting part, and the other end of the fifth conductive plug is electrically connected with the fifth conductive transfer part.

According to some exemplary embodiments, an orthographic projection of the fifth conductive via on the substrate base plate at least partially overlaps with an orthographic projection of the other of the third source region and the third drain region on the substrate base plate; and the other of the third source region and the third drain region is electrically connected with the fifth conductive transfer part through the fifth conductive via.

In another aspect, a display device is provided, which comprises the display substrate as described above.

Drawings

Other objects and advantages of the present disclosure will become apparent from the following description of the disclosure, which is made with reference to the accompanying drawings, and can assist in a comprehensive understanding of the disclosure.

Fig. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.

Fig. 2 is an equivalent circuit diagram of a pixel circuit of a single sub-pixel of the display substrate in fig. 1.

Fig. 3 to 13 are partial plan views of at least one film layer of a display substrate according to some exemplary embodiments of the present disclosure, respectively, in which fig. 3 schematically illustrates a partial plan view of a fourth conductive layer of the display substrate, fig. 4 schematically illustrates a partial plan view of a first conductive layer of the display substrate, fig. 5 schematically illustrates a partial plan view of a combination of the first conductive layer and the fourth conductive layer of the display substrate, fig. 6 schematically illustrates a partial plan view of a semiconductor layer of the display substrate, fig. 7 schematically illustrates a partial plan view of a combination of the fourth conductive layer, the first conductive layer, and the semiconductor layer of the display substrate, fig. 8 schematically illustrates a partial plan view of a third conductive layer of the display substrate, fig. 9 schematically illustrates a partial plan view of a combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, and the third conductive layer of the display substrate, fig. 10 schematically illustrates a partial plan view of a combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, the third conductive layer, and the first insulating layer of the display substrate, fig. 11 schematically illustrates a partial plan view of a combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, the third conductive layer, the first insulating layer, and the second insulating layer of the display substrate, fig. 12 schematically illustrates a partial plan view of the second conductive layer of the display substrate, and fig. 13 schematically illustrates a partial plan view of a combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, the third conductive layer, the first insulating layer, the second insulating layer, and the second conductive layer of the display substrate.

Fig. 14 is a cross-sectional view of a display substrate taken along line AA' in fig. 13, according to some exemplary embodiments of the present disclosure.

Fig. 15A to 15D are cross-sectional views of a display substrate according to some exemplary embodiments of the present disclosure taken along lines BB ', CC', DD ', EE' in fig. 4, respectively.

Fig. 16A to 16D are cross-sectional views of a display substrate according to some exemplary embodiments of the present disclosure taken along lines FF ', GG', HH ', II' of fig. 13, respectively, in which only an electrical connection relationship between a first conductive layer and a second conductive layer is illustrated, and other components are omitted.

Fig. 17 is a cross-sectional view of a display substrate taken along line JJ' in fig. 13, according to some exemplary embodiments of the present disclosure.

It is noted that, for the sake of clarity, in the drawings used to describe embodiments of the present disclosure, the dimensions of layers, structures or regions may be exaggerated or reduced, i.e., the drawings are not drawn to scale.

Detailed Description

The technical solution of the present disclosure is further specifically described below by way of examples and with reference to the accompanying drawings. In the specification, the same or similar reference numerals denote the same or similar components. The following description of the embodiments of the present disclosure with reference to the accompanying drawings is intended to explain the general inventive concept of the present disclosure and should not be construed as limiting the present disclosure.

Furthermore, in the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element or layer is referred to as being "formed on" another element or layer, it can be directly or indirectly formed on the other element or layer. That is, for example, intermediate elements or layers may be present. In contrast, when an element or layer is referred to as being "directly formed on" another element or layer, there are no intervening elements or layers present. Other words used to describe the relationship between elements or layers (e.g., "between" and "directly between 8230; adjacent" and "directly adjacent," etc.) should be interpreted in a similar manner.

Herein, the directional expressions "first direction" and "second direction" are used to describe different directions of the pixel arrangement, for example, a lateral direction and a longitudinal direction of the pixel arrangement. It is to be understood that such representation is by way of example only and is not intended as a limitation on the present disclosure.

In this context, unless otherwise specified, the expression "in the same layer" generally means: the first feature and the second feature may use the same material and may be formed by the same patterning process. The expression "a is integrally connected with B" means that part a and part B are integrally formed, i.e. they usually comprise the same material and are formed as one structurally continuous, unitary part.

The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices having the same characteristics. Since the source and drain of the thin film transistor used herein are symmetrical, the source and drain can be interchanged. In the following examples, description is made mainly in the case of a P-type thin film transistor serving as a driving transistor, and other transistors are of the same type as or different from the driving transistor depending on circuit design. Similarly, in other embodiments, the driving transistor may also be shown as an N-type thin film transistor.

Some exemplary embodiments of the present disclosure provide a display substrate, including: a base substrate; a plurality of pixel units provided on the substrate, the plurality of pixel units being arranged in an array along a first direction and a second direction, at least one of the pixel units including a plurality of sub-pixels, at least one of the sub-pixels including a light emitting element and a pixel driving circuit for driving the light emitting element; a semiconductor layer disposed on the substrate base plate; the first conducting layer is arranged on one side, close to the substrate, of the semiconductor layer; the second conducting layer is arranged on one side, far away from the substrate, of the semiconductor layer; and a pixel defining layer disposed on a side of the second conductive layer away from the substrate, the pixel defining layer including a plurality of openings for defining light emitting areas of a plurality of sub-pixels, wherein the pixel driving circuit includes a sensing transistor, a storage capacitor, and a capacitor trace, the sensing transistor includes a source and a drain, the storage capacitor includes a first capacitor electrode and a second capacitor electrode disposed opposite to each other, the capacitor trace is configured to electrically connect one of the source and the drain of the sensing transistor with the second capacitor electrode; the source electrode and the drain electrode of the sensing transistor are positioned in the second conductive layer, the second capacitance electrode and the capacitance routing wire are both positioned in the first conductive layer, and the capacitance routing wire comprises a capacitance routing main body part extending along a second direction; and for the same sub-pixel, the orthographic projection of the capacitance routing main body part of the pixel driving circuit of the sub-pixel on the substrate and the orthographic projection of the light emitting area of the sub-pixel on the substrate are arranged at intervals. In the embodiment of the disclosure, most of the capacitor wire (for example, the capacitor wire main body portion) is disposed outside the light emitting region of the sub-pixel, so that the shielding effect of the capacitor wire on the light emitted by the light emitting region can be reduced, and the light transmittance of the light emitting region can be improved. Thus, the display quality of the display substrate can be improved without affecting the driving of the sensing transistor.

Fig. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure, and fig. 14 is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure, schematically illustrating more specific structures of the display substrate. Referring to fig. 1 and 14 in combination, a display substrate according to an embodiment of the present disclosure may include a substrate 100, a pixel unit PX disposed on the substrate 100, a driving unit DRU disposed on the substrate 100 for driving the pixel unit PX, and a wire PL electrically connecting the pixel unit PX with the driving unit DRU.

The display substrate may include a display area AA and a non-display area NA. The display area AA may be an area where pixel units PX displaying an image are disposed. Each pixel unit PX will be described later. The non-display area NA is an area where the pixel unit PX is not disposed, that is, may be an area where an image is not displayed. A driving unit DRU for driving the pixel unit PX and some wirings PL connecting the pixel unit PX with the driving unit DRU may be disposed in the non-display area NA. The non-display area NA corresponds to a bezel in the final display device, and the width of the bezel may be determined according to the width of the non-display area NA.

The display area AA may have various shapes. For example, the display area AA may be provided in various shapes such as a closed shape including a straight side (e.g., a rectangle), a circle including a curved side, an ellipse, and the like, and a semicircle including a straight side and a curved side, a semi-ellipse, and the like. In the embodiment of the present disclosure, the display area AA is provided as one area having a quadrangular shape including straight sides, and it should be understood that this is only an exemplary embodiment of the present disclosure, and not a limitation of the present disclosure.

The non-display area NA may be disposed at least one side of the display area AA. In an embodiment of the present disclosure, the non-display area NA may surround the periphery of the display area AA. In an embodiment of the present disclosure, the non-display area NA may include a lateral portion extending in the first direction X and a longitudinal portion extending in the second direction Y.

The pixel unit PX is disposed in the display area AA. The pixel unit PX is a minimum unit for displaying an image, and may be provided in plurality. For example, the pixel unit PX may include a light emitting device emitting white light and/or colored light.

The pixel units PX may be disposed in plurality to be arranged in a matrix form along rows extending in the first direction X and columns extending in the first direction Y. However, the embodiment of the present disclosure does not particularly limit the arrangement form of the pixel units PX, and the pixel units PX may be arranged in various forms. For example, the pixel units PX may be arranged such that a direction inclined with respect to the first direction X and the first direction Y becomes a column direction, and a direction intersecting the column direction becomes a row direction.

One pixel unit PX may include a plurality of sub-pixels. For example, one pixel unit PX may include 3 sub-pixels, i.e., a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For another example, one pixel unit PX may include 4 sub-pixels, i.e., a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4. For example, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, the third sub-pixel SP3 may be a blue sub-pixel, and the fourth sub-pixel SP4 may be a white sub-pixel.

Each sub-pixel may include a light emitting element and a pixel driving circuit for driving the light emitting element. For example, the first subpixel SP1 may include a first light emitting element, which may emit red light, in the first light emitting area SPA1 and a first pixel driving circuit SPC1 for driving the first light emitting element; the second sub-pixel SP2 may include a second light emitting element in the second light emitting region SPA2, which may emit green light, and a second pixel driving circuit SPC2 for driving the second light emitting element; the third sub-pixel SP3 may include a third light emitting element in the third light emitting area SPA3, which may emit blue light, and a third pixel driving circuit SPC3 for driving the third light emitting element; the fourth sub-pixel SP4 may include a fourth light emitting element in the fourth light emitting region SPA4 and a fourth pixel driving circuit SPC4 for driving the fourth light emitting element.

The light emitting region of the sub-pixel may be a region where the light emitting element of the sub-pixel is located. For example, in an OLED display substrate, a light emitting element of a sub-pixel may include a first electrode (e.g., an anode), a light emitting material layer, and a second electrode (e.g., a cathode) that are stacked. Thus, the light emitting region of the sub-pixel may be a region corresponding to a portion of the light emitting material layer sandwiched between the anode and the cathode. For another example, in an OLED display substrate, the display substrate may include a pixel defining layer disposed on a substrate 100, and the pixel defining layer may include a plurality of openings corresponding to a plurality of sub-pixels, the plurality of openings respectively defining light emitting regions of the plurality of sub-pixels.

The sub-pixel further includes a non-light emitting region, for example, a portion of the pixel driving circuit of the sub-pixel is located in the non-light emitting region of the sub-pixel. The ratio of the area of the light-emitting region of each sub-pixel to the total area of the sub-pixel (the sum of the areas of the light-emitting region and the non-light-emitting region) determines the aperture ratio of the sub-pixel.

The uniformity of a light emitting device (e.g., a light emitting layer, abbreviated as an EL layer) of an OLED may not be good enough, for example, when the EL layer is formed by an evaporation process, the EL layer of each sub-pixel is not uniform due to the limitation of the evaporation process, and thus the luminance or chromaticity of the light emitting device is not uniform among different sub-pixels. Moreover, as the usage time increases, the EL layer may age differently, and the EL layers of the respective sub-pixels may not be uniform, thereby causing non-uniformity in light emission luminance or chromaticity among the sub-pixels. In an embodiment of the present disclosure, the display substrate may further include a photosensitive circuit OSC that may sense light actually emitted from the pixel unit. In this way, in the embodiment of the disclosure, the display substrate may optically compensate the sub-pixels in each pixel unit based on the light actually emitted by the pixel unit sensed by the light sensing circuit OSC, so as to improve the uniformity of the light emission of the display substrate.

For example, in some exemplary embodiments of the present disclosure, one photometry circuit OSC is disposed in each pixel unit PX. Each of the photometric circuits OSC senses light actually emitted from the pixel unit PX in which it is located.

For example, in an embodiment of the present disclosure, at least two pixel units PX may share one photosensitive circuit OSC. In the pixel units in the same column, two pixel units PX located in two adjacent rows may share one photosensitive circuit OSC. Thus, it is not necessary to provide one photosensitive circuit for each pixel unit PX, the number of photosensitive circuits can be reduced, and the aperture ratio can be improved.

The light sensing circuit OSC may sense light actually emitted from 2 pixel cells adjacent thereto when the display substrate is in a display state. For example, the photosensitive circuit OSC may include at least a photoelectric conversion element. As such, the photosensitive circuit OSC may be configured to: sensing light actually emitted from 2 pixel units adjacent to the sensing unit; and transmitting a sensing electrical signal according to the sensed light.

For another example, referring to fig. 1, the light sensing circuit OSC may transmit the sensing electrical signal to an external circuit, such as a control IC of the display device. The control IC may control a control signal transmitted to the pixel unit PX according to the sensing electric signal, for example, may control a data signal (i.e., a data signal) transmitted to a pixel driving circuit of each sub-pixel. Under the control of the data signal, each sub-pixel emits light accordingly.

In the embodiment shown in fig. 1, the sub-pixels SP1, SP2, SP3, SP4 are arranged side by side, and each sub-pixel SP1, SP2, SP3, SP4 may have a respective data line DL.

Fig. 2 is an equivalent circuit diagram of a pixel circuit of a single sub-pixel of the display substrate in fig. 1. The pixel driving circuit shown in fig. 2 may be any one of the pixel driving circuits SPC1, SPC2, SPC3, SPC4 described above. Referring to fig. 2, the pixel driving circuit may include a plurality of elements such as a driving transistor T1, a switching transistor T2, a sensing transistor T3, and a storage capacitor Cst. The pixel driving circuit may be referred to as a 3T1C structure.

It should be noted that, the pixel driving circuit included in the display substrate according to the embodiment of the present disclosure is described here by taking a 3T1C structure as an example, but the pixel driving circuit included in the display substrate according to the embodiment of the present disclosure is not limited to the 3T1C structure.

Continuing to refer to fig. 2, the gate g2 of the switching transistor T2 is electrically connected to the first scanning signal line GL1, the first electrode of the switching transistor T2 is electrically connected to the data line DL, and the second electrode of the switching transistor T2 is electrically connected to the gate g1 of the driving transistor T1, for example, the second electrode of the switching transistor T2 and the gate g1 of the driving transistor T1 may both be electrically connected to the node GN. The switching transistor T2 is used to control writing of a voltage signal from the data line DL to the pixel driving circuit.

It should be noted that each transistor may include an active layer, a gate electrode, a first electrode (e.g., a source electrode), and a second electrode (e.g., a drain electrode). For example, the switching transistor T2 includes a gate g2 and an active layer ACT2; the driving transistor T1 includes a gate g1 and an active layer ACT1; the sensing transistor T3 includes a gate g3 and an active layer ACT3. In an embodiment of the present disclosure, the active layer of the transistor may be located in a semiconductor layer, and the gate may be located in a conductive layer disposed in the semiconductor layer away from the substrate base plate.

It should be noted that, in this document, the first electrode of the transistor may refer to one of a source (e.g., s1, s2, s 3) and a drain (e.g., d1, d2, d 3) of the transistor, and the second electrode of the transistor may refer to the other of the source (e.g., s1, s2, s 3) and the drain (e.g., d1, d2, d 3) of the transistor.

The gate g1 of the driving transistor T1 is electrically connected to the node GN, the first electrode of the driving transistor T1 is electrically connected to a first power signal (e.g., a high voltage level signal VDD), and the second electrode of the driving transistor T1 can be electrically connected to the anode of the light emitting element OLED, so that a driving current can be generated according to the voltage signal to drive the light emitting element OLED to emit light. For example, the light emitting element OLED may be an Organic Light Emitting Diode (OLED).

Both ends of the storage capacitor Cst are electrically connected to the gate electrode g1 and the drain electrode d1 of the driving transistor T1, respectively, for storing the voltage signal input from the data line DL. For example, one end of the storage capacitor Cst is electrically connected to the node GN, and the other end of the storage capacitor Cst is electrically connected to the node SN. For example, the storage capacitor Cst may include a first capacitor electrode Cst1 and a second capacitor electrode Cst2. The first capacitor electrode Cst1 of the storage capacitor Cst, the second electrode (e.g., the drain electrode d 2) of the switching transistor T2, and the gate electrode g1 of the driving transistor T1 are all electrically connected to the node GN, and the second capacitor electrode Cst2 of the storage capacitor Cst, the second electrode (e.g., the drain electrode d 1) of the driving transistor T1, and the anode of the light emitting element OLED are all electrically connected to the node SN.

The gate g3 of the sensing transistor T3 is electrically connected to the second scanning signal line GL2, a first electrode (e.g., the source s 3) of the sensing transistor T3 is electrically connected to the sensing signal line SL, and a second electrode (e.g., the drain d 3) of the sensing transistor T3 is electrically connected to the node SN. That is, the second capacitor electrode Cst2 of the storage capacitor Cst, the second electrode (e.g., the drain electrode d 1) of the driving transistor T1, the anode of the light emitting element OLED, and the second electrode (e.g., the drain electrode d 3) of the sensing transistor T3 are electrically connected to the node SN.

The anode of the light emitting element OLED is electrically connected to the node SN, and the cathode of the light emitting element OLED is electrically connected to a second power signal (e.g., a low voltage level signal VSS). The level signals VDD and VSS are dc voltage signals for providing necessary voltages for driving the light emitting element OLED to emit light.

Fig. 14 is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure, fig. 3 to 14 are partial plan views of at least one film layer of the display substrate according to some exemplary embodiments of the present disclosure, respectively, wherein fig. 3 schematically illustrates a partial plan view of a fourth conductive layer of the display substrate, fig. 4 schematically illustrates a partial plan view of a first conductive layer of the display substrate, fig. 5 schematically illustrates a partial plan view of a combination of the first conductive layer and the fourth conductive layer of the display substrate, fig. 6 schematically illustrates a partial plan view of a semiconductor layer of the display substrate, fig. 7 schematically illustrates a partial plan view of a combination of the fourth conductive layer, the first conductive layer, and the semiconductor layer of the display substrate, fig. 8 schematically illustrates a partial plan view of a third conductive layer of the display substrate, fig. 9 schematically illustrates a partial plan view of a combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, and the third conductive layer of the display substrate, fig. 10 schematically illustrates a partial plan view of a combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, the third conductive layer, and the first insulating layer of the display substrate, fig. 11 schematically illustrates a partial plan view of a combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, the third conductive layer, the first insulating layer, and the second insulating layer of the display substrate, fig. 12 schematically illustrates a partial plan view of the second conductive layer of the display substrate, and fig. 13 schematically illustrates a partial plan view of a combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, the third conductive layer, the first insulating layer, the second insulating layer, and the second conductive layer of the display substrate. Fig. 14 is a cross-sectional view of a display substrate taken along line AA' in fig. 13, according to some exemplary embodiments of the present disclosure. Fig. 15A to 15D are cross-sectional views of a display substrate according to some exemplary embodiments of the present disclosure taken along lines BB ', CC', DD ', EE' in fig. 4, respectively. Fig. 16A to 16D are cross-sectional views of a display substrate according to some exemplary embodiments of the present disclosure, taken along lines FF ', GG', HH ', II' in fig. 13, respectively, in which only the electrical connection relationship between the first conductive layer and the second conductive layer is shown, and other components are omitted. Fig. 17 is a cross-sectional view of a display substrate taken along line JJ' in fig. 13, according to some exemplary embodiments of the present disclosure.

Referring to fig. 3 to 17 in combination, the display substrate may include a plurality of conductive layers, a semiconductor layer, and a plurality of insulating layers. For convenience of description, the plurality of conductive layers are respectively described as a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer.

The display substrate may include: a substrate 100, a fourth conductive layer 40 disposed on the substrate 100, a third insulating layer IDL3 disposed on the side of the fourth conductive layer 40 away from the substrate 100, a first conductive layer 10 disposed on the side of the third insulating layer IDL3 away from the substrate 100, a buffer layer BFL disposed on the side of the first conductive layer 10 away from the substrate 100, a semiconductor layer ACT disposed on the side of the buffer layer BFL away from the substrate 100, a gate insulating layer GIL disposed on the side of the semiconductor layer ACT away from the substrate 100, a third conductive layer 30 disposed on the side of the gate insulating layer GIL away from the substrate 100, a first insulating layer IDL1 disposed on the side of the third conductive layer 30 away from the substrate 100, a second conductive layer 20 disposed on the side of the first insulating layer IDL1 away from the substrate 100, a second insulating layer IDL2 disposed on the side of the second insulating layer IDL 20 away from the substrate 100, a first electrode layer 300 disposed on the side of the first electrode layer 300 away from the substrate 100, a pixel definition layer PDL disposed on the side of the pixel definition layer 100, and a light emitting layer PDL disposed on the side of the substrate 100 away from the second insulating layer EL layer 100.

Each of the insulating layers may have a single-layer structure or a stacked-layer structure including a plurality of insulating layers. For example, the second insulation layer IDL2 may include at least one passivation layer and at least one planarization layer. The specific structure of the insulating layer is not particularly limited in the embodiments of the present disclosure.

Referring to fig. 3, a partial plan view of the fourth conductive layer 40 is schematically shown. The material of the fourth conductive layer 40 may include a transparent conductive material, such as Indium Tin Oxide (ITO). For example, the first capacitive electrode Cst1 or the second capacitive electrode Cst2 of the storage capacitor Cst may be located in the first conductive layer 10. In the embodiment of the present disclosure, the display substrate may further include a capacitor trace 5 for electrically connecting the storage capacitor Cst and the sensing transistor T3, and specifically, the capacitor trace 5 may be used for electrically connecting the first capacitor electrode Cst1 or the second capacitor electrode Cst2 of the storage capacitor Cst and one of the source electrode s3 and the drain electrode d3 of the sensing transistor T3. As shown in fig. 3, the capacitive trace 5 may include a first connection portion 51, a second connection portion 53 and a capacitive trace body portion 52. The capacitor trace main body portion 52 extends along the second direction Y, and the capacitor trace main body portion 52 is located between the first connection portion 51 and the second connection portion 53. The first connection portion 51 is connected to the first capacitive electrode Cst1 or the second capacitive electrode Cst2, and the second connection portion 53 is electrically connected to one of the source electrode s3 and the drain electrode d3 of the sensing transistor T (which will be described in detail below).

In some exemplary embodiments of the present disclosure, the first or second capacitive electrode Cst1 or Cst2 and the capacitive trace 5 are formed as a continuously extending integral structure for the same sub-pixel. For example, as shown in fig. 3, a partial plan view of the fourth conductive layer 40 of 4 sub-pixels located in the same pixel unit is schematically shown. For each sub-pixel, the first capacitive electrode Cst1 or the second capacitive electrode Cst2 has a block pattern with a relatively large area, the capacitive trace 5 has a bar pattern with a relatively large aspect ratio, and the block pattern and the bar pattern are connected to each other to form a continuously extending integral structure. Thus, the second capacitor electrode and the capacitor wire on the same layer can be formed through the same patterning process.

It is to be noted that, in this document, unless otherwise specifically stated, the expression "continuously extending integral structure" means that at least 2 parts located in the same layer extend continuously without being interrupted in the middle, that is, at least 2 ends close to each other are connected to each other in the at least 2 parts.

For the same sub-pixel, an orthographic projection of the first capacitive electrode Cst1 or the second capacitive electrode Cst2 of the pixel driving circuit of the sub-pixel on the substrate 100 at least partially overlaps an orthographic projection of the light emitting area of the sub-pixel on the substrate 100.

Referring to fig. 4 and 5 in combination, the material of the first conductive layer 10 may include a light shielding material, for example, a metal material. In an embodiment of the present disclosure, the display substrate may further include a first conductive connection part 11, a second conductive connection part 12, a third conductive connection part 13, and a fourth conductive connection part 14 in the first conductive layer 10. The first conductive connection portion 11, the second conductive connection portion 12, the third conductive connection portion 13, and the fourth conductive connection portion 14 are disposed at intervals for the same sub-pixel.

For the same sub-pixel, an orthogonal projection of the first conductive connection portion 11 on the substrate 100 at least partially overlaps an orthogonal projection of the first capacitive electrode Cst1 or the second capacitive electrode Cst2 located in the fourth conductive layer 40 on the substrate 100, an orthogonal projection of the fourth conductive connection portion 14 on the substrate 100 at least partially overlaps an orthogonal projection of the capacitive trace 5 on the substrate 100, for example, an orthogonal projection of the fourth conductive connection portion 14 on the substrate 100 at least partially overlaps an orthogonal projection of the second connection portion 53 of the capacitive trace 5 on the substrate 100. An orthogonal projection of each of the second and third

conductive connection parts

12 and 13 on the substrate 100 does not overlap an orthogonal projection of each of the second capacitive electrode Cst2 and the capacitive trace 5 on the substrate 100.

In an embodiment of the present disclosure, the display substrate includes a first conductive portion in the first conductive layer 10. The first conductive part may include at least one of a first conductive connection part 11, a second conductive connection part 12, a third conductive connection part 13, and a fourth conductive connection part 14. The structure of the first conductive portion will be described further below with reference to the drawings.

It should be noted that, in the embodiment of the present disclosure, the first capacitor electrode Cst1 or the second capacitor electrode Cst2 of the storage capacitor Cst may be located in the first conductive layer 10. For example, at least a portion of the first conductive connection part 11 may function as the first capacitive electrode Cst1 or the second capacitive electrode Cst2.

Referring to fig. 6, a partial plan view of the semiconductor layer ACT is schematically shown. Referring to fig. 7, a partial plan view of the fourth conductive layer 40, the first conductive layer 10, and the semiconductor layer ACT is schematically illustrated. In an embodiment of the present disclosure, the semiconductor layer ACT may include various types of semiconductor materials, for example, amorphous silicon semiconductor material, polycrystalline silicon semiconductor material, and metal oxide semiconductor material. Referring to fig. 6 and 7 in combination, in an embodiment of the present disclosure, the display substrate may further include a first semiconductor portion 301, a second semiconductor portion 302, and a third semiconductor portion 303 in the semiconductor layer ACT. The first capacitor electrode Cst1 or the second capacitor electrode Cst2 of the storage capacitor Cst may be located in the semiconductor layer ACT.

It should be noted that, referring to fig. 15 and 17, in the embodiment of the present disclosure, one of the first and second capacitive electrodes Cst1 and Cst2 of the storage capacitor Cst may be located in the first conductive layer 10, for example, may be at least a part of the first conductive connection 11. The other of the first and second capacitive electrodes Cst1 and Cst2 of the storage capacitor Cst may be located in at least one of the fourth conductive layer 40 and the semiconductor layer ACT, for example, the other of the first and second capacitive electrodes Cst1 and Cst2 may include a block-shaped pattern portion in the fourth conductive layer 40, or the other of the first and second capacitive electrodes Cst1 and Cst2 may include a portion of the semiconductor layer ACT that is made conductive, or the other of the first and second capacitive electrodes Cst1 and Cst2 may include both a block-shaped pattern portion in the fourth conductive layer 40 and a portion of the semiconductor layer ACT that is made conductive (e.g., may be a doped semiconductor portion).

For the same sub-pixel, an orthographic projection of the first capacitive electrode Cst1 of the storage capacitor Cst on the substrate 100 at least partially overlaps an orthographic projection of the second capacitive electrode Cst2 of the storage capacitor Cst on the substrate 100, so that the first capacitive electrode Cst1 and the second capacitive electrode Cst2 are oppositely disposed to form the storage capacitor Cst.

For example, the first semiconductor portion 301 corresponds to the driving transistor T1, the first semiconductor portion 301 may include a source region 301s, a drain region 301d and a channel region 301c, the channel region 301c is a channel region of the driving transistor T1, and the source region 301s and the drain region 301d correspond to the source s1 and the drain d1 of the driving transistor T1, respectively. It is to be understood that the channel region may have a semiconductor property, and the source region and the drain region may be semiconductor portions which are treated with a conductor, for example, may be semiconductor portions which are treated with a dopant.

For example, the second semiconductor portion 302 corresponds to the switch transistor T2, and the second semiconductor portion 302 may include a source region 302s, a drain region 302d, and a channel region 302c, where the channel region 302c is a channel region of the switch transistor T2, and the source region 302s and the drain region 302d correspond to the source s2 and the drain d2 of the switch transistor T2, respectively.

For example, the third semiconductor portion 303 corresponds to the sensing transistor T3, and the third semiconductor portion 303 may include a source region 303s, a drain region 303d, and a channel region 303c, the channel region 303c being a channel region of the sensing transistor T3, the source region 303s and the drain region 303d corresponding to the source s3 and the drain d3 of the sensing transistor T3, respectively.

In some exemplary embodiments of the present disclosure, for the same sub-pixel, an orthogonal projection of the first semiconductor part 301 on the substrate 100 at least partially overlaps an orthogonal projection of the first conductive connection part 11 on the substrate 100, and an orthogonal projection of the first semiconductor part 301 on the substrate 100 at least partially overlaps an orthogonal projection of the first or second capacitive electrode Cst1 or Cst2 on the substrate 100. For example, for the same sub-pixel, the orthographic projection of the first semiconductor portion 301 on the substrate 100 falls within the orthographic projection of the first conductive connecting portion 11 on the substrate 100, and the orthographic projection of the first semiconductor portion 301 on the substrate 100 falls within the orthographic projection of the first capacitive electrode Cst1 or the second capacitive electrode Cst2 on the substrate 100.

In some exemplary embodiments of the present disclosure, for the same sub-pixel, an orthogonal projection of the third semiconductor portion 303 on the base substrate 100 at least partially overlaps an orthogonal projection of the second conductive connection portion 12 on the base substrate 100, and an orthogonal projection of the third semiconductor portion 303 on the base substrate 100 at least partially overlaps an orthogonal projection of the fourth conductive connection portion 14 on the base substrate 100. For example, for the same sub-pixel, the orthographic projection of one end of the third semiconductor portion 303 on the substrate 100 at least partially overlaps with the orthographic projection of the second conductive connection portion 12 on the substrate 100, and the orthographic projection of the other end of the third semiconductor portion 303 on the substrate 100 at least partially overlaps with the orthographic projection of the fourth conductive connection portion 14 on the substrate 100.

Referring to fig. 8, a partial plan view of the third conductive layer 30 is schematically shown. Referring to fig. 9, a partial plan view of the fourth conductive layer 40, the first conductive layer 10, the semiconductor layer ACT, and the third conductive layer 30 is schematically shown. In an embodiment of the present disclosure, the third conductive layer 30 may include various types of gate materials. With reference to fig. 8 and 9, in the embodiment of the present disclosure, the display substrate may further include a first gate conductor portion 31, a second gate conductor portion 32, a first auxiliary trace 33, a second auxiliary trace 34, and a third auxiliary trace 35 located in the third conductive layer 30. The display substrate may further include first and second scanning signal lines GL1 and GL2 for supplying gate scanning signals, and the first and second scanning signal lines GL1 and GL2 are located in the third conductive layer 30.

For example, the first gate conductor portion 31 corresponds to the driving transistor T1, and an orthogonal projection of the first gate conductor portion 31 on the substrate 100 at least partially overlaps an orthogonal projection of the first semiconductor portion 301 (for example, the channel region 301c of the driving transistor T1) on the substrate 100. A portion of the first gate conductor portion 31 overlapping the channel region 301c of the driving transistor T1 forms a gate g1 of the driving transistor T1.

For example, the first scanning signal line GL1 corresponds to the switching transistor T2, and an orthogonal projection of the first scanning signal line GL1 on the substrate 100 at least partially overlaps an orthogonal projection of the second semiconductor portion 302 (e.g., the channel region 302c of the switching transistor T2) on the substrate 100. A portion of the first scanning signal line GL1 overlapping the channel region 302c of the switching transistor T2 forms a gate g2 of the switching transistor T2. For example, the first scanning signal line GL1 includes a protrusion protruding in the second direction Y, which is the second gate conductor portion 32. In the embodiment of the present disclosure, the first scanning signal line GL1 is located below the channel region 302c of the switching transistor T2 in the second direction Y, and the second gate conductor portion 32 of the first scanning signal line GL1 extends toward the channel region 302c of the switching transistor T2 in an upward direction.

For example, the second scanning signal line GL2 corresponds to the sensing transistor T3, and an orthogonal projection of the second scanning signal line GL2 on the substrate 100 at least partially overlaps an orthogonal projection of the third semiconductor portion 303 (e.g., the channel region 303c of the sensing transistor T3) on the substrate 100. A portion of the second scanning signal line GL2 overlapping the channel region 303c of the sensing transistor T3 forms a gate g3 of the sensing transistor T3.

In the embodiment of the disclosure, the first scanning signal line GL1 and the second scanning signal line GL2 extend substantially along the first direction X, and the first auxiliary trace 33, the second auxiliary trace 34 and the third auxiliary trace 35 extend substantially along the second direction Y.

In the embodiment of the present disclosure, the first scanning signal line GL1 and the second scanning signal line GL2 for supplying the gate scanning signal to the pixel driving circuits of the same row of sub-pixels are respectively located at both sides of the light emitting area of the same row of sub-pixels in the second direction Y. For example, in the illustrated embodiment, the first and second scanning signal lines GL1 and GL2 for supplying gate scanning signals to the pixel driving circuits of the sub-pixels of the same row are respectively located on the upper and lower sides of the light emitting areas of the sub-pixels of the same row in the second direction Y.

Fig. 10 schematically shows a partial plan view of a combination of the fourth conductive layer, the first conductive layer, the semiconductor layer, the third conductive layer and the first insulating layer of the display substrate, and fig. 10 schematically shows some of the vias located in the first insulating layer IDL1.

Referring to fig. 10, the display substrate may include a first conductive via VH1 penetrating the first insulating layer IDL1. The first conductive via VH1 exposes a part of the first conductive connection portion 11. The first conductive via VH1 exposes at least a portion of the first conductive sub-portion 1101 of the first conductive connection portion 11. The first conductive via VH1 exposes the first source region 301s or the first drain region 301d of the driving transistor T1.

The display substrate may include a second conductive via VH2 penetrating the first insulating layer IDL1. The second conductive via VH2 exposes a part of the second conductive connection portion 12. The second conductive via VH2 exposes at least a portion of the first conductive sub-portion 1101 of the second conductive connection portion 12. The second conductive via VH2 exposes the third source region 303s or the third drain region 303d of the sensing transistor T3.

The display substrate may include a third conductive via VH3 penetrating the first insulating layer IDL1. The third conductive via VH3 exposes a part of the third conductive connection 13. The third conductive via VH3 exposes at least a portion of the first conductive sub-portion 1101 of the third conductive connection portion 13.

The display substrate may include a fourth conductive via VH4 penetrating the first insulating layer IDL1. The fourth conductive via VH4 exposes another portion of the third conductive connection 13. The fourth conductive via VH4 exposes at least a portion of the first conductive sub-portion 1101 of the fourth conductive via VH4.

The display substrate may include a fifth conductive via VH5 penetrating the first insulating layer IDL1. The fifth conductive via VH5 exposes a portion of the fourth conductive connection 14. The fifth conductive via VH5 exposes at least a portion of the first conductive sub-portion 1101 of the fifth conductive via VH5. The fifth conductive via VH5 exposes the third drain region 303d or the third source region 303s of the sensing transistor T3.

Referring to fig. 11, a partial plan view of the second conductive layer 20 is schematically shown. Referring to fig. 12, a partial plan view of the fourth conductive layer 40, the first conductive layer 10, the semiconductor layer ACT, the third conductive layer 30, the first insulating layer IDL1, and the second conductive layer 20 is schematically shown. In embodiments of the present disclosure, the second conductive layer 20 may include various types of source and drain materials. Referring to fig. 11 and 12 in combination, in an embodiment of the present disclosure, the display substrate may further include a first power signal line VDD, a data line DL, a sensing signal line SL, a first conductive interposer 21, a second conductive interposer 22, a third conductive interposer 23, a fourth conductive interposer 24, a fifth conductive interposer 25, and a sixth conductive interposer 26 in the second conductive layer 20. For the same sub-pixel, the first power signal line VDD, the data line DL, the sensing signal line SL, the first conductive patch 21, the second conductive patch 22, the fourth conductive patch 24, the fifth conductive patch 25, and the sixth conductive patch 26 are disposed at intervals from each other. The third conductive transition 23 is a part of the first power signal line VDD.

With combined reference to fig. 3 to 17, the display substrate includes a first conductive portion 110 located in the first conductive layer 10 and a second conductive portion 120 located in the second conductive layer 20, and an orthographic projection of the first conductive portion 110 on the substrate 100 at least partially overlaps an orthographic projection of the second conductive portion 120 on the substrate 100.

For example, the first conductive part 110 may be at least one of the first conductive connection part 11, the second conductive connection part 12, the third conductive connection part 13, and the fourth conductive connection part 14. The second conductive part 120 may be at least one of the first conductive transition part 21, the second conductive transition part 22, the third conductive transition part 23, the fourth conductive transition part 24, and the fifth conductive transition part 25.

The display substrate further comprises at least one conductive via VH running through at least the first insulating layer IDL1. For example, the at least one conductive via VH may be at least one of the first, second, third, fourth and fifth conductive vias VH1, VH2, VH3, VH4 and VH5 described above.

The display substrate may further comprise at least one conductive plug 1110 located in the at least one conductive via VH, and the second conductive portion 120 is electrically connected to the first conductive portion 110 through the at least one conductive plug 1110. With respect to the "conductive plug", it will be further described below in conjunction with the accompanying drawings.

Referring to fig. 14, the first conductive part 110 may include a first conductive sub-part 1101 and a second conductive sub-part 1102, an orthogonal projection of the first conductive sub-part 1101 on the substrate may at least partially overlap an orthogonal projection of the at least one conductive via VH on the substrate, and a thickness of the first conductive sub-part 1101 along a third direction Z perpendicular to a plane defined by the first direction X and the second direction Y is greater than a thickness of the second conductive sub-part 1102 along the third direction Z. That is, the first conductive sub-portion is a portion of the first conductive portion corresponding to the conductive via, and the second conductive sub-portion is another portion of the first conductive portion except the first conductive sub-portion. In an embodiment of the present disclosure, a thickness of the first conductive sub-portion is greater than a thickness of the second conductive sub-portion.

The first conductive sub-portion 1101 includes a first top surface 1101T remote from the substrate base plate 100, the second conductive sub-portion 1102 includes a second top surface 1102T remote from the substrate base plate 100, and the first top surface 1101T is further away from the substrate base plate 100 than the second top surface 1102T in the third direction Z.

With continued reference to fig. 14, the first conductive sub-portion 1101 includes a protrusion that protrudes relative to the second top surface 1102T of the second conductive sub-portion toward the at least one conductive via VH, and the at least one conductive plug 1110 contacts at least a portion of the first top surface 1101T of the first conductive sub-portion.

The buffer layer BFL exposes at least a portion of the first conductive sub-portion 1101. The buffer layer BFL covers the second conductive sub-part 1102. Specifically, the buffer layer BFL includes a third top surface BFLT remote from the substrate base plate 100, and the first top surface 1101T of the first conductive sub-section 1101 is substantially flush with a portion of the third top surface BFLT adjacent to the first conductive sub-section 1101.

It should be noted that, unless otherwise specified, the expression "substantially level" in this document means that the two objects to be compared are at the same height, or in the same horizontal plane, in the third direction Z; alternatively, the two objects to be compared have a certain height difference in the third direction Z, but the height difference is within ± 5 of the thickness of the body component to which the two objects to be compared belong. For example, herein, the first top surface 1101T being substantially flush with the third top surface BFLT may include: first top surface 1101T and third top surface BFLT may be at the same height in third direction Z, or the difference in height between first top surface 1101T and third top surface BFLT may be within ± 5a thickness of first conductive portion 110 or buffer layer BFL itself.

With continued reference to FIG. 14, the tab includes a first side 11011 and a second side 11012, the first side 11011 and the second side 11012 being located on opposite sides of the first top 1101T, the first top 1101T connecting the first side 11011 and the second side 11012. The buffer layer BFL contacts and covers the first and second side surfaces 11011 and 11012 and the second top surface 1102T of the second conductive part.

The first conductive sub-portion 1101 includes a first bottom surface 1101B adjacent to the substrate base plate 100, the second conductive sub-portion 1102 includes a second bottom surface 1102B adjacent to the substrate base plate 100, and the first bottom surface 1101B and the second bottom surface 1102B are substantially flush in the third direction Z. For example, herein, the first bottom surface 1101B and the second bottom surface 1102B being substantially flush may include: the first bottom surface 1101B and the second bottom surface 1102B are at the same height in the third direction Z, or the difference in height between the first bottom surface 1101B and the second bottom surface 1102B is within ± 5 of the thickness of the first conductive portion 110 or the buffer layer BFL itself.

With continued reference to fig. 14, the second conductive portion 120 includes a third bottom surface 120B proximate to the substrate base plate 100; the third bottom surface 120B of the second conductive portion is spaced apart from the second top surface 1102T of the second conductive sub-portion 1102 by a first distance H1 along the third direction Z at a location adjacent to the at least one conductive via VH, and a depth H2 of the at least one conductive via VH along the third direction Z is less than the first distance H1.

Referring to fig. 1 to 17, in some embodiments, the first conductive part 110 may include a first conductive connection part 11 in the first conductive layer 10. That is, the first conductive connection part 11 may include one first conductive sub-part 1101 and one second conductive sub-part 1102. The thickness of the first conductive sub-portion 1101 of the first conductive connection part 11 in the third direction Z is greater than the thickness of the second conductive sub-portion 1102 of the first conductive connection part 11 in the third direction Z.

It should be noted that, since the first conductive connecting portion 11 is a specific embodiment of the first conductive portion 110, the above description of the first conductive connecting portion can be applied to the first conductive connecting portion 11, and the specific structure of the first conductive connecting portion 11, especially the cross-sectional structure thereof, can be referred to the above description.

The second conductive portion 120 may include a first conductive via 21 in the second conductive layer 20. The orthographic projection of the first conductive adapting part 21 on the substrate base plate falls into the orthographic projection of the first conductive connecting part 11 on the substrate base plate.

In this embodiment, the at least one conductive via VH includes a first conductive via VH1, and the at least one conductive plug 1110 includes a first conductive plug 111, and the first conductive plug 111 is located in the first conductive via VH1. The orthographic projection of the first conductive adaptor 21 on the substrate base plate is at least partially overlapped with the orthographic projection of the first conductive via VH1 on the substrate base plate. For example, an orthographic projection of the first conductive interposer 21 on the substrate base plate 100 may cover an orthographic projection of the first conductive via VH1 on the substrate base plate 100. An orthographic projection of a part of the first conductive via VH1 on the substrate base is at least partially overlapped with an orthographic projection of the first sub-conductive portion 1101 of the first conductive connection portion 11 on the substrate base, one end of the first conductive plug 111 is electrically connected with the first sub-conductive portion 1101 of the first conductive connection portion 11, and the other end of the first conductive plug 11 is electrically connected with the first conductive adapting portion 21.

An orthographic projection of the first conductive via VH1 on the substrate base at least partially overlaps with an orthographic projection of one of the first source region 301s and the first drain region 301d on the substrate base. One of the first source region 301s and the first drain region 301d is electrically connected to the first conductive via 21 through the first conductive via VH1.

The source s1 or the drain d1 of the driving transistor T1 and the first capacitive electrode Cst1 or the second capacitive electrode Cst2 may be electrically connected by a via conductive structure such as the first conductive connection portion 11, the first conductive via VH1, and the first conductive via 21.

In some embodiments, the first conductive portion 110 may include a second conductive connection portion 12 in the first conductive layer 10. For example, one second conductive connection part 11 may include 2 first conductive sub-parts 1101 and one second conductive sub-part 1102. The thickness of the first conductive sub-portion 1101 of the second conductive connection portion 12 in the third direction Z is greater than the thickness of the second conductive sub-portion 1102 of the second conductive connection portion 12 in the third direction Z.

It should be noted that, since the second conductive connecting portion 12 is a specific embodiment of the first conductive portion 110, the above description of the first conductive portion can be applied to the second conductive connecting portion 12, and the specific structure of the second conductive connecting portion 12, especially the cross-sectional structure thereof, can be referred to the above description.

In the embodiment of the present disclosure, the second conductive connection part 12 is electrically connected to the sensing signal line SL.

The orthographic projection of the second conductive adapting part 22 on the substrate base plate is at least partially overlapped with the orthographic projection of the second conductive connecting part 12 on the substrate base plate.

The at least one conductive via VH comprises a second conductive via VH2, the at least one conductive plug 1110 comprises a second conductive plug 112, and the second conductive plug 112 is located in the second conductive via VH2.

The orthographic projection of the second conductive adaptor 22 on the substrate base plate is at least partially overlapped with the orthographic projection of the second conductive via VH2 on the substrate base plate.

An orthographic projection of a part of the second conductive via VH2 on the substrate base is at least partially overlapped with an orthographic projection of the first sub-conductive portion 1101 of the second conductive connection portion 12 on the substrate base, one end of the second conductive plug 112 is electrically connected to the first sub-conductive portion 1101 of the second conductive connection portion 12, and the other end of the second conductive plug 112 is electrically connected to the second conductive adaptor 22.

An orthogonal projection of the second conductive via VH2 on the substrate base at least partially overlaps with an orthogonal projection of one of the third source region 303s and the third drain region 303d on the substrate base. One of the third source region 303s and the third drain region 303d is electrically connected to the second conductive adaptor 22 through the second conductive via VH2.

In some embodiments, the first conductive portion 110 may include a third conductive connection portion 13 in the first conductive layer 10. For example, one third conductive connection part 13 may include 2 first conductive sub-parts 1101 and one second conductive sub-part 1102. The thickness of the first conductive sub-portion 1101 of the third conductive connection part 13 in the third direction Z is greater than the thickness of the second conductive sub-portion 1102 of the third conductive connection part 13 in the third direction Z.

It should be noted that, since the third conductive connecting portion 13 is a specific embodiment of the first conductive portion 110, the above description of the first conductive portion can be applied to the third conductive connecting portion 13, and the specific structure of the third conductive connecting portion 13, especially the cross-sectional structure thereof, can be referred to the above description.

In the embodiment of the present disclosure, the third conductive connection portion 23 is a part of the first power supply signal line VDD. The orthographic projection of the third conductive adapting part 23 on the substrate base plate is at least partially overlapped with the orthographic projection of the third conductive connecting part 13 on the substrate base plate.

The at least one conductive via VH comprises a third conductive via VH3, the at least one conductive plug 1110 comprises a third conductive plug 113, and the third conductive plug 113 is located in the third conductive via VH3.

An orthographic projection of the first power supply signal line VDD on the substrate base at least partially overlaps with an orthographic projection of the third conductive via VH3 on the substrate base.

One of the third conductive connection portions 13 includes two first sub-conductive portions 1101, an orthogonal projection of the third conductive via VH3 on the base substrate at least partially overlaps with an orthogonal projection of one of the two first sub-conductive portions 1101 of the third conductive connection portion 13 on the base substrate, one end of the third conductive plug 113 is electrically connected to one of the two first sub-conductive portions 1101 of the third conductive connection portion 13, and the other end of the third conductive plug 113 is electrically connected to the first power signal line VDD.

The orthographic projection of the fourth conductive adapting part 24 on the substrate base plate is at least partially overlapped with the orthographic projection of the third conductive connecting part 13 on the substrate base plate.

The at least one conductive via VH comprises a fourth conductive via VH4, the at least one conductive plug 1110 comprises a fourth conductive plug 114, and the fourth conductive plug 114 is located in the fourth conductive via VH4.

The orthographic projection of the fourth conductive adaptor 24 on the substrate base plate is at least partially overlapped with the orthographic projection of the fourth conductive via VH4 on the substrate base plate.

An orthographic projection of the fourth conductive via VH4 on the substrate base is at least partially overlapped with an orthographic projection of the other of the two first sub-conductive portions 1101 of the third conductive connection portion 13 on the substrate base, one end of the fourth conductive plug 114 is electrically connected to the other of the two first sub-conductive portions 1101 of the third conductive connection portion 13, and the other end of the fourth conductive plug 114 is electrically connected to the fourth conductive relay portion 24.

In some embodiments, the first conductive portion 110 may include a fourth conductive connection 14 in the first conductive layer 10. For example, a fourth conductive connection portion 14 may include a first conductive sub-portion 1101 and a second conductive sub-portion 1102. The thickness of the first conductive sub-portion 1101 of the fourth conductive connection portion 14 in the third direction Z is greater than the thickness of the second conductive sub-portion 1102 of the fourth conductive connection portion 14 in the third direction Z.

It should be noted that, since the fourth conductive connecting portion 14 is a specific embodiment of the first conductive portion 110, the above description of the first conductive portion can be applied to the fourth conductive connecting portion 14, and the specific structure of the fourth conductive connecting portion 14, especially the cross-sectional structure thereof, can be referred to the above description.

In the embodiment of the present disclosure, an orthogonal projection of the fifth conductive adapting portion 25 on the substrate base plate at least partially overlaps an orthogonal projection of the fourth conductive connecting portion 14 on the substrate base plate.

The at least one conductive via VH comprises a fifth conductive via VH5, the at least one conductive plug 1110 comprises a fifth conductive plug 115, and the fifth conductive plug 115 is located in the fifth conductive via VH5.

The orthographic projection of the fifth conductive adaptor 25 on the substrate base plate is at least partially overlapped with the orthographic projection of the fifth conductive via VH5 on the substrate base plate.

An orthographic projection of the fifth conductive via VH5 on the substrate base plate is at least partially overlapped with an orthographic projection of the first sub-conductive portion 1101 of the fourth conductive connecting portion 14 on the substrate base plate, one end of the fifth conductive plug 115 is electrically connected with the first sub-conductive portion 1101 of the fourth conductive connecting portion 14, and the other end of the fifth conductive plug 115 is electrically connected with the fifth conductive adapting portion 25.

An orthogonal projection of the fifth conductive via VH5 on the substrate base at least partially overlaps with an orthogonal projection of the other of the third source region 303s and the third drain region 303d on the substrate base. The other of the third source region 303s and the third drain region 303d is electrically connected to the fifth conductive adaptor 25 through the fifth conductive via VH5.

In the embodiment of the present disclosure, an orthogonal projection of the fifth conductive interposer 25 on the substrate base plate 100 at least partially overlaps an orthogonal projection of the fifth conductive via VH5 on the substrate base plate 100. For example, an orthogonal projection of the fifth conductive via 25 on the substrate base 100 may cover an orthogonal projection of the fifth conductive via VH5 on the substrate base 100. Through the switching conductive structure such as the fourth conductive connection portion 14, the fifth conductive via VH5 and the fifth conductive switching portion 25, the source s3 or the drain d3 of the sensing transistor T3 can be electrically connected to the capacitor trace 5.

In the embodiment of the present disclosure, an orthogonal projection of the sixth conductive adaptor 26 on the substrate base plate 100 at least partially overlaps an orthogonal projection of the seventh via VH7 on the substrate base plate 100, for example, the orthogonal projection of the sixth conductive adaptor 26 on the substrate base plate 100 may cover the orthogonal projection of the seventh via VH7 on the substrate base plate 100. The gate g1 of the driving transistor T1 and the second or first capacitive electrode Cst2 or Cst1 may be electrically connected by the via conductive structure of the seventh via VH7 and the sixth conductive via 26.

For example, the first power supply signal line VDD may be electrically connected to the source region s1 or the drain region d1 of the driving transistor T1 through the eighth via VH 8.

For example, in the embodiment of the present disclosure, for the same sub-pixel, an orthogonal projection of the data line DL on the substrate base 100 at least partially overlaps an orthogonal projection of the first auxiliary trace 33 on the substrate base 100, for example, the orthogonal projection of the data line DL on the substrate base 100 covers the orthogonal projection of the first auxiliary trace 33 on the substrate base 100. The data line DL may be electrically connected to the first auxiliary trace 33 through the tenth via VH 10. For example, a plurality of tenth vias VH10 may be arranged at intervals in the second direction Y, and the data line DL may be electrically connected to the first auxiliary trace 33 through the plurality of tenth vias VH10 arranged at intervals. In this way, the contact area between the data line DL and the first auxiliary trace 33 may be increased, thereby reducing the contact resistance and the voltage drop on the data line DL.

In the embodiment of the present disclosure, for the same sub-pixel, the orthogonal projection of the first auxiliary trace 33 electrically connected to the data line for supplying the data signal to the pixel driving circuit of the sub-pixel on the substrate 100 is spaced from the orthogonal projection of the capacitive trace main body portion 52 of the pixel driving circuit of the sub-pixel on the substrate 100.

For example, in the embodiment of the present disclosure, for the same sub-pixel, an orthogonal projection of the sensing signal line SL on the substrate 100 at least partially overlaps an orthogonal projection of the second auxiliary trace 34 on the substrate 100, for example, the orthogonal projection of the sensing signal line SL on the substrate 100 covers the orthogonal projection of the second auxiliary trace 34 on the substrate 100. The sensing signal line SL may be electrically connected to the second auxiliary trace 34 through the eleventh via VH 11. For example, a plurality of eleventh vias VH11 may be arranged at intervals in the second direction Y, and the sensing signal line SL may be electrically connected to the first auxiliary trace 33 through the plurality of eleventh vias VH11 arranged at intervals. In this way, the contact area between the sensing signal line SL and the second auxiliary trace 34 can be increased, thereby reducing the contact resistance and reducing the voltage drop on the sensing signal line SL.

For example, in the embodiment of the disclosure, for the same sub-pixel, an orthographic projection of the first power signal line VDD on the substrate 100 at least partially overlaps with an orthographic projection of the third auxiliary trace 35 on the substrate 100, for example, the orthographic projection of the first power signal line VDD on the substrate 100 covers the orthographic projection of the third auxiliary trace 35 on the substrate 100. The first power signal line VDD may be electrically connected to the third auxiliary trace 35 through the twelfth via VH 12. For example, a plurality of twelfth vias VH12 may be arranged at intervals in the second direction Y, and the first power signal line VDD may be electrically connected to the first auxiliary trace 33 through the plurality of twelfth vias VH12 arranged at intervals. In this way, the contact area between the first power signal line VDD and the first auxiliary trace 33 can be increased, thereby reducing the contact resistance and reducing the voltage drop on the first power signal line VDD.

For example, the data line DL may be electrically connected to the source region s2 or the drain region d2 of the switching transistor T2 through the ninth via VH 9.

In the embodiment of the present disclosure, 2 data lines DL are disposed between two adjacent sub-pixels located in the same row, for example, the two adjacent sub-pixels located in the same row include a first sub-pixel SP1 and a second sub-pixel SP2, and the 2 data lines include a first data line DL1 and a second data line DL2.

The first data line DL1 is used for supplying a data signal to the first sub-pixel SP1, and an orthographic projection of a data line main body portion of the data line DL1 for supplying a data signal to the pixel driving circuit of the first sub-pixel on the substrate is spaced from an orthographic projection of a capacitor wiring main body portion 52 of the pixel driving circuit of the first sub-pixel on the substrate.

The second data line DL2 is used for supplying a data signal to the second sub-pixel SP2, and an orthographic projection of a data line main body portion of the data line DL2 for supplying a data signal to the pixel driving circuit of the second sub-pixel on the substrate is spaced from an orthographic projection of a capacitor wiring main body portion 52 of the pixel driving circuit of the second sub-pixel on the substrate.

For example, the sensing signal line SL includes a first portion SL1 extending in the second direction Y and a second portion SL2 extending in the first direction X. In the first direction X, the second subpixel SP2 is adjacent to the sensing signal line SL, and the first subpixel SP1 is located at a side of the second subpixel SP2 away from the sensing signal line SL.

For example, one end of the second conductive connection part 12 is electrically connected to the other of the source s3 and the drain d3 of the sensing transistor T3 of the pixel driving circuit of the first sub-pixel SP1 through a second conductive via VH2, and the other end of the second conductive connection part 12 is electrically connected to the other of the source s3 and the drain d3 of the sensing transistor T3 of the pixel driving circuit of the second sub-pixel SP2 through a sixth via VH 6.

The second portion SL2 of the sensing signal line is electrically connected to the other end of the second conductive connection part 12 and the other of the source s3 and the drain d3 of the sensing transistor T3 of the pixel driving circuit of the second subpixel SP2 through a sixth via VH 6. In this way, the sensing signal supplied from the sensing signal line SL can be supplied to each sub-pixel of one pixel unit.

For example, the first power supply signal line VDD is located at a side of the first sub-pixel SP1 away from the second sub-pixel SP 2. The first power signal line VDD may be electrically connected to the source s1 or the drain d1 of the driving transistor T1 through the third conductive via VH3, the third conductive connection portion 13, the fourth conductive via VH4, and the fourth conductive transfer portion 24.

In the embodiment of the present disclosure, referring to fig. 14 and 17, the pixel define layer PDL includes a plurality of openings 80 for defining the light emitting regions SPA1, SPA2, SPA3, SPA4 of the plurality of sub-pixels.

Embodiments of the present disclosure also provide a display device, which may include the above display substrate. The display device may include, but is not limited to: any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. It is to be understood that the display device has the same advantageous effects as the display substrate provided in the foregoing embodiment.

Although a few embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A display substrate, comprising:

a base substrate;

a plurality of pixel units disposed on the substrate, the plurality of pixel units being arranged in an array along a first direction and a second direction, at least one of the pixel units including a plurality of sub-pixels, at least one of the sub-pixels including a light emitting element and a pixel driving circuit for driving the light emitting element, wherein the first direction and the second direction intersect;

a first conductive layer disposed on the substrate base;

a second conductive layer arranged on one side of the first insulating layer far away from the substrate base plate,

the first conductive part comprises a first conductive sub-part and a second conductive sub-part, an orthographic projection of the first conductive sub-part on the substrate is at least partially overlapped with an orthographic projection of the at least one conductive via on the substrate, and the thickness of the first conductive sub-part along a third direction is larger than that of the second conductive sub-part along the third direction, wherein the third direction is perpendicular to a plane defined by the first direction and the second direction.

2. The display substrate of claim 1, wherein the first conductive sub-portion includes a first top surface remote from the base substrate, the second conductive sub-portion includes a second top surface remote from the base substrate, the first top surface being further from the base substrate in the third direction than the second top surface.

3. The display substrate of claim 2, wherein the first conductive sub-portion includes a protrusion that protrudes relative to the second top surface of the second conductive sub-portion toward the at least one conductive via, the at least one conductive plug contacting at least a portion of the first top surface of the first conductive sub-portion.

4. The display substrate of any of claims 1-3, wherein the buffer layer exposes at least a portion of the first conductive sub-portion; and/or, the buffer layer covers the second conductive sub-portion.

5. The display substrate of claim 2 or 3, wherein the buffer layer includes a third top surface distal from the base substrate, the first top surface of the first conductive sub-portion being substantially flush with a portion of the third top surface adjacent to the first conductive sub-portion.

6. The display substrate of claim 3, wherein the protrusion comprises a first side surface and a second side surface, the first side surface and the second side surface being on opposite sides of the first top surface, the first top surface connecting the first side surface and the second side surface; and

the buffer layer contacts and covers the second top surface, the first side surface, and the second side surface of the second conductive part.

7. The display substrate of claim 5, wherein the first conductive sub-portion includes a first bottom surface proximate the base substrate, the second conductive sub-portion includes a second bottom surface proximate the base substrate, and the first and second bottom surfaces are substantially flush in the third direction.

8. The display substrate of claim 7, wherein the second conductive portion comprises a third bottom surface proximate to the substrate base; the third bottom surface of the second conductive portion is spaced apart from the second top surface of the second conductive sub-portion by a first distance in a third direction at a position adjacent to the at least one conductive via, and a depth of the at least one conductive via in the third direction is smaller than the first distance.

9. A display substrate according to any one of claims 1 to 3, wherein the first conductive part comprises a first conductive connection in the first conductive layer, at least a part of the first conductive connection serving as the second capacitive electrode;

the second conductive part comprises a first conductive transfer part positioned in the second conductive layer; and

the orthographic projection of the first conductive adapter part on the substrate base plate falls into the orthographic projection of the first conductive connecting part on the substrate base plate.

10. The display substrate of claim 9, wherein the at least one conductive via comprises a first conductive via, the at least one conductive plug comprises a first conductive plug, and the first conductive plug is located in the first conductive via;

the orthographic projection of the first conductive switching part on the substrate base plate is at least partially overlapped with the orthographic projection of the first conductive through hole on the substrate base plate; and

the orthographic projection of one part of the first conductive via hole on the substrate base plate is at least partially overlapped with the orthographic projection of the first sub-conductive part of the first conductive connecting part on the substrate base plate, one end of the first conductive plug is electrically connected with the first sub-conductive part of the first conductive connecting part, and the other end of the first conductive plug is electrically connected with the first conductive transfer part.

11. The display substrate of claim 10, wherein the at least one transistor comprises a drive transistor comprising a channel region;

the display substrate further comprises a first semiconductor part positioned in the semiconductor layer, the first semiconductor part comprises a first source region, a first drain region and a channel region of the driving transistor, and the first source region and the first drain region are respectively positioned at two sides of the channel region of the driving transistor;

an orthographic projection of the first conductive via on the substrate base plate at least partially overlaps an orthographic projection of one of the first source region and the first drain region on the substrate base plate; and

one of the first source region and the first drain region is electrically connected to the first conductive via.

12. The display substrate according to claim 11, wherein the first conductive portion comprises a second conductive connection portion in the first conductive layer, the display substrate further comprising a sensing signal line, the second conductive connection portion being electrically connected to the sensing signal line;

the second conductive part comprises a second conductive transfer part positioned in the second conductive layer; and

the orthographic projection of the second conductive adapting part on the substrate base plate is at least partially overlapped with the orthographic projection of the second conductive connecting part on the substrate base plate.

13. The display substrate of claim 12, wherein the at least one conductive via comprises a second conductive via, the at least one conductive plug comprises a second conductive plug, the second conductive plug is located in the second conductive via;

the orthographic projection of the second conductive switching part on the substrate base plate is at least partially overlapped with the orthographic projection of the second conductive via hole on the substrate base plate; and

the orthographic projection of one part of the second conductive via hole on the substrate base plate is at least partially overlapped with the orthographic projection of the first sub-conductive part of the second conductive connecting part on the substrate base plate, one end of the second conductive plug is electrically connected with the first sub-conductive part of the second conductive connecting part, and the other end of the second conductive plug is electrically connected with the second conductive transfer part.

14. The display substrate of claim 13, wherein the at least one transistor comprises a sense transistor comprising a channel region;

the display substrate further comprises a third semiconductor part positioned in the semiconductor layer, the third semiconductor part comprises a third source region, a third drain region and a channel region of the sensing transistor, and the third source region and the third drain region are respectively positioned at two sides of the channel region of the sensing transistor;

an orthographic projection of the second conductive via on the substrate base plate at least partially overlaps with an orthographic projection of one of the third source region and the third drain region on the substrate base plate; and

one of the third source region and the third drain region is electrically connected with the second conductive transfer part through the second conductive via hole.

15. The display substrate of claim 14, wherein the first conductive portion comprises a third conductive connection in the first conductive layer;

the second conductive part comprises a third conductive transfer part positioned in the second conductive layer, the display substrate comprises a first power signal line positioned in the second conductive layer, and the third conductive connection part is a part of the first power signal line; and

the orthographic projection of the third conductive adapting part on the substrate base plate is at least partially overlapped with the orthographic projection of the third conductive connecting part on the substrate base plate.

16. The display substrate of claim 15, wherein the at least one conductive via comprises a third conductive via, the at least one conductive patch comprises a third conductive patch, and the third conductive patch is located in the third conductive via;

an orthographic projection of the first power signal line on the substrate base plate is at least partially overlapped with an orthographic projection of the third conductive via on the substrate base plate; and

the third conductive connection portion includes two first sub-conductive portions, an orthographic projection of the third conductive via on the substrate base at least partially overlaps with an orthographic projection of one of the two first sub-conductive portions of the third conductive connection portion on the substrate base, one end of the third conductive plug is electrically connected to one of the two first sub-conductive portions of the third conductive connection portion, and the other end of the third conductive plug is electrically connected to the first power signal line.

17. The display substrate of claim 16, wherein the second conductive portion further comprises a fourth conductive interposer in the second conductive layer; and

the orthographic projection of the fourth conductive adapting part on the substrate base plate is at least partially overlapped with the orthographic projection of the third conductive connecting part on the substrate base plate.

18. The display substrate of claim 17, wherein the at least one conductive via comprises a fourth conductive via, the at least one conductive patch comprises a fourth conductive patch, and the fourth conductive patch is located in the fourth conductive via;

the orthographic projection of the fourth conductive switching part on the substrate base plate is at least partially overlapped with the orthographic projection of the fourth conductive via hole on the substrate base plate; and

the orthographic projection of the fourth conductive via hole on the substrate base plate is at least partially overlapped with the orthographic projection of the other of the two first sub conductive parts of the third conductive connecting part on the substrate base plate, one end of the fourth conductive plug is electrically connected with the other of the two first sub conductive parts of the third conductive connecting part, and the other end of the fourth conductive plug is electrically connected with the fourth conductive switching part.

19. The display substrate of claim 18, wherein the first conductive portion comprises a fourth conductive connection in the first conductive layer;

the second conductive part comprises a fifth conductive transfer part positioned in the second conductive layer; and

the orthographic projection of the fifth conductive adapting part on the substrate base plate is at least partially overlapped with the orthographic projection of the fourth conductive connecting part on the substrate base plate.

20. The display substrate of claim 19, wherein the at least one conductive via comprises a fifth conductive via, the at least one conductive plug comprises a fifth conductive plug, and the fifth conductive plug is located in the fifth conductive via;

the orthographic projection of the fifth conductive adapting part on the substrate base plate is at least partially overlapped with the orthographic projection of the fifth conductive through hole on the substrate base plate; and

the orthographic projection of the fifth conductive via hole on the substrate base plate is at least partially overlapped with the orthographic projection of the first sub-conductive part of the fourth conductive connecting part on the substrate base plate, one end of the fifth conductive plug is electrically connected with the first sub-conductive part of the fourth conductive connecting part, and the other end of the fifth conductive plug is electrically connected with the fifth conductive switching part.

21. The display substrate of claim 20, wherein an orthographic projection of the fifth conductive via on the substrate at least partially overlaps an orthographic projection of the other of the third source region and the third drain region on the substrate; and

the other of the third source region and the third drain region is electrically connected to the fifth conductive via.

22. A display device, characterized in that the display device comprises a display substrate according to any one of claims 1 to 21.