CN217770052U - Two-step single-slope analog-to-digital converter, reading circuit and image system - Google Patents
Two-step single-slope analog-to-digital converter, reading circuit and image system Download PDFInfo
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Abstract
The utility model provides a two step type monoclinic slope analog-to-digital converter, include: the ramp generator is used for generating a ramp control signal and adjusting the ramp control signal based on the control feedback signal so as to generate and output a ramp voltage; the comparator is used for comparing the ramp voltage with the pixel voltage and outputting a comparison result; the memory is connected with the comparison output end of the comparator and used for storing the value of the highest bit according to the comparison result in the coarse quantization stage; the digital control logic is connected with the output end of the memory and used for generating a control feedback signal and adjusting the control feedback signal according to the value of the highest bit to reset the ramp voltage; and the counter is connected with the comparison output end of the comparator and is used for carrying out quantization counting on the residual bits according to the comparison result in the fine quantization stage. Through the utility model discloses, the problem of current two steps SS ADC because of slope generator is in large number leads to CIS's area and consumption increase has been solved.
Description
Technical Field
The utility model relates to an integrated circuit design field especially relates to a two-step list slope analog-to-digital converter, reading circuit and image system.
Background
The Single Slope analog-to-digital converter (SS ADC) has a series of advantages of simple circuit structure, low noise, small area, low power consumption and the like, but the A/D conversion speed is slow, and 2 is needed for each n-bit A/D conversion n One clock period, which limits the readout speed of a CMOS Image Sensor (CIS), limits the enhancement of the resolution and frame rate of the CIS.
In order to increase the readout speed of the SS ADC, a two-step SS ADC concept is proposed, and a conventional two-step SS ADC quantization process is shown in fig. 1. The whole A/D conversion process is divided into two stages of coarse quantization and fine quantization, the high C bit (the high C bit and the low F bit can be set, for example, 11 bits ADC, the high C bit is generally selected as 3 bits, the low F bit is selected as 8 bits) is quantized first, and the corresponding quantization step Δ V is calculated C Is VREF/2 C The coarse quantization divides the quantization range VREF into 2 C And (4) voltage intervals. According to the coarse quantization result, the voltage range of the input signal can be determined, then a proper fine quantization signal is selected to be connected into the comparator, the low F bit quantization is completed, and the quantization step length delta V corresponding to the fine quantization is performed F Is (VREF/2) C )/2 F . Thus, for n-bit resolution, a two-step SS ADC is only required (2) C +2 F ) One clock cycle, where n = C + F.
The two-step SS ADC can greatly improve the A/D conversion speed, but the quantization range VREF is divided into 2 by coarse quantization C Voltage interval such that a conventional two-step SS ADC requires 2 C The slope generators perform fine quantization (coarse quantization can multiplex the fine quantization), the coarse quantization is generally designed to be 3 bits, that is, 8 slope generators are needed, the 8 slope generators can significantly increase the area and power consumption of the CIS, and in addition, the mismatch of slopes among the slopes can cause the reduction of linearity.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned shortcomings of the prior art, the present invention provides a two-step single-slope analog-to-digital converter, a readout circuit and an image system, which are used to solve the problem of increased area and power consumption of the CIS due to the large number of slope generators in the existing two-step SS ADC.
To achieve the above and other related objects, the present invention provides a two-step single slope analog-to-digital converter, comprising:
the ramp generator is used for generating a ramp control signal and adjusting the ramp control signal based on a control feedback signal so as to generate and output a ramp voltage;
the comparator is connected with the ramp voltage at a non-inverting input end, connected with the pixel voltage at an inverting input end and used for comparing the ramp voltage with the pixel voltage and outputting a comparison result;
the memory is connected with the comparison output end of the comparator and used for storing the value of the highest bit according to the comparison result in the coarse quantization stage;
the digital control logic is connected with the output end of the memory and used for generating the control feedback signal and adjusting the control feedback signal according to the value of the highest bit so as to reset the ramp voltage;
and the counter is connected with the comparison output end of the comparator and is used for carrying out quantization counting on the residual bits according to the comparison result in a fine quantization stage.
Optionally, the two-step single slope analog-to-digital converter further comprises:
the first coupling capacitor is connected between the ramp voltage and the non-inverting input end of the comparator;
and the second coupling capacitor is connected between the pixel voltage and the inverting input end of the comparator.
Optionally, the two-step single slope analog-to-digital converter further comprises:
the first zero clearing switch is connected between the in-phase input end and the in-phase output end of the comparator and is controlled by a zero clearing control signal;
and the second zero clearing switch is connected between the inverting input end and the inverting output end of the comparator and is controlled by the zero clearing control signal.
Optionally, the ramp generator is implemented by a current steering digital-to-analog converter.
Optionally, the ramp generator comprises: m group current control unit, load resistance and dummy resistance, wherein, M group the circuit structure of current control unit all includes: the circuit comprises a current source, a first control switch and a second control switch;
a power supply end of the current source is connected with a power supply voltage, an input end of the current source is connected with a bias voltage, an output end of the current source is connected with a first end of the first control switch and a first end of the second control switch, a second end of the first control switch is grounded through the load resistor and generates the ramp voltage, a second end of the second control switch is grounded through the dummy resistor, the first control switch is controlled by the ramp control signal, and the second control switch is controlled by an inverted signal of the ramp control signal; wherein M is a positive number greater than 1.
Optionally, the memory is a 1-bit memory and the counter is an (N-1) -bit counter; and N is the resolution of the two-step single-slope analog-to-digital converter.
The utility model also provides a readout circuit, readout circuit includes: a two-step single ramp analog to digital converter as claimed in any one of the preceding claims.
The utility model also provides an image system, image system includes: a readout circuit as described above.
As described above, the utility model discloses a two-step list slope analog-to-digital converter, reading circuit and image system have proposed a brand-new two-step list slope analog-to-digital conversion scheme, fall into the Most Significant Bit (MSB) of 1 bit and the surplus bit of (N-1) bit with N bit resolution, adopt the dichotomy to accomplish the quantization of MSB in the A/D conversion process for the first time, can reduce effectively and quantify the step and along with the improvement of ADC resolution, the conversion clock cycle of saving can increase gradually. According to the scheme, an additional ramp generator is not needed, and the quantization process of the two-step SS ADC can be completed only by utilizing one of the falling ramp voltage or the rising ramp voltage generated by the conventional ramp generator (namely, the conventional single-slope ADC is utilized, and only one ramp generator is needed). The ramp voltage used is not different from the traditional SS ADC, so that all the advantages of the traditional SS ADC are kept, the problems of the area, the power consumption and the linearity of the traditional two-step SS ADC are effectively solved, and the quantization speed of the SS ADC can be effectively increased on the premise of not influencing the area, the power consumption and the linearity of the CIS. In addition, the scheme is based on the traditional SS ADC architecture, so that reversible switching can be performed between the scheme and the traditional SS ADC algorithm without redesigning.
Drawings
Fig. 1 shows a waveform diagram of a conversion process corresponding to a conventional two-step SS ADC.
Fig. 2 is a schematic circuit diagram of the two-step single slope analog-to-digital converter according to the present invention.
Fig. 3 is a schematic circuit diagram of the slope generator of the present invention.
Fig. 4 shows a waveform diagram of a conversion process when MSB =1 corresponds to the conversion method of the present invention, wherein the ramp voltage is a falling ramp signal.
Fig. 5 shows a waveform diagram of a conversion process when MSB =0 corresponds to the conversion method of the present invention, wherein the ramp voltage is a falling ramp signal.
Description of the element reference
1. Readout circuit
10. Two-step single-slope analog-to-digital converter
100. Slope generator
101. Current control unit
200. Comparator with a comparator circuit
300. Memory device
400. Digital control logic
500. Counter with a counter body
2. Pixel circuit
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
Please refer to fig. 2 to 5. It should be noted that the drawings provided in the present embodiment are only for schematically illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
As shown in fig. 2, the present embodiment provides a two-step single-slope analog-to-digital converter 10, where the two-step single-slope analog-to-digital converter 10 includes: ramp generator 100, comparator 200, memory 300, digital control logic 400, and counter 500.
The ramp generator 100 is configured to generate a ramp control signal and adjust the ramp control signal based on the control feedback signal ramp _ az to generate and output a ramp voltage Vramp.
Specifically, as shown in fig. 3, the ramp generator 100 is implemented by a current steering digital-to-analog converter; the method comprises the following steps: m group current control unit 101, load resistance Rload and dummy resistance Rdummy, wherein, M group current control unit 101's circuit structure all includes: the circuit comprises a current source I0, a first control switch S1 and a second control switch S2; the power supply end of the current source I0 is connected with a power supply voltage VDD, the input end of the current source I0 is connected with a bias voltage, the output end of the current source I0 is connected with the first end of the first control switch S1 and the first end of the second control switch S2, the second end of the first control switch S1 is grounded through a load resistor Rload and generates a ramp voltage Vramp, the second end of the second control switch S2 is grounded through a dummy resistor Rdummy, the first control switch S1 is controlled by a ramp control signal, and the second control switch S2 is controlled by an inverted signal of the ramp control signal; wherein M is a positive number greater than 1.
Alternatively, the circuit structures of the M groups of current control units 101 may be the same, i.e., the current sources I0 of the M groups of current control units 101 have the same current magnitude. Alternatively, the circuit structures of the M groups of current control units 101 may be different, that is, the current source sizes of the current control units in the M groups of current control units 101 may be in a binary increasing proportion, for example, I:2I:4I:8I:16I:32I:64I:128I; the current source sizes of the current control units in the M groups of current control units 101 may also be mixed proportion, for example, I:2I:4I:8I:16I:16I: and 16I. Therefore, the current source size of each current control unit in the M current control units 101 can be designed based on actual requirements, and is not limited herein.
In this example, the M first control switches S1 are controlled by the ramp control signal, and the M second control switches S2 are controlled by the inverted signal of the ramp control signal, so that the current flowing to the load resistor Rload can be controlled by controlling the number of the first control switches S1 to control the magnitude of the ramp voltage Vramp; if M =5 and the ramp control signal is 11111, the inverted signal is 00000, at this time, 5 first control switches S1 are all closed, 5 second control switches S2 are all open, the current flowing to the load resistor Rload is maximum, the ramp voltage Vramp is maximum, and VREF is set; if M =5 and the ramp control signal is 00000, the inverted signal is 11111, at this time, all of the 5 first control switches S1 are turned off, all of the 5 second control switches S2 are turned on, the current flowing to the load resistor Rload is minimum, and the ramp voltage Vramp is minimum and is 0.
The ramp voltage Vramp may be a rising ramp signal or a falling ramp signal; the voltage value of the generated ramp voltage Vramp is changed in an ascending way or in a descending way by controlling the closed number of the first control switch S1 to be changed in an ascending way or in a descending way.
In practical application, two paths to ground are formed by using the load resistor Rload and the dummy resistor Rdummy, and the first control switch S1 and the second control switch S2 are respectively controlled by the ramp control signal and the inverted signal thereof, so that the current source I0 is ensured to have a conducting path all the time in the switch switching process, thereby avoiding generating glitches on the output node, and further avoiding influencing the differential nonlinearity of the ramp voltage Vramp (if the current source I0 has no conducting path at a certain moment, the current source I0 charges the node above the corresponding switch, and when the switch is turned on again, the charge stored in the node above the switch is discharged onto the output node and generates glitches, which influences the differential nonlinearity of the ramp voltage Vramp).
The comparator 200 has a non-inverting input terminal connected to the ramp voltage Vramp and an inverting input terminal connected to the pixel voltage VPIX, and is configured to compare the ramp voltage Vramp with the pixel voltage VPIX and output a comparison result. For example, when the ramp voltage Vramp is greater than the pixel voltage VPIX, the comparator 200 outputs a high level, and when the ramp voltage Vramp is less than the pixel voltage VPIX, the comparator 200 outputs a low level.
The memory 300 is connected to the comparison output of the comparator 200 for storing the Most Significant Bit (MSB) value according to the comparison result during the coarse quantization stage. For example, when the comparator 200 outputs a high level, the memory 300 stores MSB =1, and when the comparator 200 outputs a low level, the memory 300 stores MSB =0. Since the memory 300 stores only 1-bit data (1 or 0), the memory 300 is a 1-bit memory in general.
In this example, if the ramp voltage Vramp is a decreasing ramp signal: in an initial stage, the ramp generator 100 generates a ramp control signal to control all M first control switches S1 to be closed, so that a ramp voltage Vramp is VREF; in the coarse quantization stage, the ramp generator 100 generates a corresponding ramp control signal to control half of the M first control switches S1 to be closed, so that the ramp voltage Vramp is 1/2VREF; in the transition phase, the digital control logic 400 generates a control feedback signal ramp _ az and outputs the control feedback signal ramp _ az to the ramp generator 100, if MSB =1, the digital control logic 400 maintains the control feedback signal ramp _ az in a low level state to maintain the ramp voltage Vramp at 1/2VREF, and if MSB =0, the digital control logic 400 adjusts the control feedback signal ramp _ az to a high level state to change the ramp control signal generated by the ramp generator 100, thereby controlling all the M first control switches S1 to be closed and resetting the ramp voltage Vramp to VREF; in the fine quantization stage, the ramp control signal generated by the ramp generator 100 should control the M first control switches S1 to gradually decrease the number of closures on the existing basis, so that the ramp voltage Vramp is gradually decreased from 1/2VREF to 0, or from VREF to 1/2VREF.
If the ramp voltage Vramp is a rising ramp signal, then: in an initial stage, the ramp generator 100 generates a ramp control signal to control all M first control switches S1 to be turned off, so that the ramp voltage Vramp is 0; in the coarse quantization stage, the ramp generator 100 generates a corresponding ramp control signal to control half of the M first control switches S1 to be closed, so that the ramp voltage Vramp is 1/2VREF; in the transition phase, the digital control logic 400 generates a control feedback signal ramp _ az and outputs the control feedback signal ramp _ az to the ramp generator 100, if MSB =1, the digital control logic 400 adjusts the control feedback signal ramp _ az to a high level state to change the ramp control signal generated by the ramp generator 100, and further controls all M first control switches S1 to be turned off, and resets the ramp voltage Vramp to 0, and if MSB =0, the digital control logic 400 maintains the control feedback signal ramp _ az in a low level state to maintain the ramp voltage Vramp at 1/2VREF; in the fine quantization stage, the ramp control signal generated by the ramp generator 100 controls the M first control switches S1 to gradually increase the number of closures on the basis of the existing one, so that the ramp voltage Vramp gradually increases from 0 to 1/2VREF, or gradually increases from 1/2VREF to VREF.
In practical applications, the digital control logic 400 is implemented by a controller, however, other circuits that can generate the control feedback signal ramp _ az according to the above logic are also applicable to this example; the ramp control signal generated by the ramp generator 100 may be encoded by a binary code, a thermometer code, or a hybrid code.
The counter 500 is connected to the comparison output terminal of the comparator 200, and is used for performing quantization counting of the remaining bits according to the comparison result in the fine quantization stage. Wherein, the counter is an (N-1) bit counter, and N is the resolution of the two-step single-slope analog-to-digital converter.
Further, the two-step single-slope analog-to-digital converter 10 further includes: a first coupling capacitor C1 and a second coupling capacitor C2; the first coupling capacitor C1 is connected between the ramp voltage Vramp and the non-inverting input terminal Vinp of the comparator 200, and the second coupling capacitor C2 is connected between the pixel voltage VPIX and the inverting input terminal Vinn of the comparator 200, for buffering the corresponding voltage signal input to the comparator 200. In practical applications, the first coupling capacitor C1 is a variable capacitor, and the second coupling capacitor C2 is a fixed capacitor, wherein a specific capacitance value of the variable capacitor should be set according to a value of the corresponding ramp voltage Vramp.
Further, the two-step single-slope analog-to-digital converter 10 further includes: a first zero clearing switch K1 and a second zero clearing switch K2; the first clear switch K1 is connected between the non-inverting input terminal Vinp and the non-inverting output terminal Vop1 of the comparator 200 and controlled by a clear control signal cmp _ az, and the second clear switch K2 is connected between the inverting input terminal Vinn and the inverting output terminal Von1 of the comparator 200 and controlled by a clear control signal cmp _ az. When the zero clearing control signal cmp _ az is valid, the first zero clearing switch K1 and the second zero clearing switch K2 are closed, the non-inverting input terminal Vinp and the non-inverting output terminal Vop1 of the comparator 200 are in short circuit, and the inverting input terminal Vinn and the inverting output terminal Von1 are in short circuit, so that zero clearing operation of the comparator 200 is achieved.
Accordingly, the present embodiment also provides a conversion method of the two-step single-slope analog-to-digital converter 10 as described above, including: step 1), step 2), step 3) and step 4); in the conversion method, the ramp voltage Vramp is a descending ramp signal.
Step 1) initial stage, the value of ramp voltage Vramp is set to VREF. For example, M first control switches S1 are all controlled to be closed based on the first ramp control signal, so as to set the value of the ramp voltage Vramp as VREF.
Step 2) a coarse quantization stage, namely reducing the value of a ramp voltage Vramp from VREF to 1/2VREF based on a ramp control signal, and comparing a pixel voltage VPIX with a current ramp voltage; the most significant MSB =1 if VPIX <1/2VREF, and MSB =0 if VPIX >1/2 VREF. For example, half of the M first control switches S1 are controlled to be closed based on the second ramp control signal, so that the value of the ramp voltage Vramp is rapidly decreased from VREF to 1/2VREF; meanwhile, since the ramp voltage Vramp and the pixel voltage VPIX are respectively coupled to the non-inverting input terminal and the inverting input terminal of the comparator 200, the current ramp voltage and the pixel voltage VPIX may be compared, and the value of the MSB may be stored in the memory 300 according to the comparison result.
Step 3) a transition phase, if MSB =1, maintaining the value of the ramp voltage Vramp at 1/2VREF based on the control feedback signal ramp _ az generated by the digital control logic 400, and if MSB =0, resetting the value of the ramp voltage Vramp from 1/2VREF to VREF based on the control feedback signal ramp _ az. If MSB =1, the control feedback signal ramp _ az generated by the digital control logic 400 is maintained at a low level, and the ramp control signal generated by the ramp generator 100 is unchanged to maintain the ramp voltage Vramp at 1/2VREF; if MSB =0, the digital control logic 400 adjusts the control feedback signal ramp _ az to a high level, so that the ramp generator 100 changes the ramp control signal to control all the M first control switches S1 to be closed, and resets the ramp voltage Vramp to VREF.
And 4) in a fine quantization stage, the value of the ramp voltage Vramp is controlled to gradually decrease based on the ramp control signal, the rest bits are quantized, and then the quantization results of all bits are obtained according to the weight of the code value. For example, the M first control switches S1 are controlled to gradually decrease the number of closures based on the third ramp control signal, such that the ramp voltage Vramp is gradually decreased from 1/2VREF to 0, or from VREF to 1/2VREF, and the remaining bits are quantized using the comparator 200 and the counter 500.
Specifically, the pixel voltage VPIX includes a picture voltage Vsig and/or a reset voltage Vrst. In practical applications, the pixel voltage VPIX includes both the image voltage Vsig and the reset voltage Vrst; since the CMOS image sensor outputs the reset voltage Vrst and outputs the image voltage Vsig after a period of time, the two-step single-slope analog-to-digital converter 10 performs a/D conversion on the reset voltage Vrst and then performs a/D conversion on the image voltage Vsig.
More specifically, when the pixel voltage VPIX includes the reset voltage Vrst and the image voltage Vsig, correlated double sampling is performed based on the same ramp generator to obtain the reset voltage Vrst and the image voltage Vsig, respectively. Since the ramp voltage Vramp of the quantized reset voltage Vrst and the image voltage Vsig is generated by the same ramp generator, true correlated double sampling can be performed to eliminate noise such as KT/C and FPN; in contrast, in the conventional two-step SS ADC, since the ramp voltages of the quantized reset voltage Vrst and the image voltage Vsig are not generated by the same ramp generator, correlated double sampling can be achieved only in a partial voltage range.
Accordingly, the present embodiment further provides a conversion method of the two-step single-slope analog-to-digital converter 10 as described above, where the conversion method includes: step 1), step 2), step 3) and step 4); in the conversion method, the ramp voltage Vramp is a rising ramp signal.
Step 1) initial stage, setting the value of the ramp voltage Vramp to 0. For example, all of the M first control switches S1 are controlled to be turned off based on the first ramp control signal, thereby setting the value of the ramp voltage Vramp to 0.
Step 2) a coarse quantization stage, namely increasing the value of a ramp voltage Vramp from 0 to 1/2VREF based on a ramp control signal, and comparing a pixel voltage VPIX with a current ramp voltage; the most significant MSB =1 if VPIX <1/2VREF, and MSB =0 if VPIX >1/2 VREF. For example, half of the M first control switches S1 are controlled to be closed based on the second ramp control signal, so that the value of the ramp voltage Vramp is rapidly increased from 0 to 1/2VREF; meanwhile, since the ramp voltage Vramp and the pixel voltage VPIX are respectively coupled to the non-inverting input terminal and the inverting input terminal of the comparator 200, the current ramp voltage and the pixel voltage VPIX may be compared, and the value of the MSB may be stored in the memory 300 according to the comparison result.
Step 3) a transition phase, wherein if MSB =1, the value of the ramp voltage Vramp is reset from 1/2VREF to 0 based on the control feedback signal ramp _ az, and if MSB =0, the value of the ramp voltage Vramp is maintained at 1/2VREF based on the control feedback signal ramp _ az generated by the digital control logic 400. If MSB =1, the digital control logic 400 adjusts the control feedback signal ramp _ az to a high level, so that the ramp generator 100 changes the ramp control signal to control all the M first control switches S1 to be turned off, and resets the ramp voltage Vramp to 0; if MSB =0, the control feedback signal ramp _ az generated by the digital control logic 400 is maintained at a low level, and the ramp control signal generated by the ramp generator 100 is unchanged to maintain the ramp voltage Vramp at 1/2VREF.
And 4) a fine quantization stage, namely controlling the value of the ramp voltage Vramp to gradually rise based on the ramp control signal, quantizing the rest bits, and obtaining the quantization results of all bits according to the weight of the code value. For example, the M first control switches S1 are controlled based on the third ramp control signal to gradually increase the number of closures on the existing basis, such that the ramp voltage Vramp gradually increases from 0 to 1/2VREF, or gradually increases from 1/2VREF to VREF, and the remaining bits are quantized using the comparator 200 and the counter 500.
Specifically, the pixel voltage VPIX includes a picture voltage Vsig and/or a reset voltage Vrst. In practical applications, the pixel voltage VPIX includes both the image voltage Vsig and the reset voltage Vrst; since the CMOS image sensor outputs the reset voltage Vrst and outputs the image voltage Vsig after a certain period of time, the two-step single-slope analog-to-digital converter 10 performs a/D conversion on the reset voltage Vrst and then performs a/D conversion on the image voltage Vsig.
More specifically, when the pixel voltage VPIX includes the reset voltage Vrst and the image voltage Vsig, correlated double sampling is performed based on the same ramp generator to obtain the reset voltage Vrst and the image voltage Vsig, respectively. Since the ramp voltage Vramp of the quantized reset voltage Vrst and the image voltage Vsig is generated by the same ramp generator, true correlated double sampling can be performed to eliminate noise such as KT/C and FPN; in contrast, in the conventional two-step SS ADC, since the ramp voltages of the quantized reset voltage Vrst and the image voltage Vsig are not generated by the same ramp generator, correlated double sampling can be achieved only in a partial voltage range.
Referring to fig. 4 and 5, a description will be given of a conversion method of the two-step single-slope analog-to-digital converter according to the present embodiment with reference to fig. 2 and 3.
The pixel voltage VPIX includes an image voltage Vsig and a reset voltage Vrst, and since the time for quantizing the image voltage Vsig is much longer than the time for quantizing the reset voltage Vrst, attention is focused on the a/D conversion process of the image voltage Vsig; here, the ramp signal whose ramp voltage Vramp is decreased is taken as an example.
In the initial stage, all the M first control switches S1 are closed, all the M second control switches S2 are opened, and at this time, the initial value of the ramp voltage Vramp is VREF.
A coarse quantization stage, closing half of M first control switches S1 to reduce the value of the ramp voltage Vramp from VREF to VREF/2 in a short time; meanwhile, a ramp voltage Vramp and an image voltage Vsig are correspondingly input to the non-inverting input terminal and the inverting input terminal of the comparator 200 and compared:
(1) If the output of comparator 200 is not flipped Vsig < VREF/2, at which time MSB =1 is stored in memory 300;
then, entering a transition stage, controlling the feedback signal ramp _ az to be maintained at a low level, keeping half of the M first control switches S1 closed, and maintaining the value of the ramp voltage Vramp at VREF/2;
and then, entering a fine quantization stage, gradually opening the M first control switches S1 on the basis of half closing, gradually reducing the value of the ramp voltage Vramp from VREF/2 to 0, continuously quantizing the rest (N-1) bits according to the working mode of the traditional SS ADC, and finally obtaining an N-bit quantization result according to the weight of the code value.
(2) If the output of comparator 200 flips, then Vsig > VREF/2, at which point MSB =0 is stored in memory 300;
then, entering a transition stage, adjusting the control feedback signal ramp _ az to be at a high level, closing all the M first control switches S1, and quickly resetting the value of the ramp voltage Vramp from VREF/2 to VREF;
and then, entering a fine quantization stage, gradually disconnecting the M first control switches S1 on the basis of complete closing, gradually reducing the value of the ramp voltage Vramp from VREF to VREF/2, continuously quantizing the rest (N-1) bits according to the working mode of the traditional SS ADC, and finally obtaining an N-bit quantization result according to the weight of the code value.
In the two situations, the ramp voltage Vramp is respectively reduced from VREF/2 to 0 and from VREF to VREF/2, and the traditional SS ADC is reduced from VREF to 0, so that the scheme saves clock period compared with the traditional SS ADC, and the clock period range is 2 N To 2 N-1 And infinitely close to 2 N-1 Moreover, compared with the traditional two-step SS ADC, the scheme does not need so many ramp generators, and effectively solves the problems of the area, power consumption and linearity of the traditional two-step SS ADC.
The two-step SS ADC provided by the scheme improves the conversion speed of the SS ADC by applying the dichotomy in the first A/D conversion, and simultaneously retains the advantages of low noise, small area and low power consumption of the traditional SS ADC; in the course of coarse quantization, although the signal linearity of the ramp voltage Vramp is poor, it does not affect the acquisition of the 1-bit MSB and the fine quantization of the subsequent (N-1) bit code value. In the second a/D conversion process, the quantization range VREF is divided into two upper and lower subintervals, and whether to reset the ramp voltage Vramp to VREF is selected before fine quantization according to the value of MSB obtained in the first step, after which quantization of the remaining bits is completed. Therefore, compared with the traditional SS ADC, the MSB A/D conversion time obtained by the scheme is effectively reduced, and the effectiveness of the scheme is gradually improved along with the improvement of the resolution of the SS ADC; in addition, only one ramp generator is adopted, so that the problems of the area, the power consumption and the linearity of the traditional two-step SS ADC are effectively solved.
Example two
As shown in fig. 2, the present embodiment provides a readout circuit 1, the readout circuit 1 including: the two-step single-slope analog-to-digital converter 10 is described in the first embodiment.
Accordingly, as shown in fig. 2, the present embodiment further provides an image system, which includes: the readout circuit 1 described above.
Furthermore, the image system also comprises a pixel array, wherein the pixel array comprises a plurality of pixel units which are arranged in rows and columns to form an array; each pixel unit is correspondingly provided with a pixel circuit 2, wherein each pixel unit corresponds to the same or different column lines so as to realize serial output or parallel output of the pixel voltage VPIX through the readout circuit 1 respectively. It should be noted that the pixel unit is any of the conventional pixel circuits, and the specific structure thereof has no substantial influence on the present embodiment.
To sum up, the utility model discloses a two step type monoclinic slope analog-to-digital converter, reading circuit and image system, provided a brand-new two step type monoclinic slope analog-to-digital conversion scheme, fall into the Most Significant Bit (MSB) of 1 bit and the surplus bit of (N-1) bit with N bit resolution ratio, adopt the dichotomy to accomplish the quantization of MSB in the A/D conversion process for the first time, can reduce effectively and quantize the step and along with the improvement of ADC resolution ratio, the conversion clock cycle of saving can increase gradually. According to the scheme, an additional ramp generator is not needed, and the quantization process of the two-step SS ADC can be completed only by utilizing one of the falling ramp voltage or the rising ramp voltage generated by the conventional ramp generator (namely, the conventional single-slope ADC is utilized, and only one ramp generator is needed). Because the ramp signal used is not different from the traditional SS ADC, all the advantages of the traditional SS ADC are kept, the problems of the area, the power consumption and the linearity of the traditional two-step SS ADC are effectively solved, and the quantization speed of the SS ADC can be effectively improved on the premise of not influencing the area, the power consumption and the linearity of the CIS. In addition, the scheme is based on the traditional SS ADC architecture, so that reversible switching can be performed between the scheme and the traditional SS ADC algorithm without redesigning. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention shall be covered by the claims of the present invention.
Claims (8)
1. A two-step single-slope analog-to-digital converter, comprising:
the ramp generator is used for generating a ramp control signal and adjusting the ramp control signal based on a control feedback signal so as to generate and output a ramp voltage;
the comparator is connected with the ramp voltage at a non-inverting input end, is connected with the pixel voltage at an inverting input end, and is used for comparing the ramp voltage with the pixel voltage and outputting a comparison result;
the memory is connected with the comparison output end of the comparator and used for storing the value of the highest bit according to the comparison result in the coarse quantization stage;
the digital control logic is connected with the output end of the memory and used for generating the control feedback signal and adjusting the control feedback signal according to the value of the highest bit so as to reset the ramp voltage;
and the counter is connected with the comparison output end of the comparator and used for carrying out the quantization counting of the residual bits according to the comparison result in the fine quantization stage.
2. The two-step single-slope analog-to-digital converter of claim 1, further comprising:
the first coupling capacitor is connected between the ramp voltage and the non-inverting input end of the comparator;
and the second coupling capacitor is connected between the pixel voltage and the inverting input end of the comparator.
3. The two-step single-slope analog-to-digital converter of claim 1, further comprising:
the first zero clearing switch is connected between the in-phase input end and the in-phase output end of the comparator and is controlled by a zero clearing control signal;
and the second zero clearing switch is connected between the inverted input end and the inverted output end of the comparator and is controlled by the zero clearing control signal.
4. The two-step single-ramp analog-to-digital converter according to claim 1, wherein the ramp generator is implemented as a current-steering digital-to-analog converter.
5. The two-step single-ramp analog-to-digital converter according to claim 4, wherein the ramp generator comprises: m group current control unit, load resistance and dummy resistance, wherein, M group the circuit structure of current control unit all includes: the circuit comprises a current source, a first control switch and a second control switch;
a power supply end of the current source is connected with a power supply voltage, an input end of the current source is connected with a bias voltage, an output end of the current source is connected with a first end of the first control switch and a first end of the second control switch, a second end of the first control switch is grounded through the load resistor and generates the ramp voltage, a second end of the second control switch is grounded through the dummy resistor, the first control switch is controlled by the ramp control signal, and the second control switch is controlled by an inverted signal of the ramp control signal; wherein M is a positive number greater than 1.
6. The two-step single-slope analog-to-digital converter according to claim 1, wherein the memory is a 1-bit memory, and the counter is an (N-1) bit counter; and N is the resolution of the two-step single-slope analog-to-digital converter.
7. A sensing circuit, the sensing circuit comprising: a two-step single-ramp analog-to-digital converter as claimed in any one of claims 1 to 6.
8. An imaging system, characterized in that the imaging system comprises: the sensing circuit of claim 7.
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