CN217693281U - PWM dead zone precision control circuit and SOC chip - Google Patents
PWM dead zone precision control circuit and SOC chip Download PDFInfo
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Abstract
The utility model discloses a PWM blind spot precision control circuit and SOC chip, this circuit includes: the circuit comprises a phase inverter, a first D trigger, a second D trigger, a first two-input OR gate, a second two-input OR gate, a first two-way selector and a second two-way selector. The utility model provides a PWM blind spot precision control circuit can produce minimum half clock cycle's blind spot signal, can improve PWM's blind spot precision to half clock cycle from a clock cycle, realizes the purpose that improves energy utilization efficiency. The utility model discloses a circuit structure is simple, and the cost is lower, need not modify original PWM digital circuit, and original PWM complementary signal is received to this circuit, just can export the signal that contains the highest precision of dead time for half clock cycle after handling.
Description
Technical Field
The utility model relates to a PWM technical field especially relates to a PWM blind spot precision control circuit and SOC chip.
Background
PWM (Pulse Width Modulation) is widely used in the fields of switching power supplies, motor control, and the like. Currently, there is an increasing demand for efficiency in the use of energy, where power conversion efficiency is an important part. Due to the existence of the power device capacitor, in the power supply conversion process, the on and off of the device inevitably have certain delay phenomenon during switching. If the two devices are conducted simultaneously, the circuit can be damaged, and a protection mechanism which is set by simultaneously conducting the upper device and the lower device in the switching process of the switch can be avoided by setting a PWM dead zone. The size of the dead time depends on the manufacturing process of the power element, and on the premise of meeting the safe and reliable requirements, the smaller the dead time is, the higher the energy utilization efficiency is.
The PWM dead-zone control signal is typically generated by a dedicated driver chip or SOC. The special driving chip has high reliability, but the cost is high, and the dead time is not flexible enough because of the adjustment by external resistors and other modes. The SOC generation mode is divided into software generation and digital circuit generation, wherein the software mode is flexible, the program complexity is high, the reliability and the real-time performance are not as good as those of hardware, and the SOC resource occupation is large. At present, many SOCs comprise digital circuits capable of generating PWM signals, users can flexibly control the PWM through software programming based on the fact that the SOCs are integrated inside the SOCs, PWM waveform signals and dead zone control are generated by the digital circuits, and the precision and the reliability are high.
Most of digital circuits in the SOC chip are realized by using a synchronous digital circuit, the synchronous digital circuit is easy to realize in generating a PWM signal with the precision of one clock cycle, and a special scheme is needed if the PWM signal with the width of less than one clock cycle is to be generated. For example, the delay unit is used to delay the PWM two-way signal, which generates a phase difference between the PWM two-way signal to create the desired dead time. However, in a common CMOS manufacturing process, the delay effect of the delay unit is sensitive to the environment, and the difference in the delay effect is significant under different conditions of process deviation, voltage, temperature, and the like, which is not suitable for an application scenario with high precision requirements. If complex technologies such as DLL (Delay locked Loop) are adopted to generate reliable time Delay, the cost is greatly increased.
Disclosure of Invention
For the technical problem who exists among the solution background art, the utility model provides a PWM blind spot precision control circuit and SOC chip can realize half minimum clock cycle's dead time control.
The utility model provides a PWM blind spot precision control circuit, include: the circuit comprises an inverter 10, a first D flip-flop 20, a second D flip-flop 30, a first two-input OR gate 40, a second two-input OR gate 50, a first two-way selector 60 and a second two-way selector 70;
the input end of the inverter 10 can input a clock signal;
the output end of the inverter 10 is connected with the clock input end of the first D flip-flop 20; the output end of the first D flip-flop 20 is connected with the input end of a first two-input or gate 40, and the output end of the first two-input or gate 40 is connected with the input end of a first two-way selector 60; the other input terminals of the first D flip-flop 20, the first two-input OR gate 40 and the first two-way selector 60 may be connected to PWM + of the PWM controller in End is connected to input PWM + of one clock period in The enable input terminal of the first two-way selector 60 can input an enable signal, and the output terminal of the first two-way selector 60 can output half clock period PWM + out A signal;
the output end of the inverter 10 is connected with the clock input end of the second D flip-flop 30; the output end of the second D flip-flop 30 is connected to the input end of the second two-input or gate 50, and the output end of the second two-input or gate 50 is connected to the input end of the second two-way selector 70; the second D flip-flop 30, the second two-input OR gate 50, and the other input terminal of the second two-way selector 70 can be connected to the PWM of the PWM controller in End connected to input PWM of one clock cycle in The enable input terminal of the second two-way selector 70 can input the enable signal, and the output terminal of the second two-way selector 70 can output the half-clock period PWM- out A signal.
Preferably, inverter 10 has one input and one output; is connectable with the system controller via an input terminal to input the CLK clock signal; the output terminals are connected to the clock input terminals of the first D flip-flop 20 and the second D flip-flop 30, respectively.
Preferably, the first D flip-flop 20 has two inputs and one output; input terminal [ D ]]PWM + capable of being matched with PWM controller in End is connected to input PWM + of one clock period in The signal, clock input terminal is connected to the output terminal of the inverter 10, the input terminal [ Q ]]Connected to a first two-input or gate 40.
Preferably, the second D flip-flop 30 has two inputs and one output; input terminal [ D ]]PWM (pulse width modulation) with PWM controller in End connected to input PWM of one clock cycle in The signal, clock input terminal is connected to the output terminal of the inverter 10, the input terminal [ Q ]]Connected to a second two-input or gate 50.
Preferably, the first two-input or gate 40 has two inputs and one output; the first input terminal can be connected with PWM + of PWM controller in End is connected to input PWM + of one clock period in A second input terminal of the signal is connected to the output terminal of the first D flip-flop 20; the output is connected to a first two-way selector 60.
Preferably, a second two-input or gate 50 having two inputs and one output; the first input terminal can be connected with the PWM of the PWM controller in End connected to input PWM of one clock cycle in A second input terminal of the signal is connected to the output terminal of the second D flip-flop 30, and the output terminal is connected to the second two-way selector 70.
Preferably, a first two-way selector 60 having three inputs and one output; input terminal [0]PWM + capable of being matched with PWM controller in End is connected to input PWM + of one clock period in Signal, input terminal [1]Connected to the output of a first two-input OR gate 40, the enable input of which is connected to PWM controlThe output end can output half clock period PWM + out A signal.
Preferably, a second two-way selector 70 having three inputs and one output; input terminal [0]PWM + capable of being matched with PWM controller in End is connected to input PWM + of one clock period in Signal, input terminal [1]Is connected to the output terminal of the second two-input OR gate 50, the enable input terminal can be connected to the PWM controller for inputting the enable signal, and the output terminal can output the half-clock-period PWM- out A signal.
The utility model provides a SOC chip, which comprises a central processing unit CPU, a PWM controller, a clock generator and a PWM dead-zone precision control circuit;
the input end of the inverter 10 is connected with a clock generator;
first D flip-flop 20, first two-input OR gate 40, input terminal of first two-way selector 60 and PWM + of PWM controller in The ends are connected, the enable input end of the first two-way selector 60 is connected with the EN end of the PWM controller, and the output end PWM + of the first two-way selector 60 out Is connected with the chip pins;
the second D flip-flop 30, the second two-input OR gate 50, the input terminal of the second two-way selector 70 and the PWM of the PWM controller in End connection; the enable input terminal of the second two-way selector 70 is connected with the EN terminal of the PWM controller, and the output terminal PWM of the second two-way selector 70 out Connected with the chip pins.
The utility model provides a PWM blind spot precision control circuit can produce minimum half clock cycle's blind spot signal, can improve PWM's blind spot precision to half clock cycle from a clock cycle, realizes the purpose that improves energy utilization efficiency. The utility model discloses a circuit structure is simple, and the cost is lower, need not modify original PWM digital circuit, and original PWM complementary signal is received to this circuit, just can export the signal that contains the highest precision of dead time for half clock cycle after handling. The utility model discloses a PWM dead band precision control circuit, can integrate in the SOC chip that supports PWM digital circuit; in the practical application process, the circuit function can be turned on or off, and a user can flexibly configure the circuit function according to the requirement.
Drawings
Fig. 1 is the utility model provides a PWM dead zone precision control circuit's schematic structure diagram.
Fig. 2 is a timing diagram of signals after processing using the circuit of fig. 1.
Fig. 3 is a schematic structural diagram of an SOC chip according to an embodiment of the present invention.
Detailed Description
The embodiment of the utility model provides a PWM blind spot precision control circuit and device can realize minimum half clock cycle's dead time control.
As shown in fig. 1 and fig. 3, the present embodiment provides a PWM dead-zone accuracy control circuit, which includes: an inverter 10, a first D flip-flop 20, a second D flip-flop 30, a first two-input or gate 40, a second two-input or gate 50, a first two-way selector 60, and a second two-way selector 70.
The input end of the inverter 10 can input a clock signal;
the output end of the inverter 10 is connected with the clock input end of the first D flip-flop 20; the output end of the first D flip-flop 20 is connected with the input end of a first two-input or gate 40, and the output end of the first two-input or gate 40 is connected with the input end of a first two-way selector 60; the other input terminals of the first D flip-flop 20, the first two-input OR gate 40 and the first two-way selector 60 may be connected to PWM + of the PWM controller in End is connected to input PWM + of one clock period in The enable input terminal of the first two-way selector 60 can input an enable signal, and the output terminal of the first two-way selector 60 can output half clock period PWM + out A signal;
the output end of the inverter 10 is connected with the clock input end of the second D flip-flop 30; the output end of the second D flip-flop 30 is connected to the input end of the second two-input or gate 50, and the output end of the second two-input or gate 50 is connected to the input end of the second two-way selector 70; the other input terminals of the second D flip-flop 30, the second two-input OR gate 50, and the second two-way selector 70 may be connected to PWM + of the PWM controller in End connected to input PWM of one clock cycle in The enable input terminal of the second two-way selector 70 can input the enable signal, and the output terminal of the second two-way selector 70 can output the half-clock period PWM- out A signal.
An inverter 10 having an input terminal and an output terminal; the input end is connected with the clock generator, and the CLK clock signal is input through the input end; the output port is connected with the clock input ends of the first D flip-flop 20 and the second D flip-flop 30, and the output signal of the output port is E1;
a first D flip-flop 20 having two input terminals and one output port; one of the input terminals is the D terminal, and is connected with PWM + of the PWM controller in End connected to input PWM + of one clock period in A signal; the other input end is a clock input end and is connected with the output port of the phase inverter 10; the output port is a Q port, the output port is connected to the first two-input or gate 40, and the output signal of the output port is E2;
a second D flip-flop 30 having two input terminals and one output port; one of the input terminals is D terminal, and PWM of PWM controller in End connection for inputting PWM of a clock period in A signal; the other input end is a clock input end and is connected with the output port of the phase inverter 10; the output port is a Q port, the output port is connected to the second two-input or gate 50, and the output signal of the output port is E3;
a first two-input or gate 40 having two inputs and one output; one of the input terminals is connected with PWM + of the PWM controller in End connected to input PWM + of one clock period in A signal; the other input end is connected with the output port of the first D flip-flop 20; the output port is connected to the first two-way selector 60, and the output signal of the output port is E4;
a second two-input or gate 50 having two inputs and one output; wherein one input terminal and PWM of the PWM controller in End connection for inputting PWM of a clock period in A signal; the other input terminal and the output terminal of the second D flip-flop 30A port connection; the output port is connected to the second two-way selector 70, and the output signal of the output port is E5;
a first two-way selector 60 having three input ports and one output port; an enable input terminal connected with the EN terminal of the PWM controller for inputting an enable signal, and an input terminal [0 ]]PWM + of PWM controller in End connected to input PWM + of one clock period in Signal, input terminal [1]Connected to the output ports of the first two-input or gate 40; PWM + with output port capable of outputting half clock period out A signal;
a second two-way selector 70 having three input ports and one output port; an enable input terminal connected with the EN terminal of the PWM controller for inputting an enable signal, and an input terminal [0 ]]PWM with PWM controller in End connection for inputting PWM of a clock period in Signal, input terminal [1]Is connected with the output port of the second two-input or gate 50; PWM (pulse width modulation) device with output port capable of outputting half clock period out A signal.
In the present embodiment, CLK is an operation clock used by the digital circuit, CLK is input to the inverter 10, and E1 is an inverted clock generated by CLK through the inverter 10.
In this embodiment, PWM + in The original one-clock-cycle PWM positive terminal signal is input to the D terminal of the first D flip-flop 20, the first two-input or gate 40, and the first two-way selector 60.
In the present embodiment, PWM- in The original one-clock-cycle PWM negative terminal signal is inputted to the D terminal of the second D flip-flop 30, the second two-input or gate 50, and the second two-way selector 70.
In the present embodiment, EN is an enable signal that acts on first two-way selector 60 and second two-way selector 70 as an enable switch for a user-configured PWM dead-time accuracy control circuit. When EN is 0, the original PWM + is selected in /PWM- in The signal is output to PWM + out When EN is 1, the signal output after the precision improvement processing is selected.
In this embodiment, PWM + out And PWM- out Outputting complementary signals for the processed PWM.
According to the PWM dead-zone accuracy control circuit of the present embodiment, the logic of the working process is specifically:
PWM+ in the signal generates E2 after the second D flip-flop is delayed by one clock period through the inverted clock E1; e2 and PWM + in The E4 signal output is generated after the OR operation of the first two-input OR gate 40; e4 signal relative to PWM + in When the high level jumps to the low level, the time of the high level is increased by half a clock cycle; the EN signal acts on the first two-way selector 60 selector, which may select PWM + out Output uses the original PWM + in A signal, or a processed signal.
PWM- in The signal is generated E3 after the second D flip-flop 30 is delayed by one clock cycle by the inverted clock E1; e3 and PWM- in Generating an E5 signal output after the OR operation of the second two-input OR gate 50; e5 Signal versus PWM- in When the high level jumps to the low level, the time of the high level is increased by half a clock cycle; the EN signal acts on the second two-way selector 70 selector, and can select PWM- out Output using original PWM- in A signal, or a processed signal.
As shown in fig. 2, according to the PWM dead-zone accuracy control circuit of the present embodiment, the timing chart of the signal after processing by the circuit, where EN is kept at a high level, that is, the PWM dead-zone accuracy control circuit is enabled, is as follows:
e2 through the negative phase clock to PWM + in One cycle delayed, the phase of E2 is relative to PWM + in Will shift back by half a clock cycle; e2 and PWM + in PWM + generated after first two-input OR gate 40 OR operation out The high level duration of the signal will be relative to PWM + in A plurality of half clock cycles; the falling edge dead zone of the PWM is the time of the falling edge of the positive end of the PWM relative to the rising edge of the negative end, and the falling edge dead zone of the PWM is reduced from one clock period to half of the clock period;
e3 PWM through negative phase clock in One period delayed so that the phase of E3 is relative to PWM- in Will shift back by half a clock cycle; e3 andPWM- in PWM generated after the second two-input OR gate 50 OR operation out The high level duration of the signal will be relatively PWM- in A plurality of half clock cycles; the dead zone of the rising edge of the PWM is the time of the falling edge of the negative terminal relative to the rising edge of the positive terminal of the PWM, and the dead zone of the rising edge of the PWM is reduced from one clock cycle to a half clock cycle.
The utility model provides a PWM blind spot precision control circuit can produce minimum half clock cycle's blind spot signal, can improve PWM's blind spot precision to half clock cycle from a clock cycle, realizes the purpose that improves energy utilization efficiency.
The utility model discloses a circuit structure is simple, and the cost is lower, need not modify original PWM digital circuit, and original PWM complementary signal is received to this circuit, just can export the signal that contains the highest precision of dead time for half clock cycle after handling.
The utility model discloses a PWM dead band precision control circuit, can integrate in the SOC chip that supports PWM digital circuit; in the practical application process, the circuit function can be turned on or off, and a user can flexibly configure the circuit according to the requirement.
Referring to fig. 3, the embodiment of the utility model provides a SOC chip has provided this PWM blind spot precision control circuit integrateed, and this chip principal components part includes: the device comprises a Central Processing Unit (CPU), an on-chip bus, a clock generator, a Pulse Width Modulation (PWM) controller and a PWM dead zone precision control circuit.
In the PWM dead zone precision control circuit, the input end PWM + in And PWM- in Connected with PWM controller, input end EN connected with PWM controller, input end CLK connected with clock generator, output end PWM + out And PWM- out The ports are respectively connected with chip pins; the CLK port of the PWM controller is connected with the clock generator; the PWM controller is mounted on the on-chip bus and used for parameter configuration of the central processing unit CPU through the on-chip bus.
In a specific embodiment, various other peripheral interfaces may also be mounted on the on-chip bus.
The above, only be the concrete implementation of the preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art is in the technical scope of the present invention, according to the technical solution of the present invention and the utility model, the concept of which is equivalent to replace or change, should be covered within the protection scope of the present invention.
Claims (9)
1. A PWM dead-zone accuracy control circuit, comprising: the circuit comprises an inverter (10), a first D trigger (20), a second D trigger (30), a first two-input OR gate (40), a second two-input OR gate (50), a first two-way selector (60) and a second two-way selector (70);
the input end of the inverter (10) can input a clock signal;
the output end of the phase inverter (10) is connected with the clock input end of the first D flip-flop (20); the output end of the first D flip-flop (20) is connected with the input end of a first two-input OR gate (40), and the output end of the first two-input OR gate (40) is connected with the input end of a first two-way selector (60); the other input end of the first D flip-flop (20), the first two-input OR gate (40) and the first two-way selector (60) can be connected with PWM + of the PWM controller in End is connected to input PWM + of one clock period in The enable input end of the first two-way selector (60) can input an enable signal, and the output end of the first two-way selector (60) can output half clock period PWM + out A signal;
the output end of the phase inverter (10) is connected with the clock input end of the second D flip-flop (30); the output end of the second D flip-flop (30) is connected with the input ends of the second two-input OR gate (50), and the output ends of the second two-input OR gate (50) are connected with the input ends of the second two-way selector (70); the other input terminal of the second D flip-flop (30), the second two-input OR gate (50), and the second two-way selector (70) can be connected to the PWM of the PWM controller in End connected to input PWM of one clock cycle in The enable input end of the second two-way selector (70) can input an enable signal, and the output end of the second two-way selector (70) can output half clock period PWM- out A signal.
2. The PWM dead band accuracy control circuit according to claim 1, wherein the inverter (10) has an input terminal and an output terminal; the input end can be connected with the clock generator to input the CLK clock signal; the output ends are respectively connected with the clock input ends of the first D flip-flop (20) and the second D flip-flop (30).
3. The PWM dead band accuracy control circuit according to claim 1, characterized in that the first D flip-flop (20) has two inputs and one output; input terminal [ D ]]PWM + capable of being matched with PWM controller in Terminal connection, clock input terminal connected to output terminal of inverter (10), input terminal [ Q ]]Is connected to a first two-input or gate (40).
4. The PWM dead band accuracy control circuit according to claim 1, characterized in that the second D flip-flop (30) has two inputs and one output; input terminal [ D ]]PWM (pulse width modulation) with PWM controller in Terminal connection, clock input terminal connected to output terminal of inverter (10), input terminal [ Q ]]Is connected to a second two-input or gate (50).
5. The PWM dead band accuracy control circuit according to claim 1, characterized in that the first two-input or gate (40) has two inputs and one output; the first input terminal can be connected with PWM + of PWM controller in The second input end of the first D trigger (20) is connected with the output end of the first D trigger; the output is connected to a first two-way selector (60).
6. The PWM dead band accuracy control circuit according to claim 1, characterized in that the second two-input or gate (50) has two input terminals and one output terminal; the first input terminal can be connected with the PWM of the PWM controller in The second input end is connected with the output end of the second D trigger (30), and the output end is connected with the second two-way selector (70).
7. The PWM dead-band accuracy control circuit of claim 1, whereinThe first two-way selector (60) has three inputs and one output; input terminal [0]PWM + capable of being matched with PWM controller in End connection, input end [1 ]]Is connected with the output end of the first two-input OR gate (40), the enable input end can be connected with the PWM controller to input an enable signal, and the output end can output half clock period PWM + out A signal.
8. The PWM dead band accuracy control circuit according to claim 1, characterized in that the second two-way selector (70) has three inputs and one output; input terminal [0]PWM (pulse width modulation) with PWM controller in Terminal connection, input terminal [1 ]]Is connected with the output end of the second two-input OR gate (50), the enable input end can be connected with the PWM controller to input an enable signal, and the output end can output half clock period PWM- out A signal.
9. An SOC chip, comprising a central processing unit CPU, a PWM controller and a clock generator, characterized in that the PWM dead-zone precision control circuit of any one of claims 1-8 is integrated;
the input end of the phase inverter (10) is connected with the clock generator;
the first D flip-flop (20), the first two-input OR gate (40), the input end of the first two-way selector (60) and the PWM + of the PWM controller in The ends are connected, the enable input end of the first two-way selector (60) is connected with the EN end of the PWM controller, and the output end of the first two-way selector (60) is PWM + out Is connected with the chip pins;
a second D flip-flop (30), a second two-input OR gate (50), an input terminal of a second two-way selector (70) and PWM of the PWM controller in End connection; the enable input end of the second two-way selector (70) is connected with the EN end of the PWM controller, and the output end PWM of the second two-way selector (70) out Connected with the chip pins.
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| CN202221806389.5U CN217693281U (en) | 2022-07-14 | 2022-07-14 | PWM dead zone precision control circuit and SOC chip |
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| CN202221806389.5U CN217693281U (en) | 2022-07-14 | 2022-07-14 | PWM dead zone precision control circuit and SOC chip |
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