CN217468391U

CN217468391U - Semiconductor device with a plurality of semiconductor chips

Info

Publication number: CN217468391U
Application number: CN202123264076.XU
Authority: CN
Inventors: 内山士郎
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2021-12-23
Filing date: 2021-12-23
Publication date: 2022-09-20
Anticipated expiration: 2031-12-23

Abstract

The present disclosure relates to semiconductor devices. Some embodiments of the present application provide a semiconductor device, comprising: a substrate; and a semiconductor element. The semiconductor element is disposed on the substrate, wherein at least one of the substrate and the semiconductor element includes a first recess. The present application provides a semiconductor device having an increased alignment margin, which improves the flexibility of circuit design, thus having higher production efficiency of the semiconductor device and higher quality of the semiconductor device.

Description

Semiconductor device with a plurality of semiconductor chips

Technical Field

The present application relates to the field of semiconductors, and more particularly, to semiconductor devices.

Background

Generally, when a semiconductor device is diced using a plasma dicing process (plasma dicing process), it is necessary to perform dicing from both sides of the semiconductor device, i.e., a first side on which a substrate is located, and a second side on which chips and/or other components carried by the substrate are located, respectively. However, the process of cutting from both sides has many problems, the most important of which is that it is difficult to align a first cut through hole formed at a first side with a second cut through hole formed at a second side. In one aspect, to compensate for potential misalignment between the first cut through hole and the second cut through hole, although the width of the cut region of the first side may be designed to be greater than the width of the cut region of the second side, or the width of the cut region of the first side may be designed to be smaller than the width of the cut region of the second side, misalignment between the first cut through hole and the second cut through hole may still occur. If misalignment occurs, some structures and films in the second side may be exposed and thus may be affected by particles generated during the process, thereby affecting the quality and performance of the semiconductor device. On the other hand, in order to avoid affecting the wiring or other structures near the metal layer at the interface between the first cut via and the second cut via, the metal layer at the interface between the first cut via and the second cut via needs to be removed, which limits the arrangement of the alignment margins of the first side and the second side. Therefore, the production efficiency and quality of the existing semiconductor device are inevitably limited by the arrangement of the alignment margin.

In view of the above, there is a need for a new semiconductor device that avoids at least the above limitations.

SUMMERY OF THE UTILITY MODEL

It is an object of the present invention to provide a semiconductor device having an increased alignment margin, and improved flexibility in circuit design, which avoids affecting the arrangement of other layers in the semiconductor device, thereby achieving higher production efficiency and higher quality of the semiconductor device.

Some embodiments of the present application provide a semiconductor device, comprising: a substrate; and a semiconductor element. The semiconductor element is disposed on the substrate, wherein at least one of the substrate and the semiconductor element includes a first recess.

In some embodiments of the present application, the substrate has a first surface facing away from the semiconductor element, and the substrate includes a first notch extending from the first surface of the substrate and terminating before or at an interface between the substrate and the semiconductor element.

In some embodiments of the present application, the first recess has a first surface substantially parallel to the first surface of the substrate, and a side surface connected to the first surface of the first recess and the first surface of the substrate, and wherein an angle between the side surface and the first surface of the substrate is greater than 90 °.

In some embodiments of the present application, the substrate further comprises a second notch, and wherein the second notch is substantially symmetrical to the first notch.

In some embodiments of the present application, the substrate has a side surface connected to the first surface of the first recess, and the semiconductor element has a side surface connected to the interface, and wherein the side surface of the substrate and the side surface of the semiconductor element are substantially coplanar.

In some embodiments of the present application, the semiconductor element has a first surface facing away from the substrate, and the semiconductor element comprises a first recess extending from the first surface of the semiconductor element and terminating before or at an interface between the substrate and the semiconductor element.

In some embodiments of the present application, the first recess has a first surface substantially parallel to the first surface of the semiconductor element, and a side surface connected to the first surface of the first recess and the first surface of the semiconductor element, and wherein an angle between the side surface and the first surface of the first recess is equal to or greater than 90 °.

In some embodiments of the present application, the substrate has a side surface connected to the interface, and the semiconductor element has a side surface connected to the interface, and wherein the side surface of the substrate is substantially coplanar with the side surface of the semiconductor element.

In some embodiments of the present application, the semiconductor device further includes a second recess, and wherein the second recess is substantially symmetrical to the first recess.

In some embodiments of the present application, the substrate includes a base having a first surface facing away from the semiconductor element and a protrusion protruding from the first surface of the base.

In some embodiments of the present application, the side surface of the protrusion makes an angle with the first surface of the base greater than 90 °.

In some embodiments of the present application, a semiconductor element includes a base having a first surface facing away from a substrate and a protrusion protruding from the first surface of the base.

In some embodiments of the present application, the side surface of the protrusion makes an angle substantially equal to 90 ° or greater than 90 ° with the first surface of the base.

In some embodiments of the present application, the substrate is a silicon substrate and the semiconductor elements comprise one or more electronic elements, one or more metal layers, and/or one or more dielectric layers.

In some embodiments of the present application, the one or more electronic components include resistors, capacitors, and/or transistors.

In some embodiments of the present application, the semiconductor element includes a metal layer adjacent to the interface, and the metal layer overlaps a projected area of the first surface of the first recess on the semiconductor element.

In some embodiments of the present application, the first notch defines a cutting region of the substrate.

The present application provides a semiconductor device having an increased alignment margin, which improves the flexibility of circuit design, thus having higher production efficiency of the semiconductor device and higher quality of the semiconductor device.

Drawings

The drawings necessary for describing the embodiments of the present application or the prior art will be briefly described below in order to describe the embodiments of the present application. It is to be understood that the drawings in the following description are only some of the embodiments of the present application. It will be apparent to those skilled in the art that other embodiments of the drawings can be obtained from the structures illustrated in these drawings without the need for inventive work.

Fig. 1A is a schematic longitudinal cross-sectional view of a semiconductor device according to some embodiments of the present application.

Fig. 1B is a schematic top view of the semiconductor device shown in fig. 1A.

Fig. 2 is a schematic longitudinal cross-sectional view of semiconductor devices according to further embodiments of the present application.

Fig. 3A, 3B, and 3C are schematic flow diagrams of fabricating semiconductor devices according to some embodiments of the present application, which can fabricate semiconductor devices such as shown in fig. 1A.

Fig. 4A, 4B, and 4C are schematic flow diagrams of fabricating semiconductor devices according to other embodiments of the present application, which may fabricate semiconductor devices such as those shown in fig. 2.

Fig. 5 is a schematic longitudinal cross-sectional view of semiconductor devices according to further embodiments of the present application.

Detailed Description

Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The examples of the present application should not be construed as limiting the present application.

As used herein, the terms "about", "substantially", "essentially" are used to describe and describe small variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity. For example, when used in connection with numerical values, the term can refer to a variation of less than or equal to ± 10% of the numerical value, such as less than or equal to ± 5%, less than or equal to ± 0.5%, or less than or equal to ± 0.05%. For example, two numerical values may be considered "substantially" the same if the difference between the two numerical values is less than or equal to ± 10% of the mean of the values.

Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

In this application, unless specified or limited otherwise, "disposed," "connected," "coupled," "secured," and words of similar import are used broadly and those skilled in the art will understand that the words used above apply to situations in which, for example, a fixed connection, a removable connection, or an integrated connection; it may also be a mechanical or electrical connection; it may also be directly connected or indirectly connected through intervening structures; or may be internal to both components.

Fig. 1A is a schematic longitudinal cross-sectional view of a semiconductor device 10 according to some embodiments of the present application. Fig. 1B is a schematic top view of the semiconductor device 10 shown in fig. 1A.

As shown in fig. 1A and 1B, a semiconductor device 10 according to some embodiments of the present application may include: a substrate 101 and a semiconductor element 103. The semiconductor device 10 has a width in the horizontal direction and a height in the vertical direction.

The substrate 101 may have a first surface 101a and a second surface 101b opposite to the first surface 101 a. The first surface 101a may face away from the semiconductor element 103. The second surface 101b may face the semiconductor element 103. The substrate 101 may comprise a first recess 107 extending from the first surface 101a of the substrate 101 and terminating before the interface 105 between the substrate 101 and the semiconductor element 103. In other embodiments of the present application, the first recess 107 may extend from the first surface 101a of the substrate 101 and terminate at the interface 105 between the substrate 101 and the semiconductor element 103. In some embodiments of the present application, at least one of the substrate 101 and the semiconductor element 103 may include a first recess 107. The first recess 107 may have a first surface 107a and a side surface 107 b. The first surface 107a may be substantially parallel to the first surface 101a of the substrate 101. The side surface 107b may be connected to the first surface 107a of the first recess 107 and the first surface 101a of the substrate 101. The angle β 1 between the side surface 107b and the first surface 101a of the substrate 101 is greater than 90 °, such as, but not limited to, 100 °, 120 °, or 150 °. The first recess 107 may be formed by any suitable etching process, such as, but not limited to, a plasma etching process or a laser etching process. The first recess 107 may define a cutting region S of the substrate 101. The substrate 101 may further comprise a second recess 109. The second recess 109 may be substantially symmetrical to the first recess 107. The second recess 109 may have a first surface 109a and a side surface 109 b. The first surface 109a may be substantially parallel to the first surface 101a of the substrate 101. The side surface 109b may be connected to the first surface 109a of the second recess 109 and the first surface 101a of the substrate 101. The angle α 1 between the side surface 109b and the first surface 101a of the substrate 101 is greater than 90 °, such as, but not limited to, 100 °, 120 °, or 150 °. The included angle α 1 and the included angle β 1 may be the same or different. The second recess 109 may define a cutting area of the substrate 101. The substrate 101 may have a side surface 101c connected to the first surface 107a of the first recess 107. The side surface 101c of the substrate 101 may be substantially coplanar with the side surface 103c of the semiconductor element 103. The substrate 101 may include a base 101d and a protrusion 101 e. The substrate 101d may have a first surface 1011d facing away from the semiconductor element 103. The protrusion 101e may protrude from the first surface 1011d of the substrate 101 d. The side surfaces 1011e of the projections 101e are both angled at θ 1 and θ 2 greater than 90 ° to the first surface 1011d of the substrate 101d, such as, but not limited to, 100 °, 120 °, or 150 °. The substrate 101 may be any type of substrate, such as, but not limited to, a silicon substrate.

The semiconductor element 103 may be disposed on the substrate 101. The semiconductor element 103 may have a first surface 103a and a second surface 103b opposite to the first surface 103 a. The first surface 103a may face away from the substrate 101. The second surface 103b may face the substrate 101. The semiconductor element 103 may have a side surface 103c connected to the interface 105. The semiconductor device 103 may include one or more electronic devices, one or more metal layers, and/or one or more dielectric layers. The one or more electronic components may include any type of electronic component, such as resistors, capacitors, and/or transistors. The semiconductor element 103 may include a metal layer 103d adjacent to the interface 105. The metal layer 103d may overlap with a projected area of the first surface 107a of the first recess 107 on the semiconductor element 103. The metal layer 103d may overlap with a projected area of the first surface 109a of the second recess 109 on the semiconductor element 103.

In some embodiments of the present application, one complete side of the substrate 101 includes a first section made up of the side surface 107b of the first recess 107, and a second section made up of the side surface 101c of the substrate 101, wherein the first section is spaced from the second section by the first surface 107 a. And, the second section is coplanar with the side surface 103c of the semiconductor element 103.

The semiconductor device 10 provided by the present application can avoid removing the metal layer at the interface between the first etched (or cut) via and the second etched (or cut) via by disposing the first surface 107a of the first recess 107 in the substrate 101 so that the structure in the vicinity of the interface 105 is not affected when etching or cutting the semiconductor device 10 from the side of the semiconductor element 103 and when etching or cutting the semiconductor device 10 from the side of the substrate 101. Since the arrangement of the first recess 107 does not affect any structure in the vicinity of the interface 105, the alignment margin between the side where the semiconductor element 103 is located and the side where the substrate 101 is located can be optimized at any time, and the alignment margin can be flexibly enlarged to avoid misalignment between the first etched (or cut) through hole and the second etched (or cut) through hole. Therefore, the present application provides a semiconductor device 10 having a great flexibility in the arrangement of the alignment margin of the side where the semiconductor element 103 is located and the side where the substrate 101 is located, and avoids influencing the structure in the semiconductor device 10 at the time of dicing, thereby achieving higher production efficiency of the semiconductor device and higher quality of the semiconductor device.

Fig. 2 is a schematic longitudinal cross-sectional view of a semiconductor device 20 according to further embodiments of the present application. As shown in fig. 2, a semiconductor device 20 according to further embodiments of the present application may include: a substrate 201 and a semiconductor element 203. The semiconductor device 20 has a width in the horizontal direction and a height in the vertical direction.

The substrate 201 may have a first surface 201a and a second surface 201b opposite the first surface 201 a. The first surface 201a may face away from the semiconductor element 203. The second surface 201b may face the semiconductor element 203. The substrate 201 may have a side surface 201c between the first surface 201a and the second surface 201 b. The side surface 201c of the substrate 201 may be substantially coplanar with the side surface 203c of the semiconductor element 203. The substrate 201 may be any type of substrate such as, but not limited to, a silicon substrate.

The semiconductor device 203 may be disposed on the substrate 201. The semiconductor device 203 may have a first surface 203a and a second surface 203b opposite to the first surface 203 a. The first surface 203a may face away from the substrate 201. The second surface 203b may face the substrate 201. The semiconductor device 203 may have a side surface 203c connected to the interface 205. The semiconductor element 203 may comprise a first recess 207 extending from the first surface 203a of the semiconductor element 203 and terminating before the interface 205 between the substrate 201 and the semiconductor element 203. In some embodiments of the present application, the first recess 207 may extend from the first surface 203a of the semiconductor element 203 and terminate at the interface 205 between the substrate 201 and the semiconductor element 203. The first recess 207 may have a first surface 207a and a side surface 207 b. The first surface 207a may be substantially parallel to the first surface 203a of the semiconductor element 203. The side surface 207b may be connected to the first surface 207a of the first recess 207 and the first surface 203a of the semiconductor element 203. The side surface 207b may have an angle β 2 with the first surface 207a of the first notch 207 that is equal to or greater than 90 °, such as, but not limited to, 100 °, 120 °, or 150 °. The first recess 207 may be formed by any suitable etching process, such as, but not limited to, a plasma etching process or a laser etching process. The first notch 207 may define a cutting region of the semiconductor element 203. The semiconductor element 203 may further include a second recess 209. The second recess 209 may be substantially symmetrical to the first recess 207. The second recess 209 may have a first surface 209a and a side surface 209 b. The first surface 209a may be substantially parallel to the first surface 203a of the semiconductor element 203. The side surface 209b may be connected to the first surface 209a of the second recess 209 and the first surface 203a of the semiconductor element 203. The angle α 2 between the side surface 209b and the first surface 209a of the second recess 209 is equal to 90 ° or greater than 90 °, such as, but not limited to, 100 °, 120 °, or 150 °. Included angle α 2 and included angle β 2 may be the same or different. The second recess 209 may define a cutting region of the semiconductor element 203. The semiconductor device 203 may include a base 203d and a protrusion 203 e. The base 203d may have a first surface 2031d facing away from the substrate 201. The protrusion 203e may protrude from the first surface 2031d of the base 203 d. The side surface 2031e of the protrusion 203e forms an angle β 2 with the first surface 2031d of the base 203d substantially equal to 90 ° or greater than 90 °. The semiconductor device 203 may include a metal layer 203d adjacent to the interface 205. The metal layer 203d overlaps with a projection area of the first surface 209a of the second recess 209 on the semiconductor element 203. The second recess 209 defines a cutting region of the semiconductor element 203. The semiconductor device 203 may include one or more electronic devices, one or more metal layers, and/or one or more dielectric layers. The one or more electronic components may include resistors, capacitors, and/or transistors.

In some embodiments of the present application, the complete side of the semiconductor element 203 comprises a first section constituted by the side surface 207b of the first recess 207 and a second section constituted by the side surface 203c of the semiconductor element 203, wherein the first section is spaced from the second section by the first surface 207 a. And, the second section is coplanar with the side surface 201c of the substrate 201.

The semiconductor device 20 provided by the present application can avoid removing the metal layer at the interface between the first etched (or cut) via and the second etched (or cut) via by disposing the first surface 207a of the first recess 207 in the semiconductor element 203 so that the structure in the vicinity of the interface 205 is not affected when etching or cutting the semiconductor device 20 from the side of the semiconductor element 203 and when etching or cutting the semiconductor device 20 from the side of the substrate 201. Since the arrangement of the first recess 207 does not affect any structure near the interface 205, the alignment margin between the side where the semiconductor device 203 is located and the side where the substrate 201 is located can be optimized at any time, and the alignment margin can be flexibly enlarged to avoid the misalignment between the first etching via and the second etching via. Therefore, the present application provides a semiconductor device 20 having a great flexibility in the arrangement of the alignment margin between the side where the semiconductor element 203 is located and the side where the substrate 201 is located, and avoids influencing the structure in the semiconductor device 20 during dicing, thereby achieving higher production efficiency of the semiconductor device and higher quality of the semiconductor device.

The present application may be implemented by providing the first surface of the first recess in at least one of the substrate and the semiconductor element, i.e. such that the first recess extends from the first surface of the substrate and terminates before the interface between the substrate and the semiconductor element, or extend from the first surface of the substrate and terminate at or before the interface between the substrate and the semiconductor element, or extend from the first surface of the semiconductor element and terminate at the interface between the substrate and the semiconductor element, it is possible to avoid the influence of the structure in the semiconductor device at the time of dicing, and thus to realize an increase in the size of the arrangement of the alignment margin and flexibility in the setting position, thereby not only preventing the dislocation between the first etching or cutting through hole and the second etching or cutting through hole better, but also improving the production efficiency and the product quality of the semiconductor device.

Fig. 3A, 3B, and 3C are schematic flow diagrams of fabricating semiconductor devices, such as the semiconductor device 10 shown in fig. 1A, according to some embodiments of the present application.

As shown in fig. 3A, a semiconductor device is provided, which includes a substrate 101 and a semiconductor element 103 formed on the substrate 101.

As shown in fig. 3B, a first etching (or cutting) process may be performed first to form a first etched (or cut) via 107E extending through the semiconductor element 103 and into the substrate 101. The etching process may be selected as appropriate according to particular needs. For example, the semiconductor element 103 may be etched using a SiO or SiN dry etching process, and then the substrate 101 may be etched using a Si dry etching process, thereby forming the first etched (or cut) via 107E.

As shown in fig. 3C, a second etching process may then be performed to form a second etched (or cut) via 107F in communication with the first etched via 107E on the substrate 101. The second etched (or cut) via 107F may have a diameter larger than the first etched (or cut) via 107E to result in a plurality of semiconductor devices 10 such as shown in fig. 1A. The etching process may be selected as appropriate according to particular needs. For example, the substrate 101 may be etched using a Si dry etch process to form the second etched (or cut) via 107F.

The present application can avoid affecting the structure near the interface between the substrate 101 and the semiconductor element 103 by etching the first etched (or cut) via 107E from the semiconductor element 103 into the substrate 101.

Fig. 4A, 4B, and 4C are schematic flow diagrams of fabricating semiconductor devices according to other embodiments of the present application, which may fabricate, for example, the semiconductor device 20 shown in fig. 2.

As shown in fig. 4A, a semiconductor device is provided, which includes a substrate 201 and a semiconductor element 203 formed on the substrate 201.

As shown in fig. 4B, a first etching process may be performed first to form a first etching (or cutting) via 207E extending through the substrate 201 and into the semiconductor device 203. The etching process may be selected as appropriate according to particular needs. For example, the substrate 201 may be etched using a Si dry etch process, and then the semiconductor element 203 may be etched using a SiO or SiN dry etch process, thereby forming a first etched (or cut) via 207E.

As shown in fig. 4C, a second etching process may then be performed to form a second etched (or cut) via 207F on the semiconductor device 203 in connection with the first etched (or cut) via 207E. The second etched (or cut) via 207F may have a diameter larger than that of the first etched (or cut) via 207E to obtain a plurality of semiconductor devices 20 such as shown in fig. 2. The etching process may be selected as appropriate according to particular needs. For example, the semiconductor element 203 may be etched using a SiO or SiN dry etching process to form a second etched (or cut) via 207F.

The present application can avoid affecting the structure near the interface between the substrate 201 and the semiconductor element 203 by etching the first etched via 207E from the substrate 201 into the semiconductor element 203.

Fig. 5 is a schematic longitudinal cross-sectional view of a semiconductor device 50 according to further embodiments of the present application. As shown in fig. 5, the semiconductor device 50 includes a substrate 501 and a semiconductor element 503 provided over the substrate 501. A first recess 507 extends from the lower surface of the substrate 501 and through an interface 505 between the substrate 501 and the semiconductor element 503 to a dielectric layer 506 within the semiconductor element 503. The first recess 507 exposes the metal layer and the dielectric layer 506 near the interface 505. Unlike the embodiment illustrated in fig. 1A and 2 of the present application, the structure in the semiconductor element 503 is affected by the first recess 507, which limits the layout of the structure in the semiconductor element 503 and the arrangement of the first recess 507, and is not favorable for the production efficiency and the product quality of the semiconductor device 50.

The technical content and technical features of the present application have been disclosed as above, however, those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present application without departing from the spirit of the present application. Therefore, the protection scope of the present application should not be limited to the disclosure of the embodiments, but should include various substitutions and modifications without departing from the scope of the present application, and be covered by the claims of the present application.

Claims

1. A semiconductor device, characterized in that the semiconductor device comprises:

a substrate; and

a semiconductor element disposed on the substrate, wherein at least one of the substrate and the semiconductor element comprises a first recess, and the first recess is recessed from an outermost surface of the substrate, or the first recess is recessed from an outermost surface of the semiconductor element.

2. The semiconductor device according to claim 1, wherein the substrate has a first surface facing away from the semiconductor element, and wherein the substrate comprises the first recess extending from the first surface of the substrate and terminating before or at an interface between the substrate and the semiconductor element.

3. The semiconductor device according to claim 2, wherein the first recess has a first surface parallel to the first surface of the substrate, and a side surface connected to the first surface of the first recess and the first surface of the substrate, and wherein an angle between the side surface and the first surface of the substrate is greater than 90 °.

4. The semiconductor device according to claim 3, wherein the substrate further comprises a second recess, and wherein the second recess is symmetrical to the first recess.

5. The semiconductor device according to claim 3, wherein the substrate has a side surface connected to the first surface of the first recess, and the semiconductor element has a side surface connected to the interface, and wherein the side surface of the substrate is coplanar with the side surface of the semiconductor element.

6. The semiconductor device according to claim 1, wherein the semiconductor element has a first surface facing away from the substrate, and the semiconductor element comprises the first recess extending from the first surface of the semiconductor element and terminating before or at an interface between the substrate and the semiconductor element.

7. The semiconductor device according to claim 6, wherein the first recess has a first surface parallel to the first surface of the semiconductor element, and a side surface connected to the first surface of the first recess and the first surface of the semiconductor element, and wherein an angle between the side surface and the first surface of the first recess is equal to or greater than 90 °.

8. The semiconductor device according to claim 7, wherein the substrate has a side surface connected to the interface, and the semiconductor element has a side surface connected to the interface, and wherein the side surface of the substrate is coplanar with the side surface of the semiconductor element.

9. The semiconductor device according to claim 7, wherein the semiconductor element further comprises a second notch, and wherein the second notch is symmetrical to the first notch.

10. The semiconductor device according to claim 1, wherein the substrate comprises a base having a first surface facing away from the semiconductor element and a protrusion protruding from the first surface of the base.

11. The semiconductor device according to claim 10, wherein an angle between a side surface of the protruding portion and the first surface of the substrate is greater than 90 °.

12. The semiconductor device according to claim 1, wherein the semiconductor element comprises a base having a first surface facing away from the substrate and a protrusion protruding from the first surface of the base.

13. The semiconductor device according to claim 12, wherein an angle between a side surface of the protruding portion and the first surface of the substrate is equal to 90 ° or greater than 90 °.

14. The semiconductor device of claim 1, wherein the substrate is a silicon substrate and the semiconductor elements comprise one or more electronic elements, one or more metal layers, and/or one or more dielectric layers.

15. The semiconductor device according to claim 14, wherein the one or more electronic components comprise a resistor, a capacitor, and/or a transistor.

16. The semiconductor device according to claim 3, wherein the semiconductor element comprises a metal layer adjacent to the interface, and the metal layer overlaps with a projection area of the first surface of the first recess on the semiconductor element.

17. The semiconductor device according to claim 7, wherein the semiconductor element comprises a metal layer adjacent to the interface, and the metal layer overlaps with a projection area of the first surface of the first recess on the semiconductor element.

18. The semiconductor device of claim 1, wherein the first notch defines a cut region of the substrate.

19. The semiconductor device according to claim 6, wherein the first notch defines a cutting region of the substrate.