CN217363058U - Analog-digital converter circuit, analog-digital converter, and electronic apparatus - Google Patents

Abstract

The present application provides an analog-to-digital converter circuit, an analog-to-digital converter, and an electronic device, the analog-to-digital converter circuit, including: the full-parallel ADC is used for accessing an analog signal to be converted and quantizing the analog signal; the first-stage SAR ADC is connected with an analog signal, the control end of the highest-order capacitor of the first-stage SAR ADC is connected with the full-parallel ADC, and a residual error signal generated based on the analog signal and a signal quantized by the first-stage SAR ADC is quantized; the second-stage SAR ADC quantizes the accessed quantized signal again; the intermediate capacitor amplifier is arranged between the first-stage SARADC and the second-stage SARADC, comprises a first capacitor and a first operational amplifier which are connected in parallel, and a first switch which is connected with the first capacitor in series, wherein the first capacitor is used as a redundant bit capacitor of the second-stage SARADC, and the output result of the second-stage SARADC is calibrated. By the application of the ADC, the ADC with higher physical digit can be realized, and the conversion accuracy of the analog-digital converter circuit can be improved.

Description

Analog-to-digital converter circuits, analog-to-digital converters and electronic equipment

technical field

The present application belongs to the technical field of analog-to-digital conversion circuits, and in particular relates to an analog-to-digital converter circuit, an analog-to-digital converter and electronic equipment.

Background technique

Analog-to-digital converters (ADCs) can convert analog signals into digital signals and are the key means to obtain information about nature. As an important medium for obtaining information, ADC is widely used in wireless communication, industrial measurement, image recognition and other fields. With the further development of science and technology, there are more and more requirements for efficient acquisition of information in various fields, and the demand for high-speed and high-precision ADCs continues to increase.

There are many types of ADC, including: Sigma-Delta (Σ-Δ modulation) type, integral type, SAR (Successive Approximation, successive approximation) type, pipeline (pipeline) type, flash (full parallel), etc., and due to the high conversion of pipeline ADC The speed and low power consumption of SAR ADC have also resulted in the Pipeline SAR ADC (pipeline-primary and secondary approximation analog-to-digital converter), which is compatible with the excellent performance of pipeline ADC and SAR ADC.

Most of the existing Pipeline SARADC architectures include two SARADCs and an intermediate capacitor amplifier arranged between the two SAR ADCs. However, this ADC architecture often has the following defects. First, the pipeline SAR is difficult to achieve in terms of physical bits. Realize 13-15bit ADC; second, the output swing of the intermediate stage op amp is the difference between the two reference voltages (vrefp1 and vrefn1) of the previous stage SARADC, the voltage difference is large, which will greatly consume the voltage margin, Thereby increasing the power consumption requirements of the op amp.

SUMMARY OF THE INVENTION

The present application proposes an analog-to-digital converter circuit, an analog-to-digital converter, and an electronic device, which can realize an ADC with a higher physical number of bits, and can improve the conversion accuracy of the analog-to-digital converter circuit.

The embodiment of the first aspect of the present application provides an analog-to-digital converter circuit, including:

A fully parallel ADC is connected to the analog signal to be converted, and the analog signal is quantized to obtain a first quantized signal;

The first-stage SAR ADC is connected to the analog signal, and the control terminal of the highest-order capacitor is connected to the fully parallel ADC, and quantizes the residual signal generated based on the analog signal and the first quantized signal , and obtain the second quantized signal;

The second-stage SAR ADC quantizes the accessed quantized signal again to obtain a third quantized signal;

an intermediate capacitor amplifier disposed between the first-stage SAR ADC and the second-stage SAR ADC, including a first capacitor and a first operational amplifier connected in parallel, and a first switch connected in series with the first capacitor, and The first capacitor is used as a redundant bit capacitor of the second-stage SAR ADC to calibrate the output result of the second-stage SAR ADC.

In some embodiments of the present application, the first operational amplifier includes an amplifier module and a voltage adjustment module, the voltage adjustment module includes a MOS array, and the MOS array is used to adjust the gain-bandwidth product of the first operational amplifier.

In some embodiments of the present application, the voltage adjustment module includes a plurality of MOS arrays, and the sources and drains of the plurality of MOS arrays are connected end to end, and the first MOS array is adjusted by changing the number of the MOS arrays in the working state. The gain-bandwidth product of the op amp.

In some embodiments of the present application, the first operational amplifier has a power supply rejection ratio greater than or equal to a specified value.

In some embodiments of the present application, the first switch controls the first capacitor to be connected to the first-stage SARADC or the reference voltage power supply terminal, respectively; and when the first capacitor is connected to the reference voltage power supply terminal, use Used as a redundant bit capacitor of the second-stage SARADC to calibrate the output result of the second-stage SARADC; when the first capacitor is connected to the first-stage SARADC, it is used to quantify the second quantized signal Perform the specified magnification.

In some embodiments of the present application, a resistor array is further included, and the resistor array is disposed between the fully parallel ADC and the first-stage SAR ADC, and is used for adjusting the voltage of the first quantized signal.

In some embodiments of the present application, the resistor array includes a plurality of resistors connected in series, and an on-off switch is arranged between any two resistors.

In some embodiments of the present application, the fully parallel ADC is an ADC with a 4-bit physical number, the first-stage SAR ADC is an ADC with a 4-bit physical number, and the second-level SAR ADC is greater than or equal to For an ADC with 6 physical bits, the amplification factor of the intermediate capacitor amplifier is 8 times.

Embodiments of the second aspect of the present application provide an analog-to-digital converter, including the analog-to-digital converter circuit described in the first aspect.

Embodiments of the third aspect of the present application provide an electronic device, including a memory, a processor, a computer program stored on the memory and executable on the processor, and a digital logic circuit, the digital logic The circuit includes an analog-to-digital converter as described in the second aspect.

The technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

The analog-to-digital converter circuit provided by the embodiment of the present application includes a flash ADC, a first-stage SARADC, and a three-stage architecture ADC (may be called a Pipeline SAR ADC, pipeline-primary-sub-approximation analog-to-digital converter) , and connect both the flash ADC and the first-stage SARADC to the analog signal to be converted, and directly convert the analog signal through the flash ADC to generate the first quantized signal; The difference signal is quantized to obtain a second quantized signal; and then the second quantized signal is quantized again by the second-stage SARADC to obtain a final third quantized signal. In this way, through the Pipeline SAR ADC of the three-stage architecture, the three ADCs are processed in parallel, so that data conversion of more physical bits can be realized, and the working efficiency of the analog-to-digital converter circuit can be improved. In addition, the latter two SARADCs both quantize the residual signal, which has a correcting effect on the overall quantization result, and can improve the conversion accuracy of the analog-to-digital converter circuit. In addition, the first capacitor of the intermediate capacitor amplifier can be used to calibrate the redundant bits of the second-stage SAR ADC. On the basis of the original SAR bits, an additional bit can be added to make it possible to calibrate the error of the second-stage SAR ADC. , especially the set-up error of the SAR, the second-stage SAR ADC can modify the output result corresponding to each capacitor according to the output result of the comparator, thereby further improving the accuracy of the analog-to-digital converter circuit.

Description of drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are for purposes of illustrating preferred embodiments only and are not to be considered limiting of the application. Also, the same components are denoted by the same reference numerals throughout the drawings.

In the attached image:

FIG. 1 shows a schematic structural diagram of an analog-to-digital converter circuit provided by an embodiment of the present application;

FIG. 2 shows an enlarged schematic diagram of a resistor array in an embodiment of the present application;

FIG. 3 shows a schematic structural diagram of a first operational amplifier in an embodiment of the present application;

Figure 4a shows a schematic diagram of the binary conversion process of a conventional SAR ADC;

Figure 4b shows a schematic diagram of the binary conversion process of the SAR ADC under the influence of the mechanical error and settling error of the comparator;

FIG. 4c shows a schematic diagram of the binary conversion process of the SAR ADC with redundant bit calibration in the embodiment of the present application;

Fig. 5a shows a schematic diagram of the intermediate capacitor amplifier in the amplification working mode when the first switch is closed in the embodiment of the present application;

Fig. 5b shows a schematic diagram of the intermediate capacitor amplifier in the calibration working mode when the first switch is turned off in the embodiment of the present application;

FIG. 6 shows a schematic flowchart of the analog-to-digital conversion method provided in the embodiment of the present application.

Detailed ways

Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the application will be more thoroughly understood, and will fully convey the scope of the application to those skilled in the art.

It should be noted that, unless otherwise specified, the technical or scientific terms used in this application should have the usual meanings understood by those skilled in the art to which this application belongs.

The following describes an analog-to-digital converter circuit, an analog-to-digital converter, and an electronic device according to the embodiments of the present application with reference to the accompanying drawings.

Please refer to FIG. 1 , an analog-to-digital converter circuit provided in this embodiment, as shown in FIG. 1 , the circuit includes: a fully parallel ADC (flash ADC, also known as a flash analog-to-digital converter), a first-stage SAR ADC ( successive approximation analog-to-digital converter), intermediate capacitor amplifier and second-stage SARADC.

The input end of the fully parallel ADC is connected to the analog signal to be converted, and the analog signal is quantized to obtain a first quantized signal. The first-stage SARADC is connected to the analog signal, and the control terminal of the highest-order capacitor is connected to the full-parallel ADC, and quantizes the residual signal generated based on the analog signal and the first quantized signal to obtain the second quantized signal. The second-stage SARADC quantizes the accessed quantized signal again to obtain a third quantized signal. The intermediate capacitor amplifier is arranged between the first-stage SARADC and the second-stage SARADC, and is used to amplify the second quantized signal by a specified multiple, and input the amplified quantized signal to the second-stage SARADC.

Specifically, the flash ADC may be an ADC with a 4-bit physical number, the first-stage SARADC may be an ADC with a 4-bit physical number, and the second-level SARADC may be an ADC with a 6-bit physical number. In this way, due to the setting of the 4bit flash ADC, the number of bits that can be converted by the analog-to-digital converter circuit can be increased to 13 bits, and the number of bits of the second-stage SARADC can be increased as required to achieve higher physical bits, Such as 15-bit, 16-bit, 18-bit, etc. The specified multiple of the second quantized signal by the intermediate capacitor amplifier may be a multiple of 4, which may be specifically set according to the actual situation. The final output result of the analog-to-digital converter circuit is the sum of the output results of the flash ADC, the first-stage SARADC, and the second-stage SARADC.

In another specific implementation of this embodiment, as shown in FIG. 1 , the analog-to-digital converter circuit may further include a resistor array, and the resistor array is arranged between the flash ADC and the first-stage SARADC for adjusting the first quantized signal. voltage. In this way, after the analog-to-digital conversion of the flash ADC is completed, the outputted first quantized signal controls the output voltage of the resistor array, and the output voltage can control the highest-order capacitance of the first-stage SARADC.

Specifically, as shown in FIG. 2 , the resistor array may include a plurality of resistors connected in series, and an on-off switch is arranged between any two resistors. The given reference voltage Vref and the flash ADC output signal are used to control the resistors in the resistor array. The on-off switch of each on-off switch is used to control the resistance value of the resistor array and realize the voltage control of the highest-order capacitance of the first-stage SARADC, so that the desired voltage can be provided for the highest-order capacitance of the first-stage SARADC according to the needs. A corresponding residual signal is generated.

It should be noted that this embodiment does not specifically limit the specific circuit structures of the flash ADC, the first-stage SARADC, and the second-stage SARADC, as long as the above-mentioned respective functions can be performed.

The analog-to-digital converter circuit provided in this embodiment includes a flash ADC, a first-stage SARADC, and a three-stage architecture ADC (which may be referred to as a Pipeline SAR ADC, a pipeline-primary-secondary approximation analog-to-digital converter), The flash ADC and the first-stage SARADC are connected to the analog signal to be converted, and the analog signal is directly converted by the flash ADC to generate a first quantized signal; the residual difference between the analog signal and the first quantized signal is converted by the first-stage SARADC The signal is quantized to obtain a second quantized signal; and then the second quantized signal is quantized again by the second-stage SARADC to obtain a final third quantized signal. In this way, through the Pipeline SAR ADC of the three-stage architecture, the three ADCs are processed in parallel, so that data conversion of more physical bits can be realized, and the working efficiency of the analog-to-digital converter circuit can be improved. In addition, the latter two SARADCs both quantize the residual signal, which has a correcting effect on the overall quantization result, and can improve the conversion accuracy of the analog-to-digital converter circuit.

This embodiment further describes the structures and functions of the first-stage SAR ADC, the second-stage SAR ADC, and the intermediate capacitor amplifier by taking the implementation of a 13-bit Pipeline SAR ADC as an example.

As shown in Figure 1, the first-stage SAR ADC includes a comparator, a logic control circuit and a plurality of capacitors arranged according to binary weighting. Control circuit, and receive the analog signal to be converted and its logic control signal. The voltage control terminal of the lowest bit capacitor is connected to the reference voltage (Vcm1), the voltage control terminal of the highest bit capacitor (the lowest is 32 times the capacitance) is connected to the output terminal of the flash ADC, and the highest bit is controlled by the flash ADC (and the resistor array). The supply voltage of the capacitor, the voltage control terminals of other capacitors are free terminals, and the connected reference voltage (Vrefp1-Vrefn1) can be selected according to the logic control signal.

The structure of the second-stage SAR ADC is similar to that of the first-stage SAR ADC. It also includes a comparator, a logic control circuit, and a plurality of capacitors (with different numbers of capacitors) arranged according to binary weighting. One end connected to the middle horizontal line) is respectively connected to the comparator and the logic control circuit, and receives the above-mentioned second quantization signal and its logic control signal. The voltage control terminal of the lowest capacitor is still connected to the reference voltage (Vcm2), and the voltage control terminals of other capacitors (including the highest capacitor) are free terminals, and the connected reference voltage (Vrefp2-Vrefn2) can be selected according to the logic control signal.

The intermediate capacitor amplifier may include a first capacitor and a first operational amplifier connected in parallel, and the first operational amplifier has a high power supply rejection ratio greater than or equal to a specified value, so as to further improve the conversion accuracy of the analog-to-digital converter.

The input and output of the power supply are regarded as independent signal sources, and the ratio of the input to the output ripple is the power supply rejection ratio, also known as the power supply ripple rejection ratio (unit is dB). For high-quality analog-to-digital converters, it is usually required that when the power supply voltage used by the switching circuit and the operational amplifier changes, the output voltage has little effect. Power supply rejection ratio. The larger the power supply rejection ratio, the less the output signal is affected by the power supply, and the corresponding unity gain bandwidth is higher.

In view of the fact that the intermediate capacitor amplifier of this embodiment adopts an operational amplifier with a high power supply rejection ratio, and the corresponding unity gain bandwidth is relatively high, the amplification factor of the intermediate capacitor amplifier can be set to a smaller multiple. For example, for an existing operational amplifier with a similar configuration of 16 times, the amplification factor can be set to 8 times in this embodiment. In this way, the reference voltage and output voltage of the first-stage SAR ADC are also reduced accordingly, and the input voltage and reference voltage of the second-stage SAR ADC are also correspondingly reduced, that is, the voltage margin is reduced, so that the analog-to-digital converter circuit can be reduced. The power consumption of the overall op amp.

For example, the amplification factor of the intermediate capacitor amplifier of the traditional pipeline SAR ADC is 16 times, and the output swing is Vrefp1'-Vrefn1'. The amplification factor of the intermediate capacitor amplifier in this embodiment is changed from 16 times to 8 times, so its output swing Vrefp1-Vrefn1 becomes 0.5 times Vrefp1'-Vrefn1'. At the same time, the first capacitor will change from 4 times the capacitance to 8 times the capacitance, and the output swing amplitude Vrefp2-Vrefn2 of the second stage SAR ADC also becomes 0.5 times Vrefp2'-Vrefn2' (the second stage of the traditional pipeline SAR ADC output swing of the SAR ADC).

It should be noted that this embodiment does not specifically limit the specific value of the high power supply rejection ratio of the first operational amplifier, and those skilled in the art can set it according to actual needs, as long as it is higher than the power supply rejection ratio of the conventional operational amplifier. Can.

As shown in FIG. 3 , the above-mentioned first operational amplifier may include an amplifier module and a voltage adjustment module, the voltage adjustment module includes a MOS array, and the MOS array is used to adjust the gain-bandwidth product of the first operational amplifier. Wherein, the MOS array may include multiple ones, for example, the MOS array 1 to the MOS array 5 in FIG. 3 , and the bandwidth of the first operational amplifier can be adjusted more finely. The first operational amplifier has its own MOS array, through which the gain-bandwidth product (gain-bandwidth product, GBW, refers to the product of an amplifier's bandwidth and its corresponding gain) can be configured according to the design environment of the ADC. Moreover, when configuring the GBW of the first operational amplifier, not only the bandwidth of the first operational amplifier itself needs to be adjusted, but the MOS array (MOS array 5 in FIG. 3 ) in the voltage adjustment module will also be synchronized with the current of the first operational amplifier increase, so that the voltage adjustment module always works in the optimal region, which further reduces the overall power consumption, working efficiency, and conversion accuracy of the first operational amplifier.

Specifically, as shown in FIG. 3 , the connection manners between the multiple MOS arrays can be set as required, and this embodiment does not specifically limit them. For example, the sources and drains of different MOS arrays can be connected end to end, and the gain-bandwidth product of the first operational amplifier can be adjusted by changing the number of MOS arrays in the working state.

It should be noted that, the structure of the above-mentioned first operational amplifier is only an example of the present embodiment, and the present embodiment is not limited thereto, and may also include more MOS transistors and other electronic devices.

In a specific implementation of this embodiment, the intermediate capacitor amplifier further includes a first switch, the first switch is connected in series with the first capacitor, and the first capacitor is controlled to be connected to the first-stage SARADC or the reference voltage power supply terminal; the first capacitor is connected to the reference voltage supply terminal. When the voltage supply terminal is connected, the first capacitor is used as a redundant bit capacitor of the second-stage SARADC, and the redundant bit calibration is performed on the output result of the second-stage SARADC.

In the application process of ADC, the establishment of the analog-to-digital conversion function after each electronic component is started requires a process and a certain time, that is, the ADC establishment process. During the establishment process, an error may occur in a certain link. For example, due to the untimely processing time, Some data are not compared, resulting in erroneous comparison results, which can be called establishment errors. At the same time, the comparator itself also has certain mechanical errors. In this way, the pipeline SAR ADC may generate certain errors in the application process.

As shown in Figure 4a-4c (the ordinate in the figure represents the voltage, the abscissa in the figure represents the time, B0-B3 represent 4 bits respectively, the column can represent the voltage value, the broken line in the figure is the signal intensity change curve collected by the ADC, The value of B0-B3 corresponding to the rising of the broken line is 1, and the value of B0-B3 corresponding to the falling or unchanged broken line is 0). Figure 4a (in the figure) shows the binary conversion process of the traditional SARADC, and the output result of the SARADC is Dout=8 *B3+4*B2+2*B1+1*B0=8*0+4*1+2*0+1*0=4. Figure 4b shows that due to the influence of the mechanical error and setup error of the comparator, the output will produce an erroneous comparison result, resulting in the output result of the SARADC as Dout=8*B3+4*B2+2*B1+1*B0=8* 0+4*0+2*1+1*1=3, that is, the SARADC outputs the wrong conversion result. In Figure 4c, due to the redundant bit alignment of the B2' bit, the output returns to the normal comparison result. The output result of the SARADC is Dout=8*B3+4*B2+4*(B2'-0.5) +2*B1+1*B0=8*0+4*0+4*(1-0.5)2*1+1*1=4.

The intermediate capacitor amplifier of this embodiment is provided with a first switch connected in series with the first capacitor. As shown in FIG. 5a, when the first switch is closed and the first capacitor is connected to the first-stage SARADC, the first capacitor only serves as a Capacitance of the intermediate capacitor amplifier. The operation mode of the intermediate capacitor amplifier is the amplification mode, which can amplify the second quantized signal output by the first-stage SAR ADC (for example, amplify it by 8 times), and use it as the quantized signal of the second-stage SAR ADC after amplification. As shown in Figure 5b, when the first switch is turned off, the first capacitor is connected to the reference voltage power supply terminal. At this time, the first capacitor can be used as a redundant bit capacitor of the second-stage SARADC, which can affect the output of the second-stage SARADC. The result is redundant bit calibration. In this way, using the first capacitor of the intermediate capacitor amplifier, the redundant bit of the second-stage SARADC can be calibrated. On the basis of the original SAR bit, an additional bit is added to make it more accurate. The error of the quasi-second-stage SAR ADC, especially the set-up error of the SAR, the second-stage SAR ADC can modify the output result corresponding to each capacitor according to the output result of the comparator, thereby further improving the accuracy of the analog-to-digital converter circuit . In addition, through the setting of the first switch, the first capacitor can play a role in both the above-mentioned working modules, which is equivalent to the reuse of the capacitor, and there is no need to specially set a redundant capacitor, thereby reducing the overall development cost.

Based on the same concept of the above analog-to-digital converter circuit, this embodiment also provides an analog-to-digital conversion method, as shown in FIG. 6 , the method includes the following steps:

In step S1, the analog signal to be converted is quantized by the fully parallel ADC, and the first quantized signal obtained by quantization is input to the first-stage SAR ADC;

Step S2, the residual signal generated based on the analog signal and the first quantized signal is quantized by the first-stage SAR ADC, and the second quantized signal obtained by quantization is input to the intermediate capacitor amplifier;

Step S3, the second quantized signal is amplified by a specified multiple through the intermediate capacitor amplifier, and the amplified quantized signal is input to the second-stage SAR ADC;

Step S4, the amplified quantized signal is quantized again by the second-stage SAR ADC to obtain a third quantized signal.

It should be noted that this method can be applied to the above-mentioned analog-to-digital converter circuit, and can also be applied to other circuits, as long as the analog-to-digital conversion method can be implemented.

In the analog-to-digital conversion method provided in this embodiment, both the flash ADC and the first-stage SARADC are connected to the analog signal to be converted, and the analog signal is directly converted by the flash ADC to generate the first quantized signal; the analog signal is converted by the first-stage SARADC to the analog signal. Perform quantization with the residual signal of the first quantized signal to obtain a second quantized signal; and then re-quantize the second quantized signal through the second-stage SARADC to obtain a final third quantized signal. In this way, through the Pipeline SAR ADC of the three-stage architecture, the three ADCs are processed in parallel, so that data conversion of more physical bits can be realized, and the working efficiency of the analog-to-digital converter circuit can be improved. In addition, the latter two SAR ADCs both quantize the residual signal, which has a correcting effect on the overall quantization result, and can improve the conversion accuracy of the analog-to-digital converter circuit.

Based on the same concept of the above analog-to-digital converter circuit, the present embodiment further provides an analog-to-digital converter, including the analog-to-digital converter circuit of any of the above embodiments.

The analog-to-digital converter provided in this embodiment is based on the same concept as the analog-to-digital converter circuit described above, so at least the beneficial effects that the analog-to-digital converter circuit can achieve can be achieved, which will not be repeated here.

Based on the same concept as the above analog-to-digital converter circuit, this embodiment also provides an electronic device, the electronic device includes a memory, a processor, a computer program stored in the memory and running on the processor, and a digital logic circuit , the digital logic circuit includes an analog-to-digital converter as described above. Specifically, the electronic device may be a micro-control unit (MCU) including the above-mentioned analog-to-digital converter, or a chip formed with the micro-control unit, and the above-mentioned wireless charging system, motor control system (or only system using the chip) control equipment) etc.

The electronic device provided in this embodiment is based on the same concept as the analog-to-digital converter circuit described above, so at least the beneficial effects that can be achieved by the analog-to-digital converter circuit can be achieved, which will not be repeated here.

It should be noted that the above-described embodiments illustrate rather than limit the application, and alternative embodiments may be devised by those skilled in the art without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, and third, etc. do not denote any order. These words can be interpreted as names.

The above are only the preferred embodiments of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, All should be covered within the scope of protection of this application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. an analog-to-digital converter circuit, is characterized in that, comprises: A fully parallel ADC is connected to the analog signal to be converted, and the analog signal is quantized to obtain a first quantized signal; The first-stage SARADC is connected to the analog signal, and the control terminal of the highest-order capacitor is connected to the full-parallel ADC, and quantizes the residual signal generated based on the analog signal and the first quantized signal, and obtain the second quantized signal; The second-stage SARADC performs re-quantization on the connected quantized signal to obtain a third quantized signal; an intermediate capacitor amplifier, disposed between the first-stage SARADC and the second-stage SARADC, including a first capacitor and a first operational amplifier connected in parallel, and a first switch connected in series with the first capacitor, and the The first capacitor is used as a redundant bit capacitor of the second-stage SARADC to calibrate the output result of the second-stage SARADC. 2 . The circuit according to claim 1 , wherein the first operational amplifier includes an amplifier module and a voltage adjustment module, the voltage adjustment module includes a MOS array, and the MOS array is used to adjust the first operation. 3 . The gain-bandwidth product of the amplifier. 3 . The circuit according to claim 2 , wherein the voltage adjustment module comprises a plurality of MOS arrays, and the sources and drains of the plurality of MOS arrays are connected end to end, by changing the number of the MOS arrays in the working state. 4 . to adjust the gain-bandwidth product of the first operational amplifier. 4. The circuit of claim 1, wherein the first operational amplifier has a power supply rejection ratio greater than or equal to a specified value. 5 . The circuit according to claim 2 , wherein the first switch controls the first capacitor to be connected to the first-stage SARADC or a reference voltage power supply terminal, respectively; and the first capacitor is connected to the reference voltage. 6 . When the power supply terminal is connected, it is used as a redundant bit capacitor of the second-stage SARADC to calibrate the output result of the second-stage SARADC; when the first capacitor is connected to the first-stage SARADC, it is used to The second quantized signal is amplified by a specified factor. 6 . The circuit according to claim 1 , further comprising a resistor array, the resistor array is arranged between the fully parallel ADC and the first-stage SARADC, and is used to adjust the first quantized signal. 7 . voltage. 7 . The circuit according to claim 6 , wherein the resistor array comprises a plurality of resistors connected in series, and an on-off switch is arranged between any two resistors. 8 . 8 . The circuit according to claim 1 , wherein the fully parallel ADC is an ADC with a 4-bit physical number, the first-stage SARADC is an ADC with a 4-bit physical number, and the second-level SARADC For an ADC with a physical number of bits greater than or equal to 6 bits, the amplification factor of the intermediate capacitor amplifier is 8 times. 9. An analog-to-digital converter, characterized by comprising the analog-to-digital converter circuit of any one of claims 1-8. 10. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and running on the processor, characterized in that it also includes a digital logic circuit, the digital logic circuit comprising as claimed in claim 1 . The analog-to-digital converter described in claim 9.

Images