CN216902933U - Packaging structure and module structure of power semiconductor module compatible with multiple topologies - Google Patents
Packaging structure and module structure of power semiconductor module compatible with multiple topologies Download PDFInfo
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- CN216902933U CN216902933U CN202220289954.9U CN202220289954U CN216902933U CN 216902933 U CN216902933 U CN 216902933U CN 202220289954 U CN202220289954 U CN 202220289954U CN 216902933 U CN216902933 U CN 216902933U
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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Abstract
The utility model relates to the technical field of power semiconductor module packaging, and discloses a packaging structure and a module structure of a multi-topology compatible power semiconductor module, wherein the packaging structure comprises an insulating substrate, and the insulating substrate comprises an insulating plate; a conductive plate disposed at one side of the insulating plate, the conductive plate having a plurality of notches etched therein to divide the conductive plate into a plurality of conductive regions; and the heat dissipation plate is arranged on the other side of the insulation plate. According to the technical scheme, the packaging structure and the module structure of the power semiconductor module compatible with multiple topologies, provided by the utility model, have the advantages that the power semiconductor chips are respectively arranged on the multiple areas and are connected with the circuit loop through the conductive assembly so as to realize high integration of the power semiconductor module, so that the power semiconductor module is compatible with multiple forms of power electronic circuit topologies, and the universality is high; meanwhile, the packaging structure adopts an insulating substrate, which is beneficial to reducing the thermal resistance of a system.
Description
Technical Field
The utility model relates to the technical field of power semiconductor module packaging, in particular to a packaging structure and a module structure of a multi-topology compatible power semiconductor module.
Background
A power electronic converter is a power device circuit topology that converts power from ac/dc to ac/dc.
At present, in order to improve the integration degree of the system, the power semiconductor devices may be packaged into power semiconductor modules of a specific topology, which contributes to the compact design of the whole system. However, the power semiconductor module has insufficient versatility and is sometimes inconvenient to expand in parallel; in addition, the single tube of the existing power semiconductor device is mostly packaged by TO, and an insulating substrate is required TO be added, so that the thermal resistance of the system is high.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the problems of insufficient universality and high system thermal resistance of a power semiconductor module in the prior art, and provides a packaging structure and a module structure of a power semiconductor module compatible with multiple topologies.
In order to achieve the above object, an aspect of the present invention provides a package structure of a multi-topology compatible power semiconductor module, including:
an insulating substrate comprising:
an insulating plate;
a conductive plate disposed at one side of the insulating plate, the conductive plate having a plurality of notches etched therein to divide the conductive plate into a plurality of conductive regions;
the heat dissipation plate is arranged on the other side of the insulating plate;
the power semiconductor chips are respectively arranged on the conductive areas, and one electrode of each power semiconductor chip is electrically connected with the conductive area;
the conductive component is connected with the other electrode of the power semiconductor chip so as to connect the power semiconductor chip into a circuit loop where the packaging structure is located;
and the plastic package shell is sleeved outside the insulating substrate and the plurality of power semiconductor chips, and one side of the heat dissipation plate, which is far away from the insulating plate, extends out of the plastic package shell.
Optionally, the conductive component includes a plurality of bonding wires, one end of each bonding wire is connected to the other electrode of the corresponding power semiconductor chip, and the other end of each bonding wire is connected to the next adjacent conductive region.
Optionally, the conductive assembly further includes a first lead frame, one end of the first lead frame is connected to the last conductive region, and the other end of the first lead frame penetrates through the plastic package housing and extends to the outside of the plastic package housing.
Optionally, the first lead frames are multiple, and the other ends of the multiple first lead frames are located on the same side of the plastic package housing.
Optionally, the conductive assembly includes a plurality of second lead frames, one end of each second lead frame is connected to another corresponding electrode of the power semiconductor chip, the other end of each second lead frame is connected to the next adjacent conductive region, and the other end of the last second lead frame passes through the plastic package housing and extends to the outside of the plastic package housing.
Optionally, the insulating substrate is an alumina DBC substrate.
Optionally, a plurality of the power semiconductor chips are soldered/sintered with the conductive plate.
In another aspect, the present invention further provides a module structure of a multi-topology compatible power semiconductor module, including:
a liquid-cooled radiator;
a plurality of the package structures as described in any of the above, the plurality of package structures being arranged side-by-side along the side wall of the liquid-cooled heat sink;
and the laminated power bus bar is sleeved on the conductive components of the packaging structures and is used for connecting the direct-current bus capacitor and the power semiconductor chips in the packaging structures to form a conversion circuit.
Optionally, a limiting groove is formed in the side wall of the liquid cooling radiator, and the limiting groove is used for installing a plurality of the packaging structures.
Optionally, one side of the heat dissipation plate of the package structure is attached to the side wall of the liquid cooling radiator.
According to the technical scheme, the packaging structure and the module structure of the power semiconductor module compatible with multiple topologies, provided by the utility model, have the advantages that the multiple power semiconductor chips are respectively arranged on the multiple areas and are connected with the circuit loop through the conductive assembly so as to realize high integration of the power semiconductor module, so that the power semiconductor module is compatible with multiple forms of power electronic circuit topologies, and the universality is high; meanwhile, the packaging structure adopts an insulating substrate, which is beneficial to reducing the thermal resistance of the system.
Drawings
Fig. 1 is a schematic structural diagram of a packaging structure of a multi-topology compatible power semiconductor module according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a packaging structure of a multi-topology compatible power semiconductor module according to an embodiment of the present invention;
FIG. 3 is an exemplary diagram of a package structure of a multi-topology compatible power semiconductor module according to one embodiment of the utility model;
FIG. 4 is a schematic diagram of the circuit of FIG. 3;
FIG. 5 is a layout diagram of FIG. 3;
FIG. 6 is an exemplary diagram of a module structure of a multi-topology compatible power semiconductor module according to one embodiment of the utility model;
FIG. 7 is an exemplary diagram of a package structure of a multi-topology compatible power semiconductor module according to one embodiment of the utility model;
FIG. 8 is a schematic diagram of the circuit of FIG. 7;
fig. 9 is an exemplary diagram of a module structure of a multi-topology compatible power semiconductor module according to an embodiment of the present invention;
FIG. 10 is a top view of FIG. 8;
fig. 11 is a schematic diagram of the circuit of fig. 9.
Description of the reference numerals
01. Power semiconductor chip 02 and bonding wire
03. Conductive plate 04 and insulating plate
05. Heat dissipation plate 06, insulating substrate
07. First lead frame 08 and plastic package shell
09. Second lead frame 10, liquid cooling radiator
11. Laminated power bus bar 12 and limiting groove
13. Power terminal 14, gate drive terminal
15. Gate resistor 16, diode
17. MOS tube
Detailed Description
The following detailed description of embodiments of the utility model refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
Fig. 1 is a schematic structural diagram of a packaging structure of a multi-topology compatible power semiconductor module according to an embodiment of the present invention; fig. 2 is a schematic structural diagram of a packaging structure of a multi-topology compatible power semiconductor module according to an embodiment of the present invention. In fig. 1 and 2, the package structure may include an insulating substrate 06, a plurality of power semiconductor chips 01, a conductive assembly, and a mold housing 08. Specifically, the insulating substrate 06 may include an insulating plate 04, a conductive plate 03, and a heat dissipation plate 05. Specifically, the conductive plate 03 may include a notch and a conductive region.
The conductive plate 03 is disposed at one side of the insulating plate 04, a plurality of notches are etched on the conductive plate 03 to divide the conductive plate 03 into a plurality of conductive regions, and the heat dissipation plate 05 is disposed at the other side of the insulating plate 04. The plurality of power semiconductor chips 01 are respectively arranged on the plurality of conductive areas, and one electrode of each power semiconductor chip 01 is electrically connected with the conductive area. The conductive element is connected to the other electrode of the power semiconductor chip 01 to connect the power semiconductor chip 01 to the circuit loop in which the package structure is located. The plastic package casing 08 is sleeved outside the insulating substrate 06 and the plurality of power semiconductor chips 01, and one side of the heat dissipation plate 05, which is far away from the insulating plate 04, extends out of the plastic package casing 08.
The plurality of power semiconductor chips 01 are respectively arranged on the plurality of conductive areas and connected with the corresponding conductive areas, and the conductive component connects the plurality of power semiconductor chips 01 into a circuit loop where the power semiconductor chips are located, so that high integration of the power semiconductor module is realized. Meanwhile, the insulating substrate 06 is adopted in the packaging structure, and the insulating substrate does not need to be added, so that the use of thermal interface materials is reduced. One side of the heat dissipation plate 05 extends out of the plastic package shell 08, which is more beneficial to heat dissipation of the plurality of power semiconductor chips 01.
The traditional power semiconductor packaging structure has the defects of poor universality, inconvenience for parallel expansion, adoption of TO packaging, and high thermal resistance of a system due TO the need of an additional insulating substrate. In a preferred mode of the utility model, the insulating substrate 06 and the plastic package casing 08 with specific sizes are adopted, the power semiconductor chip 01 can be mounted on different conductive areas according to actual requirements, and the power semiconductor chip 01 and the conductive areas are connected through the conductive assembly to form different circuit topologies, so that the purpose of being compatible with various forms of power electronic circuit topologies is achieved, and the utility model is more flexible and reliable. Meanwhile, compared with the traditional TO single-tube package, the packaging structure has higher integration level and more compact system structure, so that the power density of the packaging structure is further improved; and an additional insulating substrate is not needed, which is beneficial to reducing the thermal resistance of the system.
In this embodiment of the utility model, as shown in fig. 1, the conductive assembly may include a plurality of bonding wires 02 and a first lead frame 07.
One end of each bonding wire 02 is connected to the other electrode of the corresponding power semiconductor chip 01, and the other end of each bonding wire 02 is connected to the next adjacent conductive region. One end of the first lead frame 07 is connected to the last conductive region, and the other end of the first lead frame 07 passes through the plastic package casing 08 and extends to the outside of the plastic package casing 08.
A plurality of bonding wires 02 can connect the plurality of power semiconductor chips 01 on the plurality of conductive areas and connect the plurality of power semiconductor chips 01 into a circuit loop in which they are located through the first lead frame 07. The first lead frame 07 is matched with the bonding wires 02, so that the packaging structure is more stable and reliable in connection.
In the embodiment of the present invention, specific materials for the bonding wire 03 include, but are not limited to, aluminum wire bonding, aluminum ribbon bonding, copper wire bonding, and the like.
In the embodiment of the present invention, since the package structure needs to be connected to a circuit loop, the number of the first lead frames 07 is plural. In order to improve the convenience and reliability of connection of the plurality of package structures, the other ends of the plurality of first lead frames 07 are located on the same side of the plastic package casing 08.
In this embodiment of the present invention, as shown in fig. 2, the conductive assembly may include a plurality of second lead frames 09.
One end of each second lead frame 09 is connected to the other electrode of the corresponding power semiconductor chip 01, the other end of each second lead frame 09 is connected to the next adjacent conductive region, and the other end of the last second lead frame 09 passes through the plastic package casing 08 and extends to the outside of the plastic package casing 08.
The second lead frames 09 can connect the power semiconductor chips 01 in the conductive areas, and the last second lead frame 09 connects the power semiconductor chips 01 into the circuit loop where the last second lead frame 09 is located, so that the package structure is more stable and reliable in connection.
In this embodiment of the present invention, the specific material for the insulating substrate 06 may be in various forms known to those skilled in the art, such as an aluminum oxide DBC substrate, an aluminum nitride AMB substrate, a silicon nitride AMB substrate, an insulating metal substrate IMS, and the like. In a preferred example of the present invention, however, the insulating substrate 06 is an alumina DBC substrate in view of the insulation and reliability of the insulating substrate 06.
In this embodiment of the present invention, the connection method for the power semiconductor chip 01 and the conductive plate 03 includes, but is not limited to, soldering, sintering, and the like.
In this embodiment of the present invention, the connection manner for the second lead frame 09 and the other electrode of the power semiconductor chip 01 may be in various forms known to those skilled in the art, such as soldering, sintering, and the like. However, in a preferred example of the present invention, the second lead frame 09 is connected to the other electrode of the power semiconductor chip 01 by soldering in consideration of the reliability of the connection of the second lead frame 09 to the other electrode of the power semiconductor chip 01.
FIG. 3 is an exemplary diagram of a package structure of a multi-topology compatible power semiconductor module according to one embodiment of the utility model; FIG. 4 is a schematic diagram of the circuit of FIG. 3; fig. 5 is a layout diagram of fig. 3. In fig. 3, 4 and 5, the package structure may include an insulating substrate 06, a plastic package 08, a bonding wire 02, three power terminals 13, four gate driving terminals 14, four gate resistors 15, two diodes 16 and two MOS transistors 17. Specifically, the insulating substrate 06 may include seven conductive regions.
The seven conductive areas are distributed in parallel on the top of the insulating plate 04, one end of each of the three power terminals 13 is connected with the middle three conductive areas, and the other end of each of the three power terminals 13 penetrates through the plastic package casing 08 and extends to the outside of the plastic package casing 08. The four gate drive terminals 14 are respectively connected with the four conductive regions on the two sides, and the other ends of the four gate drive terminals 14 penetrate through the plastic package casing 08 and extend to the outside of the plastic package casing 08. The two MOS tubes 17 are respectively arranged on a first conductive region and a second conductive region from left to right of the middle three conductive regions, and drain electrodes of the two MOS tubes 17 are respectively connected with the first conductive region and the second conductive region; the source electrode of the MOS tube 17 on the first conductive region is connected with the second conductive region through a bonding wire 02, and the source electrode of the MOS tube 17 on the second conductive region is connected with the third conductive region from left to right of the middle three conductive regions through the bonding wire 02; the source of the MOS transistor 17 in the first conductive region is connected to the leftmost conductive region through a bonding wire 02, and the source of the MOS transistor 17 in the second conductive region is connected to the rightmost conductive region through a bonding wire 02. The two diodes 16 are respectively arranged on the first conductive area and the second conductive area, and the cathodes of the two diodes 16 are respectively connected with the first conductive area and the second conductive area; the anode of the diode 16 on the first conductive region is connected to the second conductive region through a bonding wire 02, and the anode of the diode 16 on the second conductive region is connected to the third conductive region through a bonding wire 02. The four gate resistors 15 are grouped pairwise, the two groups of gate resistors 15 are respectively arranged on the two conductive regions on the two sides of the middle three conductive regions and are connected with the corresponding conductive regions, the gate electrode and the diode 16 of the MOS tube 17 on the first conductive region are connected with the two adjacent gate resistors 15 through the bonding wire 02, and the gate electrode and the diode 16 of the MOS tube 17 on the second conductive region are connected with the other two gate resistors 15 through the bonding wire 02.
The MOS tube 17 and the diode 16 are connected in parallel on the same conductive region, and the source and the drain of the two MOS tubes 17 are connected to form an internal half-bridge circuit topology.
In this embodiment of the present invention, the connection of the three power terminals 13 and the four gate drive terminals 14 to the corresponding conductive regions may be performed in various manners known to those skilled in the art, such as welding, ultrasonic welding, etc. In a preferred example of the present invention, however, the three power terminals 13, the four gate drive terminals 14 and the corresponding conductive regions are connected by ultrasonic welding in consideration of stability and reliability of the connection.
In this embodiment of the utility model, four gate resistors 15 are mounted on the corresponding conductive areas by means of welding or sintering. Meanwhile, in the circuit topology, the gate resistor 15 contributes to the dynamic current sharing of the two parallel MOS tubes 17.
In the embodiment of the present invention, the plastic package casing 08 is an epoxy plastic package material in consideration of the reliability of the package structure package.
FIG. 7 is an exemplary diagram of a package structure of a multi-topology compatible power semiconductor module according to one embodiment of the utility model; fig. 8 is a schematic diagram of the circuit of fig. 7. In fig. 7 and 8, the package structure may include an insulating board substrate 06, a plastic package, a bonding wire 02, three power terminals 13, four gate driving terminals 14, four gate resistors 15, two diodes 16, and two MOS transistors 17. Specifically, the insulating substrate 06 may include seven conductive regions.
Seven conductive areas are distributed in parallel on the top of the insulating board substrate 06, one end of each of the three power terminals 13 is connected with the middle three conductive areas, and the other end of each of the three power terminals 13 penetrates through the plastic package casing and extends to the outside of the plastic package casing. The four gate drive terminals 14 are respectively connected with the four conductive areas on the two sides, and the other ends of the four gate drive terminals 14 penetrate through the plastic package casing and extend to the outside of the plastic package casing. The two MOS tubes 17 are respectively arranged on a first conductive region and a third conductive region from left to right of the middle three conductive regions, and drain electrodes of the two MOS tubes 17 are respectively connected with the first conductive region and the third conductive region; the source electrode of the MOS tube 17 on the first conductive region is connected with the second conductive regions from left to right of the middle three conductive regions through bonding wires 02, and the source electrode of the MOS tube 17 on the third conductive region is connected with the second conductive region through bonding wires 02; the source of the MOS transistor 17 in the first conductive region is connected to the leftmost conductive region through a bonding wire 02, and the source of the MOS transistor 17 in the third conductive region is connected to the rightmost conductive region through a bonding wire 02. The two diodes 16 are respectively arranged on the first conductive area and the third conductive area, and the cathodes of the two diodes 16 are respectively connected with the first conductive area and the third conductive area; the anode of the diode 16 on the first conductive region is connected to the second conductive region through a bonding wire 02, and the anode of the diode 16 on the third conductive region is connected to the second conductive region through a bonding wire 02. The four gate resistors 15 are grouped pairwise, the two groups of gate resistors 15 are respectively arranged on the two conductive regions on the two sides of the middle three conductive regions and are connected with the corresponding conductive regions, the gate electrode and the diode 16 of the MOS tube 17 on the first conductive region are connected with the two adjacent gate resistors 15 through the bonding wire 02, and the gate electrode and the diode 16 of the MOS tube 17 on the third conductive region are connected with the other two gate resistors 15 through the bonding wire 02.
The MOS tube 17 and the diode 16 are connected in parallel on the same conductive region, and the sources of the two MOS tubes 17 are connected with each other to form an internal common source circuit topology.
On the other hand, the present invention also provides a module structure of a power semiconductor module compatible with multiple topologies, as shown in fig. 9. Specifically, in fig. 9, the module structure includes a liquid-cooled heat sink 10, the package structure as described above, and a laminated power bus bar 11.
The plurality of packaging structures are distributed in parallel along the side wall of the liquid cooling radiator 10, and the laminated power busbar 11 is sleeved on a conductive assembly of the packaging structures and used for connecting the direct-current bus capacitor and the power semiconductor chips 01 in the plurality of packaging structures to form a conversion circuit.
The shapes of the plurality of packaging structures are consistent, the packaging structures are arranged on the side wall of the liquid cooling radiator 10 in parallel, and the plurality of packaging structures are radiated through the liquid cooling radiator 10 so as to ensure that the power semiconductor chips 01 in the plurality of packaging structures can reliably and stably operate. The laminated power busbar 11 is adopted to connect the conductive components of the multiple packaging structures, so that a new circuit topology is formed, the packaging structures needing to be connected can be selected according to the actual required conversion circuit, and then the power modules with multiple topologies can be combined, so that the packaging structure is more flexible and stable.
In this embodiment of the present invention, as shown in fig. 9, the liquid-cooled heat sink 10 may further include a limiting groove 12. Specifically, the limiting groove 12 is opened on the sidewall of the liquid cooling heat sink 10 for installing a plurality of package structures.
The packaging structure is arranged in the limiting groove 12, so that the packaging structure is more stably connected with the liquid cooling radiator 10, and the heat dissipation area of the packaging structure can be enlarged.
In this embodiment of the present invention, in order to improve the heat dissipation efficiency of the package structure, one side of the heat dissipation plate 05 of the package structure is bonded to the side wall of the liquid-cooled heat sink 10.
Fig. 6 is an exemplary diagram of a module structure of a multi-topology compatible power semiconductor module according to an embodiment of the present invention. In fig. 6, three package structures are power semiconductor modules of three internal half-bridge topologies, the three power semiconductor modules are mounted inside the limiting groove 12, thermal interface materials are coated between the three power semiconductor modules, and power terminals and signal terminals of the three power semiconductor modules are connected with other parts of a loop where a system is located through a power circuit board or a copper bar to form a three-phase half-bridge power module.
Fig. 9 is an exemplary diagram of a module structure of a multi-topology compatible power semiconductor module according to an embodiment of the present invention; FIG. 10 is a top view of FIG. 8; fig. 11 is a schematic diagram of the circuit of fig. 9. In fig. 9, 10 and 11, three internal half-bridge topology package structures are installed inside the limiting groove 12, three internal common source topology package structures are installed on one side of the liquid cooling radiator 10 opposite to the limiting groove 12, and the laminated power busbar 11 is sleeved at the terminals of the six package structures to form the three-phase T-type three-level power module.
According to the technical scheme, the packaging structure and the module structure of the power semiconductor module compatible with multiple topologies, provided by the utility model, have the advantages that the power semiconductor chips 01 are respectively arranged on the multiple areas and are connected with the circuit loop through the conductive assembly so as to realize high integration of the power semiconductor module, so that the power semiconductor module is compatible with multiple forms of power electronic circuit topologies, and the universality is high; meanwhile, the packaging structure adopts the insulating substrate 06, which is beneficial to reducing the system thermal resistance.
The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, however, the present invention is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are within the protective scope of the present invention. It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and the utility model is not described in any way for the possible combinations in order to avoid unnecessary repetition.
In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as the disclosure of the present invention as long as it does not depart from the spirit of the present invention.
Claims (10)
1. A multi-topology compatible power semiconductor module package, comprising:
an insulating substrate (06), the insulating substrate (06) comprising:
an insulating plate (04);
a conductive plate (03) disposed at one side of the insulating plate (04), the conductive plate (03) having a plurality of notches etched therein to divide the conductive plate (03) into a plurality of conductive regions;
a heat dissipation plate (05) disposed on the other side of the insulation plate (04);
the power semiconductor chips (01) are respectively arranged on the conductive areas, and one electrode of each power semiconductor chip (01) is electrically connected with the conductive area;
the conductive component is connected with the other electrode of the power semiconductor chip (01) so as to connect the power semiconductor chip (01) into a circuit loop where the packaging structure is located;
and the plastic package shell (08) is sleeved on the insulating substrate (06) and the outer sides of the plurality of power semiconductor chips (01), and one side of the heat dissipation plate (05), which is far away from the insulating plate (04), extends out of the plastic package shell (08).
2. The package structure according to claim 1, wherein the conductive component comprises a plurality of bonding wires (02), one end of each bonding wire (02) is connected with the other electrode of the corresponding power semiconductor chip (01), and the other end of each bonding wire (02) is connected with the next adjacent conductive region.
3. The package structure according to claim 2, characterized in that the conductive assembly further comprises a first lead frame (07), one end of the first lead frame (07) is connected with the last conductive region, and the other end of the first lead frame (07) passes through the plastic package housing (08) and extends to the outside of the plastic package housing (08).
4. The package structure according to claim 3, wherein the first lead frame (07) is provided in plurality, and the other ends of the first lead frames (07) are located on the same side of the plastic package housing (08).
5. The package structure according to claim 1, wherein the conductive assembly comprises a plurality of second lead frames (09), one end of each second lead frame (09) is connected with the other electrode of the corresponding power semiconductor chip (01), the other end of each second lead frame (09) is connected with the next adjacent conductive region, and the other end of the last second lead frame (09) penetrates through the plastic package casing (08) and extends to the outside of the plastic package casing (08).
6. The package structure according to claim 1, characterized in that the insulating substrate (06) is an aluminum oxide, DBC, substrate.
7. The package structure according to claim 1, wherein a plurality of the power semiconductor chips (01) are soldered/sintered to a conductive plate (03).
8. A multi-topology compatible power semiconductor module architecture, comprising:
a liquid-cooled radiator (10);
-a plurality of packages according to any of claims 1 to 7, said packages being arranged side by side along the side walls of said liquid-cooled heat sink (10);
and the laminated power busbar (11) is sleeved on the conductive components of the packaging structures and is used for connecting the direct-current bus capacitor with the power semiconductor chips (01) in the packaging structures to form a conversion circuit.
9. The module structure according to claim 8, wherein the side wall of the liquid-cooled heat sink (10) is formed with a limiting groove (12), and the limiting groove (12) is used for mounting a plurality of the package structures.
10. Module structure according to claim 8, characterized in that one side of the heat sink (05) of the package structure is attached to a side wall of the liquid-cooled heat sink (10).
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