CN216748450U - Time-to-digital conversion device - Google Patents

Abstract

The utility model provides a time-to-digital conversion device. The clock generation circuit generates n clock signals having different phases. After a preset period of time elapses since the clock generation circuit starts generating the n clock signals, the time-to-digital converter starts counting rising edges or falling edges of the n clock signals to generate digital signals for the signal processing circuit.

Description

time-to-digital converter

technical field

The utility model relates to a conversion device, in particular to a time-to-digital conversion device.

Background technique

With the development of integrated circuits, the sensing information obtained by the sensor can be converted into the form of digital codes, which can be used more widely. Among them, for the time measurement system, the time-to-digital converter can represent the sensing information by the time width, and count the time width through the oscillator, so as to convert the sensing information into a digital output.

In the prior art, the time-to-digital converter generally converts time information into digital signals by counting the clock signal provided by the oscillator. However, since the pulse width of the clock signal provided at the initial stage of the oscillator is not stable, so the So that the digital signal can not correctly reflect the time information.

Utility model content

The utility model provides a time-to-digital conversion device, which can ensure that the digital signal output by the time-to-digital conversion device provides correct time information.

The time-to-digital conversion device of the utility model comprises a clock generating circuit and a time-to-digital converter. The clock generating circuit generates n clock signals with different phases, where n is a positive integer. The time-to-digital converter is coupled to the clock generation circuit, and starts to count the rising or falling edges of the n clock signals to generate digital signals after a predetermined period of time after the clock generation circuit starts to generate the n clock signals.

Based on the above, the time-to-digital converter of the embodiment of the present invention can start to count the rising edge or the falling edge of the clock signal to generate a digital signal after a predetermined period of time has elapsed since the clock generating circuit started to generate the clock signal. Waiting for the clock signal output by the clock generating circuit to be stable, then counting the rising edge or the falling edge can ensure that the correctness of the digital signal generated by the time-to-digital conversion device is not affected by the unstable clock signal of the clock generating circuit.

In order to make the above-mentioned features and advantages of the present utility model more obvious and easy to understand, the following embodiments are given and described in detail in conjunction with the accompanying drawings as follows.

Description of drawings

FIG. 1 is a schematic block diagram of a time-to-digital conversion device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating an operation sequence of a time-to-digital conversion device according to an embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating an operation sequence of a time-to-digital conversion device according to another embodiment of the present invention.

FIG. 4 is a flowchart of a time-to-digital conversion method of the time-to-digital conversion device according to an embodiment of the present invention.

5 is a flowchart of a time-to-digital conversion method of a time-to-digital conversion device according to another embodiment of the present invention.

Detailed ways

In order to make the content of the present invention easier to understand, the following specific embodiments are taken as examples by which the present invention can indeed be implemented. In addition, where possible, components/components using the same reference numerals in the drawings and embodiments represent the same or similar parts.

Please refer to FIG. 1 below. FIG. 1 is a schematic block diagram of a time-to-digital conversion device according to an embodiment of the present invention. The time-to-digital conversion device includes a clock generation circuit 102 and a time-to-digital converter 104 . The clock generation circuit 102 is coupled to the time-to-digital converter 104 . The clock generating circuit 102 can generate n clock signals CK0 ˜CKn-1 with different phases, where n is a positive integer. The clock generating circuit 102 can be implemented by, for example, a ring oscillator, but not limited thereto. The time-to-digital converter 104 can start to count the rising or falling edges of the clock signals CK0 ˜CKn-1 after the clock generation circuit 102 starts to generate the clock signals CK0 ˜CKn-1 after a predetermined period of time, so as to generate the digital signal D1 . Waiting for the clock signals CK0 to CKn-1 output by the clock generation circuit 102 to be stable in this way, and then counting the rising or falling edges of the clock signals CK0 to CKn-1, can ensure the correctness of the digital signal D1 generated by the time-to-digital conversion device. It is not affected by the instability of the clock signals CK0 to CKn- 1 of the clock generation circuit 102 .

For example, as shown in FIG. 2, the clock generation circuit 102 is enabled by the received enable signal EN1, and starts to generate the clock signals CK0-CK3. The time-to-digital converter 104 can start counting the rising edges of the clock signals CK0 - CK3 according to the received enable signal EN2 after a predetermined period of time T1 after the clock generation circuit 102 starts to generate the clock signal. As shown in FIG. 2 , at the initial stage when the clock generation circuit 102 generates the clock signals CK0 ˜ CK3 , the clock signals CK0 ˜ CK3 are not yet stable and have larger pulse widths, and after the preset time T1 elapses, the clock signals CK0 ˜ CK3 Since it becomes stable and has a small and fixed pulse width, counting the clock signals CK0 to CK3 at this time can more accurately reflect the time information.

The time-to-digital converter 104 may, for example, determine the signal value of the output digital signal D1 according to the received stop signal SP1. For example, in FIG. 2 , the stop signal SP1 is a pulse signal, and the time-to-digital converter 104 can determine the signal value of the output digital signal D1 according to the rising edge of the stop signal SP1 (in the embodiment of FIG. 2 , the rising edge of the stop signal SP1 The corresponding signal value is 8).

It should be noted that the number of clock signals generated by the clock generation circuit 102 is not limited to the embodiment of FIG. 2 , and in other embodiments, the clock generation circuit 102 may generate more or less clock signals. In addition, the preset time T1 can be determined, for example, according to the time required for the change of the pulse width of the clock signal to be less than the preset value within a period of observation time, that is, the time required for the clock signal generated by the clock generation circuit 102 to stabilize Decide. In other embodiments, the time-to-digital converter 104 can also count according to the falling edges of the clock signals CK0-CK3 instead of the rising edges. Similarly, the time-to-digital converter 104 can also count according to the falling edge of the stop signal SP1. Determines the signal value of the output digital signal D1.

The enable signals EN1 , EN2 and the stop signal SP1 may be provided by, for example, a control circuit (not shown) coupled to the clock generation circuit 102 and the time-to-digital converter 104 . In other embodiments, the control circuit can also detect whether the change of the pulse width of the clock signal generated by the clock generating circuit 102 is smaller than a preset value during the recent observation period, and determine whether the pulse width of the clock signal is When the width change is smaller than the preset value, the enable signal EN2 is generated to enable the time-to-digital converter 104 to start counting the rising or falling edge of the stop signal SP1 to ensure that the time-to-digital converter 104 can generate the correct digital signal D1 .

The time-to-digital conversion device may, for example, be applied to a distance sensing device, such as a time-of-flight distance sensor or an ultrasonic sensor, but is not limited thereto. For example, the time point at which the time-to-digital converter 104 starts to count the rising edge of the stop signal SP1 according to the enable signal EN2 may be the time point when the time-of-flight distance sensor emits a light beam or the time point when the ultrasonic sensor emits a sound wave, and the stop signal SP1 is generated. The time point of the rising edge can be, for example, the time point when the time-of-flight distance sensor receives the reflected light beam or the time point when the ultrasonic sensor receives the reflected sound wave. In this way, accurate time information can be obtained through the digital signal D1 generated by the time-to-digital conversion device. The calculated distance sensing result is correct.

In addition, in some embodiments, the signal value of the digital signal D1 can also be determined by, for example, two count values. For example, as shown in FIG. 3 , different from the embodiment of FIG. 2 , in the embodiment of FIG. 3 , the time-to-digital converter 104 can determine the first count value according to the rising edge of the received start signal ST1 (eg, Count value 2 in FIG. 3 ), and determine a second count value (eg, count value 8 in FIG. 3 ) according to the rising edge of the received stop signal SP1 , and generate a digital signal D1 according to the first count value and the second count value. For example, the difference (6) obtained by subtracting the first count value (2) from the second count value (8) can be used as the digital signal D1, which represents the rising edge from the rising edge of the start signal ST1 to the rising edge of the stop signal SP1 During the occurrence period, the time for 6 cumulative count values has elapsed.

The digital signal D1 can be transmitted to the signal processing circuit of the subsequent stage for signal application processing. For example, when the time-to-digital conversion device is applied to a distance sensing device, such as a time-of-flight distance sensor or an ultrasonic sensor, the signal processing circuit may perform application processing related to distance estimation. The time when the rising edge of the start signal ST1 occurs can be the time when the time-of-flight distance sensor emits a light beam or the time when the ultrasonic sensor emits a sound wave, and the time when the stop signal SP1 generates a rising edge can be, for example, when the time-of-flight distance sensor receives a reflection. The point in time at which the beam of light or the ultrasonic sensor receives the reflected sound wave. In addition, the time-to-digital converter 104 can also count according to the falling edges of the counting clock signals CK0-CK3, and determine the first count value and the second count value according to the falling edges of the start signal ST1 and the stop signal SP1.

FIG. 4 is a flowchart of a time-to-digital conversion method of the time-to-digital conversion device according to an embodiment of the present invention. It can be known from the above embodiments that the time-to-digital conversion method of the time-to-digital conversion device may include at least the following steps. First, the clock generation circuit is enabled to generate n clock signals (step S402 ), where n is a positive integer. For example, a first enable signal can be provided to the clock generation circuit to enable the clock generation circuit to generate n clock signals. Then, after a predetermined period of time has elapsed since the clock generation circuit starts to generate n clock signals, it starts to count the rising edges or falling edges of n clock signals to generate digital signals (step S404 ), for example, according to the second enable signal After a preset time elapses since the clock generating circuit starts to generate n clock signals, it starts counting the rising edges or falling edges of the n clock signals to generate digital signals. The preset time may be determined, for example, according to the time required for the variation of the pulse width of the n clock signals to be less than the preset value within a period of observation time. Waiting for the clock signal output by the clock generating circuit to be stable, then counting the rising edge or the falling edge can ensure that the correctness of the digital signal generated by the time-to-digital conversion device is not affected by the unstable clock signal of the clock generating circuit.

5 is a flowchart of a time-to-digital conversion method of a time-to-digital conversion device according to another embodiment of the present invention. Compared with the embodiment of FIG. 4 , the time-to-digital conversion method of this embodiment generates a digital signal representing time information according to two count values. As shown in FIG. 5 , the corresponding first count value and the second count value can be determined according to the times of the start signal and the stop signal received in sequence (step S502 ), and then according to the first count value and the second count value The digital signal is generated (step S504 ). For example, the digital signal can be generated according to the difference between the first count value and the second count value. The start signal and the stop signal can be, for example, pulse signals, and the first count value and the second count value can be determined according to the count values corresponding to the generation time of the rising edge or the falling edge of the start signal and the stop signal.

To sum up, the time-to-digital converter of the embodiment of the present invention can start to count the rising edge or the falling edge of the clock signal to generate a digital signal after a predetermined period of time has elapsed since the clock generating circuit started to generate the clock signal. Waiting for the clock signal output by the clock generating circuit to be stable, then counting the rising edge or the falling edge can ensure that the correctness of the digital signal generated by the time-to-digital conversion device is not affected by the unstable clock signal of the clock generating circuit.

Although the present utility model has been disclosed above with examples, it is not intended to limit the present utility model. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present utility model. Therefore, the protection scope of the present invention should be determined by the claims.

Claims (6)

1. A time-to-digital conversion apparatus, comprising:

a clock generation circuit generating n clock signals having different phases, wherein n is a positive integer; and

the time-to-digital converter is coupled to the clock generation circuit, and starts to count rising edges or falling edges of the n clock signals after a preset time period elapses since the clock generation circuit starts to generate the n clock signals, so as to generate digital signals.

2. The time-to-digital converter of claim 1, wherein the time-to-digital converter determines a first count value and a second count value according to a start signal and a stop signal, and generates the digital signal according to the first count value and the second count value.

3. The time-to-digital converter of claim 2, wherein the time-to-digital converter generates the digital signal according to a difference between the first count value and the second count value.

4. The time-to-digital converter of claim 2, wherein the start signal and the stop signal are pulse signals, and the time-to-digital converter determines the corresponding first count value and the second count value according to generation times of rising edges or falling edges of the start signal and the stop signal.

5. The time-to-digital conversion apparatus according to claim 1, wherein the predetermined time is determined according to a time required for the pulse width variation of the n clock signals to be less than a predetermined value within an observation time.

6. The time-to-digital converter of claim 1, wherein the clock generating circuit generates the n clock signals according to a first enable signal, and the time-to-digital converter starts counting rising edges or falling edges of the n clock signals after the preset time elapses since the clock generating circuit starts generating the n clock signals according to a second enable signal to generate the digital signals.

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