CN216671616U - Conductive circuit structure of chip package - Google Patents

Abstract

A conductive circuit structure of chip package, wherein the dielectric layer of the conductive circuit structure has only two dielectric layers of a first dielectric layer and a second dielectric layer at most, which is more than the existing conductive layer. The dielectric layer of the connecting line structure is less, so that the connecting line structure can effectively improve the problems of thick thickness and complicated manufacturing process of the existing connecting line structure, so as to conform to the development trend of the modern connecting line structure becoming thinner and thinner. , which is beneficial to reduce the cost of the manufacturing end. In addition, the conductivity of the plurality of conductive lines in the conductive line structure will also be improved, thereby increasing the product performance.

Description

Conductive circuit structure of chip package

technical field

The utility model relates to a conductive circuit structure, in particular to a conductive circuit structure of chip packaging.

Background technique

In the field of semiconductor chip packaging structure technology, there are various prior technologies such as Taiwan Invention Patent No. 434848 "Semiconductor Chip Device and Its Packaging Method" and its four additional patent cases including: Announcement No. 466715 (Additional 1), Announcement No. 495933 (Addition 2), Announcement No. 466716 (Addition 3), Announcement No. 503534 (Addition 4), or I381503, and US Patent Nos. US 6,239,488, US 5,990,546, US 6,143,991, US 6,075,712, US 6, 114,754, or US2004/0232543 and other patents. The recently developed and used semiconductor chip package structure belongs to a chip scale package type, and a variety of different processes and structures have been derived. This chip scale package type (chip scale package type) Although the process and structure of TAB technology can solve the problem of larger package size caused by TAB technology.

However, in view of the shortcomings of the method of forming the conductive line structure in the technical features of the above-mentioned invention patent I381503, there are still three layers of dielectric layers used in the technical features of the patent I381503, which does not conform to the more modern conductive line structure. The development trend of thinner type, in addition, the process required for the three-layer dielectric junction is also more complicated, which has the problem of increasing the cost of the manufacturing end.

It can be seen from the above that a conductive line structure capable of solving the chip package with thick conductive line structure and complicated manufacturing process in the prior art is urgently expected in the current related industries.

Utility model content

The main purpose of the present invention is to provide a conductive circuit structure for chip packaging, wherein the dielectric layer of the conductive circuit structure has only a first dielectric layer and a second dielectric layer at most, which is relatively Some conductive line structures have less dielectric layers, so that the conductive line structures can effectively improve the problems of thicker thickness and complicated manufacturing process of the existing conductive line structures.

In order to achieve the above-mentioned purpose, the present invention provides a conductive circuit structure of a chip package. The conductive circuit structure is mounted on a substrate in a plurality of numbers, and the conductive circuit structure includes a chip and a plurality of first protective layers. , a plurality of first dielectric layers, a plurality of conductive lines and a plurality of second protective layers; wherein the chip has a surface, and a plurality of bonding pads are arranged on the surface; wherein each of the first protective layers respectively covers The ground is disposed on the surface of the chip, and each of the first protective layers covers each of the bonding pads of the chip, wherein each of the first protective layers is electrically connected to each of the bonding pads of the wafer; wherein each of the first protective layers is A dielectric layer is overlaid on the surface of the chip, and each of the first dielectric layers is formed with at least one first groove, and each of the first grooves allows each of the bonding pads of the chip to connect to the outside Electrical connection; wherein each of the conductive lines is covered on the surface of the chip and each of the first protective layers, and a part of each of the conductive lines is arranged in each of the first grooves; wherein each of the second The protective layers are respectively disposed on the surface of each of the conductive lines and the surface of each of the first dielectric layers correspondingly, and each of the second protective layers covers each of the pads of the chip, wherein each of the second protective layers The layer is electrically connected to each of the conductive lines, and each of the second protective layers is electrically connected to each of the pads of the wafer through each of the conductive lines; it is beneficial to reduce the cost of the manufacturing end. In addition, the conductive lines The conductivity of each of the conductive lines in the structure is also improved, thereby increasing product performance.

In another preferred embodiment of the present invention, each of the first dielectric layers is formed by a spin coating process.

In another preferred embodiment of the present invention, each of the first grooves is filled with metal material selected from silver paste printing (silver paste printing), sputtering (sputter), chemical vapor deposition (Chemical Vapor Deposition, CVD). , one of sputtering and plating, or chemical vapor deposition and plating.

In order to achieve the above object, the present invention further provides a conductive circuit structure of a chip package. The conductive circuit structure is installed and combined on a substrate in a plurality of numbers, and the conductive circuit structure includes a chip, a plurality of first protection layers, a plurality of first dielectric layers, a plurality of conductive lines, a plurality of second protective layers and a plurality of second dielectric layers; wherein the chip has a surface on which a plurality of bonding pads are arranged; Each of the first protective layers is correspondingly disposed on the surface of the chip, and each of the first protective layers covers each of the pads of the chip, wherein each of the first protective layers and each of the The pads are electrically connected; wherein each of the first dielectric layers is covered on the surface of the chip, and each of the first dielectric layers is formed with at least one first groove, and each of the first grooves Each of the bonding pads of the chip can be electrically connected to the outside; wherein each of the conductive lines is covered on the surface of the chip and each of the first protective layers, and part of each of the conductive lines is provided on each of the first protective layers. On the ring sidewall of a dielectric layer; wherein each of the second protective layers is correspondingly disposed on the surface of each of the conductive lines, and each of the second protective layers covers each of the pads of the chip, wherein Each of the second protective layers is electrically connected to each of the conductive lines, and each of the second protective layers is electrically connected to each of the pads of the wafer through each of the conductive lines; wherein each of the second dielectrics The layers are covered on the surface of each of the first dielectric layers, and at least one second groove is formed on each of the second dielectric layers, and each of the second grooves is used for each of the conductive lines to be electrically connected to the outside. The second dielectric layer is not connected to or in contact with the second protective layer; it is beneficial to reduce the cost of the manufacturing end, and in addition, the conductivity of each of the conductive lines in the conductive line structure will also be enhance and increase product performance.

In another preferred embodiment of the present invention, each of the first dielectric layers and each of the second dielectric layers are formed by a spin coating process.

In another preferred embodiment of the present invention, each of the first grooves and each of the second grooves is filled with metal material selected from silver paste printing, sputtering, chemical vapor phase One of deposition (Chemical Vapor Deposition, CVD), sputtering and electroplating (plating), or chemical vapor deposition and electroplating.

In order to achieve the above object, the present invention further provides a conductive circuit structure of a chip package. The conductive circuit structure is installed and combined on a substrate in a plurality of numbers, and the conductive circuit structure includes a chip, a plurality of first protection layers, a plurality of first dielectric layers, a plurality of conductive lines, a plurality of second protective layers and a plurality of second dielectric layers; wherein the chip has a surface on which a plurality of bonding pads are arranged; Each of the first protective layers is correspondingly disposed on the surface of the chip, and each of the first protective layers covers each of the pads of the chip, wherein each of the first protective layers and each of the The pads are electrically connected; wherein each of the first dielectric layers is covered on the surface of the chip, and each of the first dielectric layers is formed with at least one first groove, and each of the first grooves Each of the bonding pads of the chip can be electrically connected to the outside; wherein each of the conductive lines is covered on the surface of the chip and each of the first protective layers, and part of each of the conductive lines is provided on each of the first protective layers. in a groove; wherein each of the second protective layers is correspondingly disposed on the surface of each of the conductive lines, and each of the second protective layers covers each of the pads of the chip, wherein each of the second protective layers is electrically connected to each of the conductive lines, and each of the second protective layers is electrically connected to each of the pads of the wafer through each of the conductive lines; wherein each of the second dielectric layers covers each of the At least one second groove is formed on the surface of the first dielectric layer and each of the second dielectric layers, and each of the second grooves is exposed to the outside of each of the second protective layers, so that each of the The second protective layer can be electrically connected to the outside; so that each of the second protective layers can be electrically connected to the outside, which is beneficial to reduce the cost of the manufacturing end. In addition, the conductivity of each of the conductive lines in the conductive line structure will also be enhance and increase product performance.

In another preferred embodiment of the present invention, each of the first dielectric layers and each of the second dielectric layers are formed by a spin coating process.

In another preferred embodiment of the present invention, each of the first grooves and each of the second grooves is filled with metal material selected from silver paste printing, sputtering, chemical vapor phase One of deposition (Chemical Vapor Deposition, CVD), sputtering and electroplating (plating), or chemical vapor deposition and electroplating.

Description of drawings

FIG. 1 is a schematic cross-sectional view of the third embodiment of the present invention and step S6 of the third embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of step S1 of the third embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of step S2 of the third embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of step S3 of the third embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of step S4 of the third embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of step S5 in the third embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of a third embodiment of the present invention, where a plurality of conductive line structures are installed and combined on a substrate.

8 is a schematic cross-sectional view of the second embodiment of the present invention and step S6 of the second embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view of step S1 of the second embodiment of the present invention.

10 is a schematic cross-sectional view of step S2 of the second embodiment of the present invention.

11 is a schematic cross-sectional view of step S3 of the second embodiment of the present invention.

12 is a schematic cross-sectional view of step S4 of the second embodiment of the present invention.

13 is a schematic cross-sectional view of step S5 of the second embodiment of the present invention.

FIG. 14 is a schematic cross-sectional view of a second embodiment of the present invention where the conductive line structures are installed and combined on a substrate in a plurality of numbers.

15 is a schematic cross-sectional view of the first embodiment of the present invention and step S5 of the first embodiment of the present invention.

16 is a schematic cross-sectional view of step S1 of the first embodiment of the present invention.

17 is a schematic cross-sectional view of step S2 of the first embodiment of the present invention.

FIG. 18 is a schematic cross-sectional view of step S3 of the first embodiment of the present invention.

19 is a schematic cross-sectional view of step S4 of the first embodiment of the present invention.

FIG. 20 is a schematic cross-sectional view of the first embodiment of the present invention where the conductive line structures are installed and combined on a substrate in a plurality of numbers.

List of reference signs: 1-conducting line structure; 1a-conducting line structure; 1b-conducting line structure; 10-wafer; 11-surface; 12-pad; 20-first protective layer; 30-first 31-first groove; 40-conducting line; 50-second protective layer; 60-second dielectric layer; 61-second groove; 2-substrate.

Detailed ways

The structure and technical features of the present invention will be described in detail below in conjunction with the drawings. Each drawing is only used to illustrate the structural relationship and related functions of the present invention. Therefore, the dimensions of each element in each drawing are not based on the actual scale. The drawings are not intended to limit the present invention.

Referring to FIGS. 1 , 8 and 15 , the present invention provides a conductive circuit structure 1 , 1 a , 1 b for a chip package, and the conductive circuit structure 1 , 1 a , 1 b can effectively improve the thickness of the existing conductive circuit structure. And the problem of complicated manufacturing process, in order to comply with the development trend of thinner and thinner structure of modern conductor lines, which is beneficial to reduce the cost of the manufacturing end. According to the difference between the steps of the manufacturing method in the conductive circuit structures 1, 1a, 1b of the chip package of the present invention, the present invention provides the following first embodiment, second embodiment and third embodiment:

The embodiment shown in FIGS. 15 to 20 is the first embodiment of the conductive line structure 1a of the present invention. The conductive line structure 1a is installed and combined on a substrate 2 in a plurality of numbers. As shown in FIG. 20 , the conductive line structure 1a The wiring structure 1 a includes a chip 10 , a plurality of first protective layers 20 , a plurality of first dielectric layers 30 , a plurality of conductive lines 40 and a plurality of second protective layers 50 .

The wafer 1 has a surface 11 as shown in FIG. 15 , and a plurality of bonding pads 12 are disposed on the surface 11 .

Each of the first protective layers 20 is correspondingly disposed on the surface 11 of the chip 10 , as shown in FIG. 15 , and each of the first protective layers 20 covers each of the bonding pads 12 of the chip 10 ; A protective layer 20 is electrically connected to each of the bonding pads 12 of the wafer 10 .

Each of the first dielectric layers 30 is overlaid on the surface 11 of the wafer 10 as shown in FIG. 15 , and at least one first groove 31 is formed on each of the first dielectric layers 30 . A groove 31 is provided for each of the bonding pads 12 of the chip 10 to be electrically connected to the outside; wherein each of the first dielectric layers 30 is formed by a spin coating process, but not limited; wherein each of the first dielectric layers 30 is not limited The method of filling the groove 31 with metal is selected from silver paste printing, sputtering, chemical vapor deposition (CVD), sputtering and plating, or chemical vapor deposition and CVD. One of but not limited to electroplating.

Each of the conductive lines 40 is covered on the surface 11 of the chip 10 and each of the first protective layers 20 as shown in FIG. 15 , and a part of each of the conductive lines 40 is disposed in each of the first grooves 31 .

Each of the second protective layers 50 is correspondingly disposed on the surface of each of the conductive lines 40 and the surface of each of the first dielectric layers 30 , as shown in FIG. 15 , and each of the second protective layers 50 covers the Each of the bonding pads 12 of the chip 10 ; wherein each of the second protective layers 50 is electrically connected to each of the conductive lines 40 , and each of the second protective layers 50 is connected to each of the The pads 12 are electrically connected.

Wherein, the manufacturing method of the conductive circuit structure 1a includes the following steps:

Step S1 : providing a wafer 10 As shown in FIG. 16 , the wafer 10 has a surface 11 , and a plurality of bonding pads 12 are provided on the surface 11 .

Step S2: Disposing a plurality of first dielectric layers 30 correspondingly on the surface 11 of the wafer 10. As shown in FIG. 17, at least one first groove 31 is formed on each of the first dielectric layers 30. , each of the first grooves 31 exposes each of the bonding pads 12 of the chip 10 to the outside, so that each of the bonding pads 12 of the chip 10 can be electrically connected to the outside. The first embodiment of the present invention is provided with only one layer of dielectric layer, which is different from the existing conductive line structure with three layers of dielectric layers, which is beneficial to reduce the thickness and reduce the manufacturing process. The conductivity of each of the conductive lines 40 in the structure 1a is also improved, thereby increasing product performance.

Step S3 : providing a plurality of first protective layers 20 correspondingly covering the surface 11 of the chip 10 as shown in FIG. 18 , and each of the first protective layers 20 covers each of the bonding pads 12 of the chip 10 ; The first protective layer 20 is electrically connected to each of the bonding pads 12 of the wafer 10 .

Step S4 : setting a plurality of conductive lines 40 correspondingly covering the surface 11 of the chip 10 and each of the first protective layers 20 as shown in FIG. 19 , and each of the conductive lines 40 is filled with each of the first interposers Each of the first grooves 31 of the dielectric layer 30 ; a part of each of the conductive lines 40 is arranged in each of the first grooves 31 .

Step S5 : disposing a plurality of second protective layers 50 correspondingly on the surface of each of the conductive lines 40 and the surface of each of the first dielectric layers 30 , as shown in FIG. 15 , and each of the second protective layers 50 Each of the bonding pads 12 of the chip 10 is covered; wherein each of the second protective layers 50 is electrically connected to each of the conductive lines 40 , and each of the second protective layers 50 is connected to the wafer 10 through each of the conductive lines 40 Each of the pads 12 is electrically connected.

The embodiment shown in FIGS. 8 to 14 is the second embodiment of the conductive line structure 1b of the present invention. The conductive line structure 1b is installed and combined on a substrate 2 in multiple numbers, as shown in FIG. 14 , The conductive line structure 1b includes a chip 10, a plurality of first protective layers 20, a plurality of first dielectric layers 30, a plurality of conductive lines 40, a plurality of second protective layers 50 and a plurality of second dielectric layers Substance layer 60.

The wafer 10 has a surface 11 as shown in FIG. 8 , and a plurality of bonding pads 12 are disposed on the surface 11 .

Each of the first protective layers 20 is correspondingly disposed on the surface 11 of the chip 10 , as shown in FIG. 8 , and each of the first protective layers 20 covers each of the bonding pads 12 of the chip 10 ; A protective layer 20 is electrically connected to each of the bonding pads 12 of the wafer 10 .

Each of the first dielectric layers 30 is overlaid on the surface 11 of the wafer 10 as shown in FIG. 8 , and at least one first groove 31 is formed on each of the first dielectric layers 30 . A groove 31 is provided for each of the bonding pads 12 of the chip 10 to be electrically connected to the outside; wherein each of the first dielectric layers 30 is formed by a spin coating process, but not limited; wherein each of the first dielectric layers 30 is not limited The method of filling the groove 31 with metal is selected from silver paste printing, sputtering, chemical vapor deposition (CVD), sputtering and plating, or chemical vapor deposition and CVD. One of but not limited to electroplating.

Each of the conductive lines 40 is covered on the surface 11 of the chip 10 and each of the first protective layers 20 as shown in FIG. 8 , and a part of each of the conductive lines 40 is provided on each of the first dielectric layers 30 on the ring sidewall.

Each of the second protective layers 50 is correspondingly disposed on the surface of each of the conductive lines 40 , as shown in FIG. 8 , and each of the second protective layers 50 covers each of the pads 12 of the chip 10 ; wherein each of the The second protective layer 50 is electrically connected to each of the conductive lines 40 , and each of the second protective layers 50 is electrically connected to each of the bonding pads 12 of the wafer 10 through each of the conductive lines 40 .

Each of the second dielectric layers 60 is covered on the surface of each of the first dielectric layers 30 as shown in FIG. 8 , and at least one second groove 61 is formed on each of the second dielectric layers 60 , each of the second grooves 61 is used for each of the conductive lines 40 to be electrically connected to the outside; each of the second dielectric layers 60 is not connected to or in contact with each of the second protective layers 50; wherein each of the second dielectric layers The dielectric layer 60 is formed by a process of spin coating, but is not limited; wherein each of the second grooves 61 is filled with metal materials selected from silver paste printing, sputtering, One of but not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD), sputtering and plating, or chemical vapor deposition and plating.

Wherein, the manufacturing method of the conductive line structure 1b includes the following steps:

Step S1 : providing a wafer 10 As shown in FIG. 9 , the wafer 10 has a surface 11 , and a plurality of bonding pads 12 are disposed on the surface 11 .

Step S2: Disposing a plurality of first dielectric layers 30 correspondingly covering the surface 11 of the wafer 10 As shown in FIG. 10 , at least one first groove 31 is formed on each of the first dielectric layers 30 , each of the first grooves 31 exposes each of the bonding pads 12 of the chip 10 to the outside, so that each of the bonding pads 12 of the chip 10 can be electrically connected to the outside.

Step S3 : providing a plurality of first protective layers 20 correspondingly covering the surface 11 of the chip 10 as shown in FIG. 11 , and each of the first protective layers 20 covers each of the bonding pads 12 of the chip 10 ; The first protective layer 20 is electrically connected to each of the bonding pads 12 of the wafer 10 ; wherein each of the first protective layers 20 is located in each of the first grooves 31 .

Step S4: Disposing a plurality of second dielectric layers 60 correspondingly on the surface of each of the first dielectric layers 30. As shown in FIG. 12, at least one first dielectric layer 60 is formed on each of the second dielectric layers 60. Two grooves 61 , each of the second grooves 61 is for each of the first protective layers 20 to be electrically connected to the outside. The second embodiment of the present invention is only provided with two layers of dielectric layers, which is different from the three layers of dielectric layers provided in the existing conductive wiring structure, which is beneficial to reduce the thickness and process. The conductivity of each of the conductive lines 40 in the circuit structure 1b is also improved, thereby increasing product performance.

Step S5: On the surface of each first protective layer 20, each of the first grooves 31 and each of the second grooves 61 are correspondingly covered with a plurality of conductive lines 40 as shown in FIG. 13, and each The conductive lines 40 are filled in each of the first grooves 31 and each of the second grooves 61 ; some of the conductive lines 40 are arranged in each of the first grooves 31 and each of the second grooves within 61.

Step S6: Disposing a plurality of second protective layers 50 correspondingly on the surface of each of the conductive lines 40 as shown in FIG. 8, and each of the second protective layers 50 covers each of the pads 12 of the chip 10; wherein Each of the second protective layers 50 is electrically connected to each of the conductive lines 40 , and each of the second protective layers 50 is electrically connected to each of the bonding pads 12 of the wafer 10 through each of the conductive lines 40 .

The embodiment shown in FIGS. 1 to 7 is the third embodiment of the conductive line structure 1 of the present invention. The conductive line structure 1 is installed and combined on a substrate 2 in a plurality of numbers, as shown in FIG. 7 , The conductive line structure 1 includes a chip 10 , a plurality of first protective layers 20 , a plurality of first dielectric layers 30 , a plurality of conductive lines 40 , a plurality of second protective layers 50 and a plurality of second dielectric layers Substance layer 60.

The wafer 10 has a surface 11 as shown in FIG. 1 , and a plurality of bonding pads 12 are disposed on the surface 11 .

Each of the first protective layers 20 is correspondingly disposed on the surface 11 of the chip 10 , as shown in FIG. 1 , and each of the first protective layers 20 covers each of the bonding pads 12 of the chip 10 ; A protective layer 20 is electrically connected to each of the bonding pads 12 of the wafer 10 .

Each of the first dielectric layers 30 is overlaid on the surface 11 of the wafer 10 as shown in FIG. 1 , and at least one first groove 31 is formed on each of the first dielectric layers 30 . A groove 31 is provided for each of the bonding pads 12 of the chip 10 to be electrically connected to the outside; wherein each of the first dielectric layers 30 is formed by a spin coating process, but not limited; wherein each of the first dielectric layers 30 is not limited The method of filling the groove 31 with metal is selected from silver paste printing, sputtering, chemical vapor deposition (CVD), sputtering and plating, or chemical vapor deposition and CVD. One of but not limited to electroplating.

Each of the conductive lines 40 is covered on the surface 11 of the chip 10 and each of the first protective layers 20 as shown in FIG. 1 , and a part of each of the conductive lines 40 is disposed in each of the first grooves 31 .

Each of the second protective layers 50 is correspondingly disposed on the surface of each of the conductive lines 40 , as shown in FIG. 1 , and each of the second protective layers 50 covers each of the pads 12 of the chip 10 ; wherein each of the The second protective layer 50 is electrically connected to each of the conductive lines 40 , and each of the second protective layers 50 is electrically connected to each of the bonding pads 12 of the wafer 10 through each of the conductive lines 40 .

Each of the second dielectric layers 60 is overlaid on the surface of each of the first dielectric layers 30 as shown in FIG. 1 , and at least one second groove 61 is formed on each of the second dielectric layers 60 , each of the second grooves 61 is for each of the second protective layers 50 to be exposed to the outside, so that each of the second protective layers 50 can be electrically connected to the outside; wherein each of the second dielectric layers 60 is spin-coated ) process but not limited; wherein the manner in which each of the second grooves 61 is filled with metal is selected from silver paste printing (silver paste printing), sputtering (sputter), chemical vapor deposition (Chemical Vapor Deposition, CVD) , one of but not limited to sputtering and plating, or chemical vapor deposition and plating.

Wherein, the manufacturing method of the conductive circuit structure 1 includes the following steps:

Step S1 : providing a wafer 10 As shown in FIG. 2 , the wafer 10 has a surface 11 , and a plurality of bonding pads 12 are disposed on the surface 11 .

Step S2 : providing a plurality of first protective layers 20 correspondingly covering the surface 11 of the chip 10 as shown in FIG. 3 , and each of the first protective layers 20 covers each of the bonding pads 12 of the chip 10 ; The first protective layer 20 is electrically connected to each of the bonding pads 12 of the wafer 10 .

Step S3 : disposing a plurality of first dielectric layers 30 correspondingly on the surface 11 of the wafer 10 as shown in FIG. 4 , and at least one first groove 31 is formed on each of the first dielectric layers 30 At least one first groove 31 is formed thereon, and each of the first grooves 31 exposes the bonding pads 12 of the chip 10 to the outside, so that the bonding pads 12 of the chip 10 can be electrically connected to the outside.

Step S4 : setting a plurality of conductive lines 40 correspondingly covering the surface 11 of the wafer 10 and each of the first protective layers 20 , as shown in FIG. 5 , and each of the conductive lines 40 fills up the Each of the first grooves 31 of the dielectric layer 30 ; a part of each of the conductive lines 40 is arranged in each of the first grooves 31 .

Step S5 : forming a plurality of second protective layers 50 correspondingly covering the surface of each of the conductive lines 40 as shown in FIG. 6 , and each of the second protective layers 50 covers each of the bonding pads 12 of the chip 10 ; wherein Each of the second protective layers 50 is electrically connected to each of the conductive lines 40 , and each of the second protective layers 50 is electrically connected to each of the bonding pads 12 of the wafer 10 through each of the conductive lines 40 .

Step S6 : disposing a plurality of second dielectric layers 60 correspondingly covering each of the second protective layers 50 and each of the first dielectric layers 30 , as shown in FIG. 1 , each of the second dielectric layers 60 At least one second groove 61 is formed thereon, and each of the second grooves 61 exposes each of the second protective layers 50 to the outside, so that each of the second protective layers 50 can be electrically connected to the outside. The third embodiment of the present invention is only provided with two layers of dielectric layers, which is different from the three-layer dielectric layers provided in the existing conductive wiring structure, which is beneficial to reduce the thickness and process. The conductivity of each of the conductive lines 40 in the circuit structure 1 is also improved, thereby increasing product performance.

The above are only the preferred embodiments of the present invention, which are only illustrative rather than restrictive for the present invention; those of ordinary skill in the art will understand that within the spirit and scope defined by the claims of the present invention, the Many changes, modifications and even equivalent changes can be made to it, but they will all fall within the protection scope of the present invention.

Claims (9)

1. A lead wire structure of a chip package, the lead wire structure being mounted and bonded on a substrate in a plurality of numbers, the lead wire structure comprising:

a chip having a surface on which a plurality of bonding pads are disposed;

a plurality of first protection layers, each of which is correspondingly covered on the surface of the chip and covers each of the bonding pads of the chip; wherein each first protection layer is electrically connected with each welding pad of the chip;

a plurality of first dielectric layers, each of which covers the surface of the chip and is formed with at least one first groove for electrically connecting each bonding pad of the chip;

a plurality of conducting circuits, wherein each conducting circuit covers the surface of the wafer and each first protective layer, and part of each conducting circuit is arranged in each first groove; and

a plurality of second protective layers, each of which is correspondingly arranged on the surface of each conducting circuit and the surface of each first dielectric layer in a covering manner, and covers each welding pad of the wafer; wherein each second protection layer is electrically connected with each conductive circuit, and each second protection layer is electrically connected with each welding pad of the wafer through each conductive circuit.

2. The bonding wire structure of claim 1, wherein each of the first dielectric layers is formed by a spin coating process.

3. The conducting circuit structure of claim 1, wherein the first recess is filled with metal by one of silver paste printing, sputtering, chemical vapor deposition, sputtering and electroplating, or chemical vapor deposition and electroplating.

4. A lead wire structure of a chip package, the lead wire structure being mounted and bonded on a substrate in a plurality of numbers, the lead wire structure comprising:

a chip having a surface on which a plurality of bonding pads are disposed;

a plurality of first protection layers, each of which is correspondingly covered on the surface of the chip and covers each of the bonding pads of the chip; wherein each first protection layer is electrically connected with each bonding pad of the chip;

the first dielectric layers are arranged on the surface of the wafer in a covering manner, at least one first groove is formed on each first dielectric layer, and each first groove is used for electrically connecting each welding pad of the wafer to the outside;

a plurality of conducting circuits, wherein each conducting circuit covers the surface of the wafer and each first protective layer, and part of each conducting circuit is arranged on the annular side wall of each first dielectric layer;

a plurality of second protective layers, each of which is correspondingly arranged on the surface of each of the conductive circuits in a covering manner and covers each of the bonding pads of the chip; wherein each second protective layer is electrically connected with each conductive circuit, and each second protective layer is electrically connected with each welding pad of the wafer through each conductive circuit; and

a plurality of second dielectric layers, each second dielectric layer covering the surface of each first dielectric layer, and each second dielectric layer being formed with at least one second groove for each conducting circuit to be electrically connected to the outside; wherein each of the second dielectric layers is not connected to or in contact with each of the second protective layers.

5. The conducting line structure of claim 4, wherein each of the first dielectric layers and each of the second dielectric layers are formed by a spin coating process.

6. The conducting circuit structure of claim 4, wherein the first and second grooves are filled with metal material selected from one of silver paste printing, sputtering, chemical vapor deposition, sputtering and electroplating, or chemical vapor deposition and electroplating.

7. A lead wire structure of a chip package, which is mounted and combined on a substrate in a plurality of numbers, the lead wire structure comprising:

a chip having a surface on which a plurality of bonding pads are disposed;

a plurality of first protection layers, wherein each first protection layer is correspondingly arranged on the surface of the wafer in a covering manner, and covers each welding pad of the wafer; wherein each first protection layer is electrically connected with each welding pad of the chip;

the first dielectric layers are arranged on the surface of the wafer in a covering manner, at least one first groove is formed on each first dielectric layer, and each first groove is used for electrically connecting each welding pad of the wafer to the outside;

a plurality of conducting circuits, wherein each conducting circuit covers the surface of the wafer and each first protective layer, and part of each conducting circuit is arranged in each first groove;

a plurality of second protective layers, each of which is correspondingly arranged on the surface of each of the conductive circuits in a covering manner and covers each of the bonding pads of the chip; wherein each second protective layer is electrically connected with each conductive circuit, and each second protective layer is electrically connected with each welding pad of the wafer through each conductive circuit; and

and each second dielectric layer covers the surface of each first dielectric layer, at least one second groove is formed on each second dielectric layer, and each second groove is used for exposing each second protective layer outwards so that each second protective layer can be electrically connected outwards.

8. The conducting line structure of claim 7, wherein each of the first dielectric layers and each of the second dielectric layers are formed by a spin coating process.

9. The conducting circuit structure of claim 7, wherein the first and second grooves are filled with metal selected from one of silver paste printing, sputtering, chemical vapor deposition, sputtering and electroplating, or chemical vapor deposition and electroplating.

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