CN216596961U - Memory cell for tristable storage - Google Patents

Abstract

The application relates to a memory cell for tristable storage, comprising: the first homogeneous phase inverter is composed of a first bipolar field effect transistor and is used for storing ternary data; the second homogeneous phase inverter is composed of a second bipolar field effect transistor and is used for storing ternary data; the input port of the first homogeneous phase inverter is connected with the output port of the second homogeneous phase inverter to obtain a node voltage Vx, the input port of the second homogeneous phase inverter is connected with the output port of the first homogeneous phase inverter to obtain a node voltage Vy, and when the node voltage Vx and the node voltage Vy are in a stable state, the first homogeneous phase inverter and the second homogeneous phase inverter are in cross connection and used for three-stable-state storage. Therefore, the problem that in the related technology, only binary data can be stored, and the storage efficiency is low is solved, the information storage efficiency can be improved, and the number of used devices cannot be increased remarkably.

Description

Memory cells for tri-stable storage

technical field

The present application relates to the field of semiconductor technology, and in particular, to a memory cell for tri-stable storage.

Background technique

In the related art, a static random-access memory (SRAM) uses a cross-connected CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) inverter as a core storage unit to achieve 0-1 bistable Latch, store logic 0 or logic 1.

However, since the internal CMOS steady-state level is fixed to VDD or VSS, data can only be stored in the framework of binary representation, which limits the further improvement of information storage efficiency and needs to be solved urgently.

Utility model content

The present application provides a storage unit for tri-stable storage, so as to solve the problem that only binary data can be stored in the related art, resulting in low storage efficiency, and can store ternary data, which can not only improve information storage efficiency , without significantly increasing the number of devices used.

The present application provides a storage unit for tri-stable storage, comprising:

a first homogeneous inverter, the first homogeneous inverter is composed of a first bipolar field effect transistor, and is used for storing ternary data;

a second homogeneous inverter, the second homogeneous inverter is composed of a second bipolar field effect transistor, and is used for storing ternary data;

Wherein, the input port of the first homogeneous inverter is connected to the output port of the second homogeneous inverter to obtain the node voltage Vx, and the input port of the second homogeneous inverter is connected to the first homogeneous inverter. The output ports of a homogeneous inverter are connected to obtain a node voltage Vy, so that when the node voltage Vx and the node voltage Vy are in a steady state, the first homogeneous inverter and the second homogeneous inverter Inverters are cross-connected for tristable storage.

Optionally, the first power supply terminal F1 and the second power supply terminal NF1 of the first homogeneous inverter and the third power supply terminal F2 and the fourth power supply terminal NF2 of the second homogeneous inverter supply power.

Optionally, the second power supply terminal NF1 and the fourth power supply terminal NF2 fixedly represent the remainder of the level of the first power supply terminal F1 and the third power supply terminal F2 relative to the power supply level.

Optionally, the first homogeneous inverter and the second homogeneous inverter are sequential inverters or inverted inverters.

Optionally, the node voltage Vx and the node voltage Vy exhibiting a steady state include a (0, 1) steady state or a (1, 0) steady state exhibited by cross-connecting two cis-inverters, or two inversions. (1, 2) steady state or (2, 1) steady state exhibited by an inverter cross-connection, or (2, 0) steady state or (0) steady state exhibited by a cis-inverter and an inverted inverter cross-connection , 2) steady state.

Optionally, the ratio of the pull-up and pull-down networks of the inversion inverter is equal to the inverse of the ratio of the pull-up and pull-down networks of the clockwise inverter.

Therefore, by cross-connecting homogeneous inverters composed of bipolar field effect transistors, a three-level voltage state is realized, and ternary data can be stored, which solves the problem that only binary data can be stored in the related art. , leading to the problem of low storage efficiency, which can not only improve the information storage efficiency, but also not significantly increase the number of devices used.

Additional aspects and advantages of the present application will be set forth, in part, in the following description, and in part will be apparent from the following description, or learned by practice of the present application.

Description of drawings

The above and/or additional aspects and advantages of the present application will become apparent and readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, wherein:

1 is a schematic structural diagram of a memory cell for tri-stable storage provided according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a structure of a sequence inverter according to an embodiment of the present application.

3 is a schematic diagram of a voltage curve of a sequence inverter according to an embodiment of the present application;

FIG. 4 is a structural example diagram of an inverted inverter according to an embodiment of the present application.

5 is a schematic diagram of a voltage curve of an inverted inverter according to an embodiment of the present application;

6 is a schematic diagram of a curve of a memory cell of tri-stable storage according to an embodiment of the present application during the first stable state;

7 is a schematic diagram of a curve of a memory cell stored in a tri-stable state in a second stable state according to an embodiment of the present application;

8 is a schematic diagram of a curve of a memory cell stored in a tri-stable state in a third stable state according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a curve of a memory cell stored in a tri-stable state in a third stable state according to another embodiment of the present application.

Detailed ways

The following describes in detail the embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, and are intended to be used to explain the present application, but should not be construed as a limitation to the present application.

The following describes a memory cell for tri-stable storage according to an embodiment of the present application with reference to the accompanying drawings. Aiming at the problem that only binary data can be stored in the related art mentioned by the above-mentioned Background Technology Center, resulting in low storage efficiency, the present application provides a storage unit for tri-stable storage. The formed homogeneous inverters are cross-connected to realize a three-level voltage state, and can store ternary data, which solves the problem that only binary data can be stored in related technologies, resulting in low storage efficiency. Information storage efficiency without significantly increasing the number of devices used.

Specifically, FIG. 1 is a schematic structural diagram of a memory cell for tri-stable storage provided by an embodiment of the present application.

As shown in FIG. 1 , the storage unit 10 for tri-stable storage includes: a first homogeneous inverter 100 and a second homogeneous inverter 200 .

The first homogeneous inverter 100 is composed of a first bipolar field effect transistor (Ambipolar Field Effect Transistor, AFET), and is used for storing ternary data. The second homogeneous inverter 200 is composed of a second bipolar field effect transistor, and is used for storing ternary data;

Wherein, the groove lengths of the first homogeneous inverter 100 and the second homogeneous inverter 200 are the same, and the input port of the first homogeneous inverter 100 is connected to the output port of the second homogeneous inverter 200 to obtain The node voltage Vx, the input port of the second homogeneous inverter 200 is connected to the output port of the first homogeneous inverter 100 to obtain the node voltage Vy, so that when the node voltage Vx and the node voltage Vy are in a steady state, the first Homogeneous inverter 100 and second homogeneous inverter 200 are cross-connected for tristable storage.

Specifically, as shown in FIG. 1 , in the embodiment of the present application, two homogeneous inverters with the same combination of channel lengths are cross-connected, and it is assumed that the inverter on the left in FIG. 1 is the first homogeneous inverter 100, the inverter on the right is the second homogeneous inverter 200, then the input port of the first homogeneous inverter 100 is connected to the output port of the second homogeneous inverter 200 to obtain the node voltage Vx, the second homogeneous inverter The input port of the mass inverter 200 is connected to the output port of the first homogeneous inverter 100 to obtain the node voltage Vy.

Optionally, in some embodiments, the first homogeneous inverter 100 and the second homogeneous inverter 200 are sequential inverters or inverted inverters.

Optionally, in some embodiments, the pull-up pull-down network ratio of the inverted inverter is equal to the inverse of the pull-up pull-down network ratio of the compliant inverter.

It should be understood that the first homogeneous inverter 100 and the second homogeneous inverter 200 of the present application are completely composed of AFETs. The highest level Vmax and the lowest level Vmin that the pull-up and pull-down can reach, and the final level Vmin' will not completely reach the level value of the supply voltage, namely VDD and VSS; define the first homogeneous inverter 100 and In the second homogeneous inverter 200, Vmax' and Vmax are collectively referred to as pull-up levels, and Vmin and Vmin' are collectively referred to as pull-down levels. Assuming that the channel length of the pull-up device is L2 and the channel length of the pull-down device is L1, the ratio of the pull-up and pull-down network Z=L2/L1 determines the degree to which Vmax and Vmin are close to VDD and VSS; the greater the Z, the greater the Vmax. Away from VDD, Vmin is closer to VSS, and vice versa; on the other hand, Z also determines the level position of the threshold level VT of the inverter, the larger Z is, the closer VT is to VSS, and vice versa, it is closer to VDD;

Thus, in the embodiments of the present application, a homogeneous inverter with a suitable voltage transfer curve (VTC) can be obtained.

For ease of understanding, in this embodiment of the present application, the power supply voltage VDD=2V and VSS=0V are used for detailed description of the forward inverter or the inverted inverter.

As shown in Figure 2, after setting the appropriate channel length ratio Z=L2/L1, in Cadence, the threshold voltage VT shown in Figure 3 is around 0.5V, and the pull-up level is 0.18um in Cadence. A homogeneous inverter with a pull-down level near 0V near 1.0V is called a sine inverter.

The power supply levels VDD and VSS of the above inverters are exchanged to obtain the electrical configuration shown in Figure 4, and the inverter at this time is called an inverted inverter.

Among them, the ratio Z of the pull-up and pull-down network of the inverted inverter is equal to the reciprocal of the ratio of the compliant inverter. Therefore, the VTC of the inverted inverter in Fig. 4 presents a dual value of the VTC of the compliant inverter shown in Fig. 2. Properties, as shown in Figure 5, the curve in Figure 5 shows that the threshold voltage VT is around 1.5V, the pull-up level is around 2.0V, and the pull-down level is around 1.0V;

Therefore, according to the above results, it is assumed that the level of 0-0.5V can be regarded as logic 0, or 0 for short; the level of 0.75-1.25V can be regarded as logic 1, or 1 for short; the level of 1.5-2.0V can be regarded as logic 2, or simply 2, the corresponding relationship between the level and the logic value shown in Table 1 can be obtained.

Table 1

level logical value 0V-0.5V 0 0.75V-1.25V 1 1.5V-2.0V 2

Optionally, in some embodiments, as shown in FIG. 1 , the first power supply terminal F1 and the second power supply terminal NF1 of the first homogeneous inverter 100 and the third power supply terminal of the second homogeneous inverter 200 F2 and the fourth power supply terminal NF2 supply power.

Wherein, in some embodiments, the second power supply terminal NF1 and the fourth power supply terminal NF2 fixedly represent the remainder of the level of the first power supply terminal F1 and the third power supply terminal F2 relative to the power supply level.

That is to say, in the embodiment of the present application, four power supply terminals can be respectively supplied to F1, F2, NF1 and NF2, wherein NF1 and NF2 fixedly represent the remainder of the levels of F1 and F2 relative to the power supply level VDD.

Optionally, in some embodiments, the node voltage Vx and the node voltage Vy exhibit a steady state including a (0, 1) steady state or a (1, 0) steady state exhibited by a cross-connection of two cis-inverters, or both. (1, 2) steady state or (2, 1) steady state exhibited by a cross-connection of two inverted inverters, or (2, 0) steady state exhibited by a cross-connection of an inversion inverter and an inverted inverter, or (0,2) steady state.

Specifically, when F1=2V and F2=2V, as shown in FIG. 6 , the solid line in FIG. 6 represents the VTC of the first homogeneous inverter 100 , and the dotted line represents the VTC of the second homogeneous inverter 200 . When it is equivalent to the cross-connection of two cis-inverters, (Vx, Vy) presents (0, 1) or (1, 0) steady state.

When F1=0V, F2=0V, as shown in FIG. 7, the solid line in FIG. 7 represents the VTC of the first homogeneous inverter 100, and the dotted line represents the VTC of the second homogeneous inverter 200, which is equivalent to The two inverted inverters are cross-connected so that (Vx, Vy) exhibits a (1, 2) or (2, 1) steady state.

When F1=2V, F2=0V, or F1=0V, F2=2V, as shown in FIG. 8 and FIG. 9, respectively, the solid line in FIG. 8 and FIG. 9 represents the VTC of the first homogeneous inverter 100, and the dotted line Represents the VTC of the second homogeneous inverter 200, which is equivalent to the cross-connection of the cis and inverted inverters at this time, so (Vx, Vy) presents (2, 0) or (0, 2) steady state;

Therefore, by specifying the first power supply terminal F1 and the third power supply terminal F2, three different steady-state levels can be realized in the same hardware circuit, so that they can be used as tri-state storage units of the SRAM.

According to the memory cell for tri-stable storage proposed by the embodiment of the present application, by cross-connecting homogeneous inverters composed of bipolar field effect transistors, a three-level voltage state is realized, and ternary data can be stored. The storage solves the problem that only binary data can be stored in the related art, resulting in low storage efficiency. It can not only improve the information storage efficiency, but also does not significantly increase the number of devices used.

In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or N of the embodiments or examples. Furthermore, those skilled in the art may combine and combine the different embodiments or examples described in this specification, as well as the features of the different embodiments or examples, without conflicting each other.

In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature delimited with "first", "second" may expressly or implicitly include at least one of that feature. In the description of the present application, "N" means at least two, such as two, three, etc., unless otherwise expressly and specifically defined.

It should be understood that various parts of this application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the N steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one of the following techniques known in the art, or a combination thereof: discrete with logic gates for implementing logic functions on data signals Logic circuits, application specific integrated circuits with suitable combinational logic gates, Programmable Gate Arrays (PGA), Field Programmable Gate Arrays (FPGA), etc.

Those of ordinary skill in the art can understand that all or part of the steps carried by the methods of the above embodiments can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium, and the program is stored in a computer-readable storage medium. When executed, one or a combination of the steps of the method embodiment is included.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing module, or each unit may exist physically alone, or two or more units may be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware, and can also be implemented in the form of software function modules. If the integrated modules are implemented in the form of software functional modules and sold or used as independent products, they may also be stored in a computer-readable storage medium.

The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, and the like. Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limitations to the present application. Embodiments are subject to variations, modifications, substitutions and variations.

Claims (7)

1. A memory cell for tristable storage, comprising:

a first homogeneous inverter composed of a first bipolar field effect transistor for storing ternary data;

a second homogenous inverter constituted by a second bipolar field effect transistor for storing ternary data;

the input port of the first homogeneous phase inverter is connected with the output port of the second homogeneous phase inverter to obtain a node voltage Vx, the input port of the second homogeneous phase inverter is connected with the output port of the first homogeneous phase inverter to obtain a node voltage Vy, and when the node voltage Vx and the node voltage Vy are in a stable state, the first homogeneous phase inverter and the second homogeneous phase inverter are in cross connection and used for storing in a three-stable state.

2. The memory cell for tristatable storage as recited in claim 1 wherein said first homogeneous inverter and said second homogeneous inverter have the same trench length.

3. The memory cell of claim 1, wherein the first F1 and second NF1 supply terminals of the first homogeneous inverter and the third F2 and fourth NF2 supply terminals of the second homogeneous inverter.

4. The memory cell of claim 3, wherein the second supply terminal NF1 and the fourth supply terminal NF2 are fixed to represent a remainder of the levels of the first supply terminal F1 and the third supply terminal F2 relative to the supply level.

5. The memory cell for tristable storage of claim 1 wherein said first homogenous inverter and said second homogenous inverter are either a forward inverter or an inverted inverter.

6. The memory cell of claim 5, wherein the node voltage Vx and the node voltage Vy exhibit a steady state comprising a (0, 1) steady state or a (1, 0) steady state exhibited by two sequential inverters cross-connected, or a (1, 2) steady state or a (2, 1) steady state exhibited by two inverted inverters cross-connected, or a (2, 0) steady state or a (0, 2) steady state exhibited by one sequential inverter and one inverted inverter cross-connected.

7. The memory cell for tristatable storage as recited in claims 5 or 6 wherein the pull-up pull-down network proportion of the inverted inverter is equal to the inverse of the pull-up pull-down network proportion of the sequential inverter.

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