CN216351005U - Quick testing arrangement of piezo-resistor chip - Google Patents
Quick testing arrangement of piezo-resistor chip Download PDFInfo
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- CN216351005U CN216351005U CN202122974796.9U CN202122974796U CN216351005U CN 216351005 U CN216351005 U CN 216351005U CN 202122974796 U CN202122974796 U CN 202122974796U CN 216351005 U CN216351005 U CN 216351005U
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- piezoresistor
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- 238000012360 testing method Methods 0.000 title claims abstract description 81
- 230000005611 electricity Effects 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 230000001419 dependent effect Effects 0.000 description 10
- 238000011056 performance test Methods 0.000 description 3
- 238000007792 addition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
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Abstract
The utility model discloses a quick testing device of a piezoresistor chip, which comprises a piezoresistor tester, a first testing wire and a second testing wire, wherein one end of each of the first testing wire and the second testing wire is inserted into a corresponding testing hole of the piezoresistor tester, and the quick testing device is characterized in that: still include insulating supporting platform, current conducting plate and test pen, the current conducting plate is installed on insulating supporting platform's upper surface, and the current conducting plate is connected with the first test wire other end electricity, and the test pen includes insulating pen-holder and conductive nib, and conductive nib is connected with the second test wire other end electricity. The quick testing device for the piezoresistor chip is convenient to operate, can quickly test a plurality of piezoresistors, accelerates the testing speed of testers, improves the production efficiency, reduces the labor intensity, and is suitable for large-batch testing of the piezoresistor chip.
Description
Technical Field
The utility model relates to the technical field of voltage dependent resistor processing, in particular to a quick testing device for a voltage dependent resistor chip.
Background
The piezoresistor is a voltage-limiting type protection device. By utilizing the nonlinear characteristic of the piezoresistor, when overvoltage appears between two poles of the piezoresistor, the piezoresistor can clamp the voltage to a relatively fixed voltage value, thereby realizing the protection of a post-stage circuit.
After the piezoresistor is processed, a piezoresistor tester is required to perform performance test, and generally, the piezoresistor is used for testing the piezovoltage, the leakage current and the nonlinear coefficient alpha value. The end parts of two testing wires of the piezoresistor tester are respectively connected with a conductive clip, when the piezoresistor tester is used for performance testing, a manual mode is usually adopted for testing, two pins of a piezoresistor need to be respectively clamped by the two conductive clips, the reading of the piezoresistor tester is observed by eyes, the specified time is waited for, whether the performance of the piezoresistor is qualified is judged, and therefore the piezoresistor is tested, and the steps are repeated in a cycle and are repeated continuously. The test method has the advantages of complex operation, long consumed time, low working efficiency and high labor intensity.
Disclosure of Invention
The utility model aims to provide a quick testing device for a piezoresistor chip, which is convenient to operate, can quickly test a plurality of piezoresistors, improves the production efficiency and reduces the labor intensity.
In order to solve the technical problems, the technical scheme adopted by the utility model is as follows:
the utility model provides a quick testing arrangement of piezo-resistor chip, includes piezo-resistor tester, first test wire and second test wire, and first test wire and second test wire respectively have one end to peg graft in the corresponding test hole of piezo-resistor tester, its characterized in that: still include insulating supporting platform, current conducting plate and test pen, the current conducting plate is installed on insulating supporting platform's upper surface, and the current conducting plate is connected with the first test wire other end electricity, and the test pen includes insulating pen-holder and conductive nib, and conductive nib is connected with the second test wire other end electricity.
And forming electrodes on two surfaces of the voltage dependent resistor medium sheet to obtain a voltage dependent resistor chip, and testing the voltage dependent voltage, leakage current, non-linear coefficient alpha value and other performance parameters of the corresponding voltage dependent resistor. During testing, a plurality of processed piezoresistor chips can be tiled on the current conducting plate, so that the electrode at the lower side of each piezoresistor chip is in contact with the current conducting plate, a tester only needs to hold the insulating pen holder of the test pen with one hand, so that the conductive pen point of the test pen is in contact with the electrode at the upper side of a certain piezoresistor chip and slightly presses downwards with force, and then a complete test loop can be formed among the piezoresistor chips, the current conducting plate, the first test wire, the piezoresistor tester, the second test wire and the test pen, the circuit is conducted, the piezoresistor tester can display the data of the piezoresistor, and the tester judges that the performance test of the piezoresistor is qualified by reading the data, namely, the test of one piezoresistor chip is completed; the other piezoresistor chips are tested only by holding the conductive pen point of the test pen to be in contact with the electrodes on the upper sides of the conductive pen point and the electrodes, and the other hand of the tester can be relaxed appropriately to have a rest, so that the labor intensity is reduced.
Generally, the area size of the conductive plate can be set according to the number of the piezoresistor chips to be detected.
In a preferred embodiment of the present invention, the conductive plate has a smooth upper surface. The conductive plate with a smooth upper surface can be better contacted with the electrode on the lower side of the piezoresistor chip.
In a preferred embodiment of the present invention, the conductive plate is a metal plate.
In a further preferred embodiment of the present invention, the metal plate is made of copper.
Compared with the prior art, the utility model has the following advantages:
the quick testing device for the piezoresistor chip is convenient to operate, can quickly test a plurality of piezoresistors, accelerates the testing speed of testers, improves the production efficiency, reduces the labor intensity, and is suitable for large-batch testing of the piezoresistor chip.
Drawings
Fig. 1 is a schematic structural diagram of an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, the rapid testing device for a varistor chip in this embodiment includes a varistor tester 1, a first test line 2, a second test line 3, an insulating support platform 4, a conductive plate 5 and a test pen 6, wherein each of the first test line 2 and the second test line 3 has one end inserted into a corresponding test hole 11 of the varistor tester 1, the conductive plate 5 is installed on the upper surface of the insulating support platform 4, the conductive plate 5 is electrically connected to the other end of the first test line 2, the test pen 6 includes an insulating pen holder 61 and a conductive pen tip 62, and the conductive pen tip 62 is electrically connected to the other end of the second test line 3.
In general, the area of the conductive plate 5 may be set according to the number of the varistor chips to be detected.
The upper surface of the conductive plate 5 is smooth, and the conductive plate 5 is a metal plate. The metal plate is made of copper. The conductive plate 5 having a smooth upper surface can be better brought into contact with the electrode on the lower side of the varistor chip.
After electrodes are formed on two surfaces of the voltage dependent resistor medium sheet to obtain the voltage dependent resistor chip 7, performance parameters such as voltage dependent voltage, leakage current and nonlinear coefficient alpha value of the corresponding voltage dependent resistor can be tested. During testing, a plurality of processed piezoresistor chips 7 can be tiled on the current conducting plate 5, so that the electrode at the lower side of each piezoresistor chip 7 is in contact with the current conducting plate 5, a tester only needs to hold the insulating pen holder 61 of the test pen 6 with one hand, so that the conductive pen point 62 of the test pen 6 is in contact with the electrode at the upper side of a certain piezoresistor chip 7 and slightly presses down with force, and then the piezoresistor chips 7, the current conducting plate 5, the first test line 2, the piezoresistor tester 1, the second test line 3 and the test pen 6 can form a complete test loop, the circuit is conducted, the piezoresistor tester 1 can display the data of the piezoresistor, and the tester judges that the performance test of the piezoresistor is qualified by reading the data, so that the test of one piezoresistor chip 7 is completed; in the test of other piezoresistor chips 7, only the conductive pen point 62 of the test pen 6 is needed to be held to be in contact with the electrodes on the upper sides of the piezoresistor chips, and the other hand of the tester can be relaxed appropriately to rest, so that the labor intensity is reduced.
In addition, it should be noted that the names of the parts and the like of the embodiments described in the present specification may be different, and the equivalent or simple change of the structure, the characteristics and the principle described in the present patent idea is included in the protection scope of the present patent. Various modifications, additions and substitutions for the specific embodiments described may be made by those skilled in the art without departing from the scope of the utility model as defined in the accompanying claims.
Claims (4)
1. The utility model provides a quick testing arrangement of piezo-resistor chip, includes piezo-resistor tester, first test wire and second test wire, and first test wire and second test wire respectively have one end to peg graft in the corresponding test hole of piezo-resistor tester, its characterized in that: still include insulating supporting platform, current conducting plate and test pen, the current conducting plate is installed on insulating supporting platform's upper surface, and the current conducting plate is connected with the first test wire other end electricity, and the test pen includes insulating pen-holder and conductive nib, and conductive nib is connected with the second test wire other end electricity.
2. The device for rapidly testing a varistor chip as claimed in claim 1, wherein: the upper surface of the conductive plate is smooth.
3. The device for rapidly testing a varistor chip as claimed in claim 1, wherein: the conductive plate is a metal plate.
4. The device for rapidly testing a varistor chip as claimed in claim 3, wherein: the metal plate is made of copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122974796.9U CN216351005U (en) | 2021-11-30 | 2021-11-30 | Quick testing arrangement of piezo-resistor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122974796.9U CN216351005U (en) | 2021-11-30 | 2021-11-30 | Quick testing arrangement of piezo-resistor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216351005U true CN216351005U (en) | 2022-04-19 |
Family
ID=81155630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122974796.9U Active CN216351005U (en) | 2021-11-30 | 2021-11-30 | Quick testing arrangement of piezo-resistor chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216351005U (en) |
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2021
- 2021-11-30 CN CN202122974796.9U patent/CN216351005U/en active Active
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