CN216054694U - Chip packaged by ceramic substrate - Google Patents
Chip packaged by ceramic substrate Download PDFInfo
- Publication number
- CN216054694U CN216054694U CN202122511871.8U CN202122511871U CN216054694U CN 216054694 U CN216054694 U CN 216054694U CN 202122511871 U CN202122511871 U CN 202122511871U CN 216054694 U CN216054694 U CN 216054694U
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- China
- Prior art keywords
- ceramic
- circuit board
- wafer
- layer
- based circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
A chip packaged by a ceramic substrate comprises a ceramic-based circuit board, wherein the ceramic-based circuit board consists of a circuit layer and a ceramic base layer, and a wafer substrate bonding pad is distributed on the circuit layer of the ceramic-based circuit board; the wafer is fixed on the wafer substrate bonding pad, and two or more than two groups of bonding pads are distributed on the wafer; the ceramic-based circuit board is clamped in the U-shaped groove by the two or more than two groups of U-shaped metal pins and fixed on the ceramic-based circuit board; and two or more groups of input and output bonding pads on the wafer are correspondingly connected with two or more groups of U-shaped metal pins in a conduction mode through bonding wires. The ceramic-based circuit board is used as a substrate for chip packaging, so that the heat conduction capability of the substrate is ensured; the ceramic base layer has good insulativity; the U-shaped metal pins are adopted, so that the sectional area can be conveniently increased to increase the current carrying capacity of the chip.
Description
Technical Field
The utility model relates to a chip packaging structure. By reconstructing the packaging structure of the chip, better chip performance is realized.
Background
A large number of chips are required to be used in electronic products. The chip is a product obtained by packaging the wafer.
Chip packaging, namely, a contact pad on a wafer is connected and led to an external joint by a lead so as to be connected with other devices; and pouring glue, sealing and forming. The wafer packaging structure not only plays the roles of mounting, fixing, sealing and protecting the wafer, but also is connected to pins of the packaging shell through the contact pads on the wafer by leads, and the pins are connected with other devices through leads on the printed circuit board, so that the connection of an internal chip and an external circuit is realized. Since the wafer must be isolated from the outside to prevent the electrical performance degradation caused by the corrosion of the chip circuit by the impurities in the air.
In chip packaging, a bonding pad on a wafer is connected with an external bonding pad or a chip pin by a wire, and the packaging industry is called bonding; bonding is a term well known to practitioners; originating from the english binding word.
The ceramic-based circuit board is a special process board in which copper foil is directly bonded to the surface of a ceramic substrate at high temperature. The prepared composite substrate has excellent electrical insulation performance and high heat conduction characteristic. Comprises a ceramic substrate and a circuit layer.
In the existing packaging structure, most of pins are in the chip, and because the volume of the chip is limited and the process requirements for the operation of the pins are caused, the thickness and the width of the pins are limited, which directly causes the output current capability of the chip to be influenced; the encapsulation of the chip limits the heat dissipation capability of the chip itself, which results in limited chip performance and power. Especially for some power chips, it is critical to improve heat dissipation and current carrying capabilities.
Disclosure of Invention
Aiming at the problems, the utility model aims to provide a chip packaged by a ceramic substrate, wherein a ceramic-based circuit board is used as the substrate to increase the current carrying capacity of the chip; and the heat dissipation capability of the chip can be increased, thereby increasing the performance and efficiency of the chip.
In order to realize the technical purpose, the scheme of the utility model is as follows: a chip packaged by a ceramic substrate comprises a ceramic-based circuit board, wherein the ceramic-based circuit board consists of a circuit layer and a ceramic base layer, and a wafer substrate bonding pad is distributed on the circuit layer of the ceramic-based circuit board; the wafer is fixed on the wafer substrate bonding pad, and two or more than two groups of bonding pads are distributed on the wafer; the ceramic-based circuit board is clamped in the U-shaped groove by the two or more than two groups of U-shaped metal pins and fixed on the ceramic-based circuit board; and two or more groups of bonding pads on the wafer are correspondingly connected with two or more groups of U-shaped metal pins in a conductive way through bonding wires.
Preferably, the ceramic-based circuit board adopts a two-layer ceramic-based circuit board, the two-layer ceramic-based circuit board is composed of a top layer circuit layer, a ceramic base layer and a bottom layer circuit layer, and a heat dissipation copper foil is arranged on the bottom layer circuit layer.
The beneficial effects of this technical scheme are: mature technology can be used, and the capability of inputting and outputting current of the chip is greatly improved; the heat dissipation capability of the chip is increased.
Drawings
Fig. 1 is a schematic top view of a chip according to a first embodiment of the utility model.
Fig. 2 is a schematic side cross-sectional view of a chip according to a first embodiment of the utility model.
FIG. 3 is a schematic view of a U-shaped metal pin according to the present invention.
FIG. 4 is a schematic diagram of a two-layer ceramic based circuit board of the present invention.
Fig. 5 is a schematic side cross-sectional view of a chip according to a second embodiment of the utility model.
Fig. 6 is a bottom view of a chip according to a second embodiment of the utility model.
Detailed Description
The utility model is described in further detail below with reference to the figures and specific embodiments.
As shown in fig. 1, a chip packaged by a ceramic substrate includes a ceramic-based circuit board 1, where the ceramic-based circuit board 1 is composed of a circuit layer 11 and a ceramic base layer 12, and a wafer substrate pad 111 is disposed on the circuit layer 11 of the ceramic-based circuit board; the wafer 2 is fixed on a wafer substrate bonding pad 111, and two or more than two groups of bonding pads are distributed on the wafer 2, including a wafer bonding pad 21, a wafer bonding pad 22, a wafer bonding pad 23 and a wafer bonding pad 24; the ceramic base circuit board is characterized by also comprising two or more than two groups of U-shaped metal pins 3, wherein the two or more than two groups of U-shaped metal pins 3 comprise U-shaped metal pins 31, U-shaped metal pins 32, U-shaped metal pins 33 and U-shaped metal pins 34, and the ceramic base circuit board 1 is clamped in the U-shaped groove and fixed on the ceramic base circuit board 1 by the two or more than two groups of U-shaped metal pins 3; two or more than two groups of bonding pads on the wafer 2 are correspondingly connected with two or more than two groups of U-shaped metal pins 3 in a conductive manner through bonding wires 4, and the wafer bonding pad 21 is connected with one group of U-shaped metal pins 31 in a conductive manner through bonding wires 41.
And (5) performing glue pouring and sealing on the wafer 2 and the bonding wire 4 to obtain a chip finished product.
Fig. 2 is a schematic side cross-sectional view of a chip according to a first embodiment of the utility model.
The wafer 2 is fixed on a wafer substrate bonding pad 111 arranged on a circuit layer 11 of the ceramic-based circuit board 1, and is correspondingly connected with two or more than two groups of U-shaped metal pins 3 in a conducting manner through bonding wires 4.
Fig. 3 is a schematic view of a U-shaped metal pin according to the present invention. Because the U-shaped metal pins 3 are externally arranged on the side surface of the chip substrate, the sectional area of the U-shaped metal pins can be conveniently increased according to the current-carrying requirement of the chip, and the current-carrying capacity of the chip is increased. In addition, two or more than two U-shaped metal pins also have high heat-conducting property, and heat generated by the work of the wafer can be directly conducted to the two or more than two U-shaped metal pins through bonding wires, so that the heat dissipation capacity of the chip is improved.
FIG. 4 is a schematic diagram of a two-layer ceramic-based circuit board according to the present invention. The two-layer ceramic-based circuit board 1 is composed of a top layer circuit layer 11, a ceramic base layer 12 and a bottom layer circuit layer 13.
Fig. 5 is a schematic side cross-sectional view of a chip according to a second embodiment of the utility model. The chip substrate is a two-layer ceramic-based circuit board, a wafer substrate bonding pad 111 is arranged on a top layer circuit layer of the two-layer ceramic-based circuit board, and the wafer 2 is fixed on the wafer substrate bonding pad 111; the heat dissipation copper foil 131 is arranged on the bottom layer circuit layer of the two ceramic-based circuit boards, the copper foil can improve the heat dissipation capacity, when the chip is applied to an electronic product, the heat dissipation copper foil 131 can be welded on the circuit board of the electronic product, the chip conducts heat to the circuit board of the electronic product through the heat dissipation copper foil 131, the heat dissipation capacity is further enhanced, and therefore the performance and the power of the chip are improved.
Fig. 6 is a bottom view of a chip according to a second embodiment of the utility model. The whole radiating copper foil 131 is arranged on the bottom layer circuit layer of the two ceramic-based circuit boards.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and any minor modifications, equivalent replacements and improvements made to the above embodiment according to the technical spirit of the present invention should be included in the protection scope of the technical solution of the present invention.
Claims (2)
1. A chip packaged by a ceramic substrate is characterized in that: the ceramic-based circuit board is composed of a circuit layer and a ceramic base layer, and a wafer substrate bonding pad is arranged on the circuit layer of the ceramic-based circuit board; the wafer is fixed on the wafer substrate bonding pad, and two or more than two groups of bonding pads are distributed on the wafer; the ceramic-based circuit board is clamped in the U-shaped groove by the two or more than two groups of U-shaped metal pins and fixed on the ceramic-based circuit board; and two or more groups of bonding pads on the wafer are correspondingly connected with two or more groups of U-shaped metal pins in a conductive way through bonding wires.
2. The chip packaged by the ceramic substrate according to claim 1, wherein: the ceramic-based circuit board adopts two layers of ceramic-based circuit boards, each of the two layers of ceramic-based circuit boards consists of a top layer circuit layer, a ceramic base layer and a bottom layer circuit layer, and a heat dissipation copper foil is arranged on the bottom layer circuit layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122511871.8U CN216054694U (en) | 2021-10-19 | 2021-10-19 | Chip packaged by ceramic substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122511871.8U CN216054694U (en) | 2021-10-19 | 2021-10-19 | Chip packaged by ceramic substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216054694U true CN216054694U (en) | 2022-03-15 |
Family
ID=80609752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122511871.8U Active CN216054694U (en) | 2021-10-19 | 2021-10-19 | Chip packaged by ceramic substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216054694U (en) |
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2021
- 2021-10-19 CN CN202122511871.8U patent/CN216054694U/en active Active
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