CN215955282U

CN215955282U - Display panel and display device thereof

Info

Publication number: CN215955282U
Application number: CN202120778905.7U
Authority: CN
Inventors: 王蓉; 张波; 马倩; 董向丹; 舒晓青; 高雅瑰; 宋二龙; 赵佳星; 付雨婷; 曾振助
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-04-15
Filing date: 2021-04-15
Publication date: 2022-03-04
Anticipated expiration: 2031-04-15

Abstract

The utility model provides a display substrate and a display device. A display substrate comprises a substrate, a plurality of sub-pixels in a display region, a plurality of contact pads in a peripheral region, a peripheral region insulating layer and a peripheral region inorganic layer, at least one of the plurality of contact pads includes a first conductor portion, a second conductor portion, and a third conductor portion, the first conductor part is positioned on the substrate base plate, the second conductor part is positioned on one side of the first conductor part, which faces away from the substrate base plate, and is electrically connected with the first conductor part, the third conductor portion is located on a side of the second conductor portion facing away from the substrate base plate and is electrically connected with the second conductor portion, the third conductor portion is electrically connected to the second conductor portion through a second via hole provided in the peripheral region inorganic layer, wherein a projection of the first conductor portion on the substrate baseplate is located within a projection of the second via on the substrate baseplate.

Description

Display panel and display device thereof

Technical Field

The utility model relates to the technical field of display, in particular to a display substrate and a display device thereof.

Background

With the development of display technology, the requirements for display panels are also increasing. The display substrate typically includes a plurality of contact pads, which are formed by a plurality of film layers. In the manufacturing process of the display substrate, the bonding of the contact pad and other circuits easily causes the contact pad film layer to break or peel off, thereby affecting the display effect.

SUMMERY OF THE UTILITY MODEL

An embodiment of the present invention provides a display substrate, including:

the substrate comprises a display area and a peripheral area surrounding the display area;

a plurality of sub-pixels located in the display area and arranged in an array;

a plurality of contact pads located in the peripheral region, wherein at least one of the plurality of contact pads includes a first conductor portion located on the substrate base plate, a second conductor portion located on a side of the first conductor portion facing away from the substrate base plate and electrically connected to the first conductor portion, and a third conductor portion located on a side of the second conductor portion facing away from the substrate base plate and electrically connected to the second conductor portion;

a peripheral region insulating layer located in the peripheral region, the second conductor portion being electrically connected to the first conductor portion through a first via hole provided in the peripheral region insulating layer; and

and the third conductor part is electrically connected with the second conductor part through a second via hole arranged in the peripheral area inorganic layer, and the projection of the first conductor part on the substrate base plate is positioned in the projection of the second via hole on the substrate base plate.

For example, the display substrate further includes:

a peripheral region planarization layer on a side of the peripheral region inorganic layer facing the substrate, and the peripheral region inorganic layer is in contact with the second conductor portion through a third via hole provided in the peripheral region planarization layer.

For example, the plurality of contact pads includes: a plurality of input contact pads arranged in a peripheral region on one side of the display region along a first direction, the first direction being a row direction of the array of the plurality of sub-pixels; and a plurality of output contact pads between the plurality of input contact pads and the display area and arranged along the first direction.

For example, the display substrate further includes:

a plurality of connection contact pads located in the peripheral region, wherein on a side of the plurality of input contact pads facing away from the display region, the first conductor portions of the input contact pads are electrically connected to the connection contact pads through first leads disposed in the peripheral region;

a gate driving circuit in a peripheral region on at least another side of the display region, the gate driving circuit being connected to the plurality of sub-pixels and configured to supply a gate driving signal to the plurality of sub-pixels, the first conductor portion of the output contact pad being electrically connected to the gate driving circuit or at least one of the plurality of sub-pixels through a second lead disposed in the peripheral region.

For example, the connection contact pad includes:

a fourth conductor portion located on the substrate and disposed on the same layer as the second conductor portion;

the fifth conductor part is positioned on one side, away from the substrate base plate, of the fourth conductor part and is arranged on the same layer as the third conductor part, and the fifth conductor part is electrically connected with the fourth conductor part through a fourth through hole arranged in the inorganic layer in the peripheral area; and

and the contact pad insulating part is positioned on one side, facing the substrate base plate, of the inorganic layer in the peripheral area and covers the edge of the fourth conductor part.

For example, the display substrate further includes a peripheral region planarization layer, the peripheral region inorganic layer is in contact with the fourth conductor portion through a fifth via hole disposed in the peripheral region planarization layer, and the contact pad insulating portion is disposed on the same layer as the peripheral region planarization layer.

For example, a pitch between a projected edge of the first conductor portion on the substrate base plate and a projected edge of the second via on the substrate base plate is in a range of 1 μm to 2 μm.

For example, a geometric center of a projection of the first conductor portion on the substrate base substantially coincides with a geometric center of a projection of the second via on the substrate base, a size of the projection of the first conductor portion on the substrate base in a first direction is in a range of 12 μm to 14 μm, a size of the projection of the second via on the substrate base in the first direction is in a range of 14 μm to 16 μm, and the first direction is a row direction of the array of the plurality of sub-pixels.

For example, a size of a projection of the second conductor portion on the substrate base plate in a first direction is in a range of 19 μm to 21 μm, and a size of a projection of the third conductor portion on the substrate base plate in the first direction is in a range of 20 μm to 22 μm, the first direction being a row direction of the array of the plurality of sub-pixels.

For example, a projection of the third via on the substrate base plate has a size in the first direction in a range of 16 μm to 20 μm.

For example, a projection of the first via on the substrate base plate has a size in a first direction in a range of 7 μm to 9 μm.

For example, a projection of the third conductor portion on the substrate base plate has a size in the range of 20 μm to 22 μm in the first direction and a size in the range of 140 μm to 150 μm in the second direction.

For example, the sidewall of the second via hole in the inorganic layer in the peripheral region has a slope angle θ 1 relative to the plane of the substrate;

the edge of the first conductor part is provided with a first surface facing the substrate base plate, a second surface departing from the substrate base plate and a third surface connecting the first surface and the second surface, the third surface of the first conductor part has a gradient angle theta 2 relative to the plane of the substrate base plate,

wherein theta 2 < theta 1.

For example, the slope angle θ 1 is in a range of 80 degrees to 90 degrees, and the slope angle θ 2 is in a range of 20 degrees to 30 degrees.

For example, the edge of the second conductor portion has a first surface facing the substrate base, a second surface facing away from the substrate base, and a third surface connecting the first surface and the second surface, and the third surface of the second conductor portion has a slope angle θ 3 with respect to a plane in which the substrate base is located;

the edge of the third conductor part is provided with a first surface facing the substrate base plate, a second surface departing from the substrate base plate and a third surface connecting the first surface and the second surface, and the third surface of the third conductor part has a slope angle theta 4 relative to the plane of the substrate base plate;

the side wall of the first via hole in the peripheral area insulating layer has a gradient angle theta 5 relative to the plane of the substrate base plate,

wherein theta 5 is more than theta 3 and less than theta 4.

For example, the slope angle θ 3 is in a range of 55 degrees to 65 degrees, the slope angle θ 4 is in a range of 58 degrees to 67 degrees, and the slope angle θ 5 is in a range of 40 degrees to 50 degrees.

For example, the projections of the first conductor portion, the second conductor portion, the third conductor portion, the first via, and the second via on the substrate base plate are all rectangles or parallelograms.

For example, at least one of the plurality of sub-pixels includes a thin film transistor including a gate, a source, and a drain, the first conductor portion of the plurality of contact pads is disposed at the same layer as the gate, and the second conductor portion is disposed at the same layer as the source and the drain.

For example, the display substrate further includes a light emitting element, a packaging layer, a first touch electrode layer, a second touch electrode layer and a touch insulating layer, the light emitting element is located on a side of the thin film transistor facing away from the substrate, the packaging layer is located on a side of the light emitting element facing away from the substrate, the first touch electrode layer is located on a side of the packaging layer facing away from the substrate, the touch insulating layer is located on a side of the first touch electrode layer facing away from the substrate and covers the first touch electrode layer, and the second touch electrode layer is located on a side of the touch insulating layer facing away from the substrate;

the inorganic layer and the touch insulating layer in the peripheral region are arranged on the same layer, and the third conductor portion and at least one of the first touch electrode layer and the second touch electrode layer are arranged on the same layer.

For example, at least one of the plurality of sub-pixels further includes a display region interlayer insulating layer, a display region first gate insulating layer, and a display region second gate insulating layer, the display region interlayer insulating layer is located between the gate electrode and the source and drain electrodes, the display region first gate insulating layer is located on a side of the display region interlayer insulating layer facing the substrate, and the display region second gate insulating layer is located between the display region interlayer insulating layer and the display region first gate insulating layer;

the peripheral area insulating layer comprises a peripheral area interlayer insulating layer and a peripheral area second gate insulating layer, wherein the peripheral area interlayer insulating layer and the display area interlayer insulating layer are arranged on the same layer, and the peripheral area second gate insulating layer and the display area second gate insulating layer are arranged on the same layer.

For example, at least one of the plurality of sub-pixels includes a thin film transistor including a gate electrode, a source electrode, and a drain electrode, and a via electrode electrically connected to one of the source electrode and the drain electrode, and the second conductor portion is disposed in the same layer as at least one of the source electrode, the drain electrode, and the via electrode.

Embodiments of the present invention also provide a display device, including the display substrate as described above.

Drawings

Fig. 1A illustrates a schematic plan view of a display substrate according to an embodiment of the present invention.

Fig. 1B illustrates a schematic plan view of a display area of the display substrate of fig. 1A.

Fig. 2A shows a schematic diagram of a cross-section of a contact pad of a display substrate.

Fig. 2B shows a scanning electron microscope image of the contact pad of fig. 2A.

Fig. 3 shows a schematic plan view of a contact pad of the display substrate of fig. 1.

FIG. 4A shows a cross-sectional view along A1-B1 in FIG. 3.

Fig. 4B shows a partial enlarged view of fig. 3.

Fig. 4C shows a scanning electron microscope image corresponding to the cross-sectional view of fig. 4A.

Fig. 5A illustrates a cross-sectional view of a contact pad of a display substrate according to another embodiment of the utility model.

Fig. 5B illustrates an enlarged plan view of the contact pad of the display substrate of fig. 5A.

Fig. 6 illustrates a cross-sectional view of a display area of a display substrate according to an embodiment of the present invention.

Fig. 7 illustrates a cross-sectional view of a display region of a display substrate according to another embodiment of the present invention.

Fig. 8 illustrates a schematic plan view of a display substrate according to another embodiment of the present invention.

Fig. 9 illustrates a cross-sectional view of one example of a connection contact pad of the display substrate of fig. 8 along a 2-B2.

Fig. 10 illustrates a cross-sectional view of another example of a connection contact pad of the display substrate of fig. 8 along a 2-B2.

Detailed Description

While the present invention will be fully described with reference to the accompanying drawings, which contain preferred embodiments of the present invention, it is to be understood that, prior to the description herein, one of ordinary skill in the art can modify the embodiments described herein while obtaining the technical effects of the present invention. Therefore, it should be understood that the foregoing description is a broad disclosure of those skilled in the art, and is not intended to limit the exemplary embodiments of the utility model described herein.

Furthermore, in the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in schematic form in order to simplify the drawing.

Fig. 1A illustrates a schematic plan view of a display substrate according to an embodiment of the present invention. Fig. 1B illustrates a schematic plan view of a display area of the display substrate of fig. 1A.

As shown in fig. 1A, the display substrate includes a substrate 10, and the substrate 10 includes a display area 11 and a peripheral area surrounding the display area 11, for example, in fig. 1A, the peripheral area includes a peripheral area (also referred to as a bonding area) 12 located on at least one side of the display area 11 and a peripheral area (also referred to as a side area) 13 located on at least another side of the display area. In fig. 1A, bonding area 12 is located on one side of display area 11 in the y-direction, and side areas 13 are located on both sides of display area 11 in the x-direction. A plurality of sub-pixels Pix are provided in the display area 11. The plurality of subpixels Pix may be arranged in the form of an array. In fig. 1A and 1B, x denotes a row direction of the sub-pixel array, and y denotes a column direction of the sub-pixel array. The display region 11 is further provided with a plurality of gate lines G1 to GN and a plurality of data lines D1 to DM, each gate line G1 to GN is connected to at least one row of sub-pixels Pix to supply gate driving signals to the row of sub-pixels Pix, and each data line D1 to DM is connected to at least one column of sub-pixels Pix to supply data signals to the column of sub-pixels Pix. Each subpixel Pix may be turned on under the control of a gate driving signal on a gate line connected thereto, and the turned-on subpixel Pix may emit light under the drive of a data signal on a data line connected thereto.

The gate driving circuits 130 are located in the side regions 13, and in fig. 1A, two gate driving circuits 130 are located in the side regions 13 on two sides of the display region 11. The gate driving circuit 130 is connected to the plurality of subpixels Pix. In fig. 1A and 1B, the gate driving circuit 130 is connected to a plurality of rows of subpixels Pix through a plurality of gate lines G1 to GN to supply gate driving signals to the respective rows of subpixels Pix. As shown in fig. 1A, the gate driving circuit 130 is also connected to various driving control signal lines, such as a first clock signal line CK1 for supplying a first clock signal, a second clock signal line CK2 for supplying a second clock signal, and a start signal line STV for supplying a start signal. The gate driving circuit 130 may include a plurality of cascaded shift registers GOA0 to GOAN, each of the cascaded shift registers GOA0 to GOAN being connected to a corresponding driving control signal line to generate a gate driving signal under the control of the driving control signal and provide the gate driving signal to the sub-pixels Pix of the display region 11.

A plurality of contact pads are arranged in the peripheral area. For example, in fig. 1A, the plurality of contact pads includes a plurality of input contact pads P1 and a plurality of output contact pads P2, each located at bonding region 12. The plurality of output touch pads P2 are located between the plurality of input touch pads P1 and the display area 11. In fig. 1A, a plurality of input contact pads P1 and a plurality of output contact pads P2 are arranged in at least one row along a first direction, which is an extending direction of a side of the display area 11 facing the bonding area 12, i.e., an x direction.

A plurality of output contact pads P2 are electrically connected to the sub-pixels Pix in the display area 11 and the gate driving circuit 130. For example, the plurality of output contact pads P2 may be connected to the sub-pixels Pix and the gate driving circuit 130 in the display region 11 through the plurality of second wires W2, respectively. As shown in fig. 1A, the plurality of output contact pads P2 on the left and right sides are connected to the first clock signal line CK1, the second clock signal line CK2, and the start signal line STV, respectively, through a plurality of second wires W2, thereby being connected to the gate driving circuit 130. The plurality of output contact pads P2 positioned in the middle of fig. 1A are connected to the data lines D1 to DM in the display area 11 through the plurality of second wire lines W2, respectively, and thus connected to the subpixels Pix in the display area 11. In some embodiments, structures such as a Cell Test (CT) circuit, an Electro-Static Discharge (ESD) circuit, a multiplexing circuit, etc. may be disposed in bonding region 12. For example, a unit test circuit may be disposed in a region between the plurality of output contact pads P2 and the display area 11, and the unit test circuit may be connected to a plurality of test signal lines and a plurality of sub-pixels in the display area. For example, a multiplexing circuit may be disposed in a region between the cell test circuit and the plurality of output contact pads P2, and the multiplexing circuit may be connected to at least one output contact pad P2 and the data lines in the display region 11 to multiplex the data signals provided from the output contact pad P2 and then provide the multiplexed data signals to the data lines in the display region 11. Although embodiments of the utility model are not limited in this respect. In some embodiments, at least one of the cell test circuit, the electrostatic protection circuit, the multiplexing circuit, and other auxiliary circuits may be disposed in an area between the input pad P1 and the output pad P2.

When the control chip is connected to the display substrate, the input pad P1 is connected to an input pin of the control chip, and the output pad P2 is connected to an output pin of the control chip. Signals (such as, but not limited to, power signals, control signals, etc.) provided by the flexible circuit board are provided to the control chip through the input contact pad P1, so that the control chip generates driving signals (such as, but not limited to, clock signals, start signals, data signals, etc.). Driving signals generated by the control chip are supplied to the subpixels Pix and/or the gate driving circuit 130 of the display area 11 through the output contact pad P2, for example, data signals generated by the control chip are supplied to the data lines D1 to DM through the output contact pad P2 located at the middle portion, thereby being supplied to the subpixels in the display area 11; the first clock signal, the second clock signal and the start signal STV generated by the control chip are supplied to the first clock signal line CK1, the second clock signal line CK2 and the start signal line STV through the output contact pads P2 at both sides, respectively, to be supplied to the gate driving circuit 130.

Fig. 2A shows a schematic diagram of a cross-section of a contact pad of a display substrate. Fig. 2B shows a scanning electron microscope image of the contact pad of fig. 2A.

As shown in fig. 2A, the contact pad includes conductor layers 210, 220, and 230 sequentially stacked on a substrate base 200. The insulating layer 240 is located between the conductor layers 210 and 220, the inorganic layer 250 is located between the conductor layers 220 and 230, and the gate insulating layer 260 is located between the conductor layer 210 and the substrate 200. The conductor layer 220 is electrically connected to the conductor layer 210 through a via hole in the insulating layer 240, and the conductor layer 230 is electrically connected to the conductor layer 220 through a via hole in the inorganic layer 250. The projection of the conductor layer 210 on the substrate base 200 at least partially overlaps the projection of the inorganic layer 250 on said substrate base 10, the overlapping area being denoted by "OA" in fig. 2A. As shown in fig. 2B, the overlap area OA causes the conductor layer 230 to form a protrusion P in a direction perpendicular to the substrate base 200, resulting in a large metal offset of the third conductor part 230. The metal offset makes the display substrate easy to generate film layer fracture (Crack) in the Bonding process with a control chip (IC). The broken part forms a water vapor invasion channel, and the control chip usually releases the whole metal water vapor in time, so that the reliability IC is stripped, and abnormal display is caused.

The utility model provides a display substrate, wherein a certain distance is arranged between an inorganic layer and a first conductor part in a peripheral area, so that the surface of a contact pad is relatively flat, and the occurrence of film layer breakage is reduced.

Fig. 3 shows a schematic plan view of a contact pad of the display substrate of fig. 1. FIG. 4A shows a cross-sectional view along A1-B1 in FIG. 3. Fig. 4B shows an enlarged view of the area 300 of fig. 3. Fig. 4C shows a scanning electron microscope image corresponding to the cross-sectional view of fig. 4A.

The touch pad shown in fig. 3 may be any one of the input touch pad P1 and the output touch pad P2. As shown in fig. 3 and 4A, the contact pad includes a first conductor portion 310, a second conductor portion 320, and a third conductor portion 330. The first conductor portion 310 is located on the substrate base plate 10, and the second conductor portion 320 is located on a side of the first conductor portion 310 facing away from the substrate base plate 10 and electrically connected to the first conductor portion 310. The third conductor portion 330 is located on a side of the second conductor portion 320 facing away from the substrate base plate 10 and is electrically connected to the second conductor portion 320. Referring to fig. 1A in combination, the first conductor portion 310 of the output contact pad P2 may be connected to the second wire W2 of the bonding region, thereby being electrically connected to the gate driving circuit 130 or at least one of the plurality of sub-pixels in the display region 11. The first conductor portion 310 of the input pad P1 may be connected to a connection pad for connection to an external circuit, as will be described in further detail below. The dimension L1 of the projection of the contact pad onto the base substrate 10 in the first direction (i.e. the x-direction) is in the range of 20 μm to 22 μm, for example may be about 21.5 μm, and the dimension H1 in the second direction (i.e. the y-direction) is in the range of 140 μm to 150 μm, for example may be about 145 μm. In some embodiments, the size of the contact pad may be defined by the size of the third conductor portion 330, which will be described in further detail below.

As shown in fig. 4A, a peripheral-region insulating layer 340 and a peripheral-region inorganic layer 350 are further disposed in the bonding region 12 of the display substrate. The second conductor portion 320 is electrically connected to the first conductor portion 310 through the first via hole V1 provided in the peripheral-region insulating layer 340. The third conductor portions 330 are electrically connected to the second conductor portions 320 through second vias V2 provided in the peripheral region inorganic layer 350.

As shown in fig. 4A, a peripheral region first gate insulating layer 360 may be further disposed in the bonding region 12 of the display substrate. The peripheral region first gate insulating layer 360 is disposed between the first conductor part 310 and the substrate base plate 10.

In some embodiments, the peripheral region insulating layer 340 may include a peripheral region second gate insulating layer and a peripheral region interlayer dielectric layer. The material of each of the peripheral-region first gate insulating layer 360, the peripheral-region second gate insulating layer, and the peripheral-region interlayer dielectric layer may include, but is not limited to, an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride. However, embodiments of the present invention are not limited thereto, and in other embodiments, the material of each of the peripheral region first gate insulating layer 360, the peripheral region second gate insulating layer, and the peripheral region interlayer dielectric layer may include, but is not limited to, an organic insulating material such as polyimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenol resin. The material of the first conductor part 310, the second conductor part 320, and the third conductor part 330 may include a metal material or an alloy material, such as, but not limited to, a metal single layer or a metal multilayer structure formed of molybdenum, aluminum, titanium, and the like.

In some embodiments, the base substrate 10 may include an organic material such as, but not limited to, one or more of a resin-based material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The substrate 10 may be a flexible substrate or a non-flexible substrate.

As shown in fig. 3 and 4A, the projection of the first conductor part 310 on the substrate base plate 10 is located in the projection of the second via hole V2 of the peripheral region inorganic layer 350 on the substrate base plate 10. As shown in fig. 4A, a projected edge of the first conductor portion 310 on the substrate board 10 and a projected edge of the second via V2 on the substrate board 10 have a certain distance D therebetween. In some embodiments, the spacing D is in the range of 1 μm to 2 μm, and may be about 1.5 μm, for example.

As shown in fig. 3 and 4B, a projection of the first via hole V1 in the peripheral-region insulating layer 340 on the substrate base plate 10 has a dimension L5 in the first direction (x direction) in a range of 7 μm to 9 μm, for example, may be about 8 μm. A projection of the first conductor portion 310 on the substrate base plate 10 has a dimension L4 in the first direction in a range of 12 μm to 14 μm, and may be about 13 μm, for example. The dimension L3 of the second via hole V2 in the peripheral region inorganic layer 350 in the first direction projected on the substrate base plate 10 is in the range of 14 μm to 16 μm, and may be about 15.5 μm, for example. As shown in fig. 3 and 4B, the geometric center of the projection of the first conductor part 310 on the substrate board 10 and the geometric center of the projection of the second via V2 on the substrate board 10 may substantially coincide. In the actual manufacturing process of the display substrate, a certain process error may be generated due to process fluctuation, so that the geometric center of the projection of the first conductor part 310 has a certain deviation from the geometric center of the projection of the second via hole V2, where the term "substantially coincide" means that the deviation is allowed. A projection of the second conductor portion 320 on the base substrate 10 has a dimension L2 in the first direction in the range of 19 μm to 21 μm, and may be about 20 μm, for example. A projection of the third conductor portion 330 on the substrate board 10 has a dimension L1 in the first direction in a range of 20 μm to 22 μm, and may be about 21.5 μm, for example. In some embodiments, the projection of the third conductor portion 330 on the substrate base plate 10 has a size in the second direction in the range of 140 μm to 150 μm.

As shown in fig. 3 and 4B, in some embodiments, the distances between the projected edges of the first conductor part 310, the second conductor part 320, the third conductor part 330, the first via V1, and the second via V2 on the substrate base plate 10 in the x direction are consistent with the distances between the projected edges in the y direction. For example, the distances between the projected edge of the first conductor portion 310 and the projected edge of the second via V2 in the x and y directions may be D, and the distances between other conductor portions and other vias may be set to be equal or different in the x and y directions, which is not described herein again.

As shown in fig. 3 and 4C, the edge of the first conductor part 310 has a first surface 311 facing the substrate base plate 10, a second surface 312 facing away from the substrate base plate 10, and a third surface 313 connecting the first surface 311 and the second surface 312. The third surface 313 of the first conductor part 310 has a slope angle θ 2 in a range of 20 degrees to 30 degrees with respect to a plane in which the substrate base plate 10 is located. For example, θ 2 may be in the range of 20 degrees to 25 degrees, and in some embodiments may be about 23 degrees.

The sidewall of the first via V1 in the peripheral-region insulating layer 340 has a slope angle θ 5 in the range of 40 degrees to 50 degrees with respect to the plane in which the substrate base plate 10 is located. For example, θ 5 may be in the range of 45 to 50 degrees, and in some embodiments about 47 degrees.

The edge of the second conductor part 320 has a first surface 321 facing the substrate base plate 10, a second surface 322 facing away from the substrate base plate 10, and a third surface 323 connecting the first surface 321 and the second surface 322, wherein the third surface 323 of the second conductor part 320 has a slope angle θ 3 in a range of 55 degrees to 65 degrees with respect to a plane in which the substrate base plate 10 is located. For example, θ 3 may be in the range of 58 degrees to 62 degrees, and in some embodiments may be about 60 degrees.

The sidewall of the second via V2 in the peripheral region inorganic layer 350 has a slope angle θ 1 in a range of 80 degrees to 90 degrees with respect to the plane of the substrate base plate 10. For example, θ 1 may be in the range of 83 degrees to 87 degrees, and in some embodiments may be about 85 degrees.

The edge of the third conductor part 330 has a first surface 331 facing the substrate base plate 10, a second surface 332 facing away from the substrate base plate 10, and a third surface 333 connecting the first surface 331 and the second surface 332, wherein the third surface 333 of the third conductor part 330 has a slope angle θ 4 in a range of 58 degrees to 67 degrees with respect to a plane in which the substrate base plate 10 is located. For example, θ 4 may be in the range of 60 degrees to 64 degrees, and in some embodiments may be about 62 degrees.

In some embodiments, the slope angle θ 2 is the smallest among the slope angles θ 1, θ 2, θ 3, θ 4, and θ 5, so that a step difference due to the edge of the first conductor part 310 is relatively small in the process, thereby making the contact pad surface relatively flat.

In other embodiments, the first conductor portion 310, the second conductor portion 320, the third conductor portion 330, the first via V1 and the second via V2 may have any angle with respect to the plane of the substrate base 10, and are not limited herein.

Although the projections of the first conductor part 310, the second conductor part 320, the third conductor part 330, the first via V1 and the second via V2 on the substrate 10 are all rectangular in fig. 3, that is, the projection of the contact pad on the substrate is rectangular, the embodiments of the present invention are not limited thereto. The shape of the projection of the contact pad (e.g., at least one of the input contact pad and the output contact pad) on the substrate base plate may be configured into other shapes as needed, such as, but not limited to, a parallelogram, a square, a trapezoid, or other polygons, and the utility model is not limited thereto.

As can be seen from fig. 4C, there is a certain distance between the projected edge of the first conductor part 310 on the substrate base plate 10 and the projected edge of the peripheral region inorganic layer 350 on the substrate base plate 10, which makes the protrusion P' formed by the third conductor part 330 in the direction perpendicular to the substrate base plate 10 much smaller than the protrusion P shown in fig. 2B, so that the metal tolerance of the third conductor part 330 is reduced, and the risk of film layer fracture of the display base plate during bonding is reduced.

Fig. 5A illustrates a cross-sectional view of a contact pad of a display substrate according to another embodiment of the utility model. Fig. 5B illustrates an enlarged plan view of the contact pad of the display substrate of fig. 5A.

The contact pad of fig. 5A is similar to the contact pad of fig. 4A, and includes a substrate 10, and a first gate insulating layer 560, a first conductive layer 510, a peripheral region insulating layer 570, a second conductive portion 520, a peripheral region inorganic layer 550, and a third conductive portion 530 stacked on the substrate 10 in sequence, which may be respectively implemented by the first gate insulating layer 360, the first conductive layer 310, the peripheral region insulating layer 370, the second conductive portion 320, the peripheral region inorganic layer 350, and the third conductive portion 330, and are not described herein again.

The contact pad of fig. 5A is different from the contact pad of fig. 4A at least in that a peripheral region planarization layer 570 is further disposed in the peripheral region of the display substrate. The peripheral-region planarization layer 570 is located on a side of the peripheral-region inorganic layer 550 facing the substrate base plate 10. As shown in fig. 5A and 5B, the peripheral region inorganic layer 550 is in contact with the second conductor portion 520 through the third via hole V3 provided in the peripheral region planarization layer 550.

As shown in fig. 5A and 5B, the peripheral-region planarization layer 570 is disposed between the peripheral-region insulating layer 540 and the peripheral-region inorganic layer 550, and a projection of the peripheral-region planarization layer 570 on the substrate base plate 10 at least partially overlaps a projection of the second conductor portion 520 on the substrate base plate 10. As can be seen in fig. 5A and 5B, the peripheral region planarization layer 570 covers at least the edge of the second conductor portion 520. As can also be seen from fig. 5A and 5B, the projection of the peripheral region planarization layer 570 on the substrate base plate 10 at least partially overlaps the projection of the peripheral region inorganic layer 550 on the substrate base plate 10, and the edge of the projection of the peripheral region planarization layer 570 on the substrate base plate 10 falls within the projection of the peripheral region inorganic layer 550 on the substrate base plate 10, i.e., the peripheral region inorganic layer 550 covers at least the edge of the peripheral region planarization layer 570. This can avoid the problem that the peripheral region planarizing layer 570 absorbs water due to exposure, thereby avoiding the occurrence of IC Peeling.

As shown in fig. 5A and 5B, a distance D' is provided between the projected edge of the first conductor portion 510 on the substrate board 10 and the projected edge of the second via V2 on the substrate board 10. The pitch D 'may be equal to the pitch D shown in fig. 4A, for example, the pitch D' may be in the range of 1 μm to 2 μm.

As shown in fig. 6, the sub-pixels in the display region 11 may include a thin film transistor 1120, a display region first planarization layer 1130, and a light emitting element 1140.

The thin film transistor 1120 includes an active layer 1122 on a substrate 10, a display region first gate insulating layer 1128 on a side of the active layer 1122 away from the substrate 10, a gate electrode 11211 on the display region first gate insulating layer 1128, a display region second gate insulating layer 1129 on the side of the gate electrode 11211 away from the substrate 10, a display region interlayer insulating layer 11210 on the display region second gate insulating layer 1129, and a source electrode 1125 and a drain electrode 1126 on the display region interlayer insulating layer 11210. The gate 11211 may be disposed at the same level as the first conductor connection portion (310, 510) in the bonding region 12. Source 1125 and drain 1126 may be disposed on the same layer as the second conductor portions (320, 520) in bonding region 12. Accordingly, the gate electrode 11211 and the first conductor connection portion (310, 510) may be formed in the same layer in a fabrication process, for example, by a patterning process using the same material layer. Source and

drain electrodes

1125 and 1126 and the second conductor portions (320, 520) in bonding region 12 may be formed in the same layer in a fabrication process, e.g., by a patterning process using the same material layer. The display-area first gate insulating layer 1128 in the display area 11 is disposed in the same layer as the gate insulating layer (360, 560) in the bonding area 12, and the peripheral-area insulating layer (340, 540) in the bonding area 12 is disposed in the same layer as the display-area insulating layer in the display area 11, wherein the display-area insulating layers include the display-area second gate insulating layer 1129 and the display-area interlayer insulating layer 11210 shown in fig. 6. In some embodiments, the peripheral region insulating layer includes a peripheral region interlayer insulating layer disposed on the same layer as the display region interlayer insulating layer 11210, and a peripheral region second gate insulating layer 1129 disposed on the same layer as the display region second gate insulating layer 1129.

In some examples of the above embodiments of the present invention, the active layer 1122 may include a source region 1123 and a drain region 1124, and a channel region between the source region 1123 and the drain region 1124. The display region interlayer insulating layer 11210, the display region second gate insulating layer 1129, and the display region first gate insulating layer 1128 have via holes to expose the source region 1123 and the drain region 1124. Source 1125 and drain 1126 are electrically connected to source 1123 and drain 1124 regions, respectively, by vias. The gate electrode 11211 overlaps a channel region in the active layer 1122 between the source region 1123 and the drain region 1124 in a direction perpendicular to the substrate 10. The display region first planarization layer 1130 is located above the source and

drain electrodes

1125 and 1126, and is used for planarizing the surface of the thin film transistor 1120 on the side away from the substrate. A via 1131 is formed in the display area first planarization layer 1130 to expose the source 1125 or the drain 1126 (case shown). In some embodiments, the material of the active layer 1122 may include polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide). The material of the gate electrode 11211 may include a metal material or an alloy material, such as a metal single layer or a multilayer structure formed by mo, Al, Ti, etc., for example, the multilayer structure is a multi-metal layer stack (e.g., Ti, Al, and Ti three-layer metal stack (Ti/Al/Ti).) and the material of the source electrode 1125 and the drain electrode 1126 may include a metal material or an alloy material, such as a metal single layer or a multilayer structure formed by mo, Al, Ti, etc., for example, the multilayer structure is a multi-metal layer stack (e.g., Ti, Al, and Ti three-layer metal stack (Ti/Al/Ti) — the material of each functional layer is not limited in the embodiments of the present invention.

In some examples of the present invention, as shown in fig. 6, the thin film transistor 1120 may further include a first display metal layer 1127, and the first display area metal layer 1127 is disposed at the same layer as the second conductor portion (320, 520). The first display metal layer 1127 includes the source and

drain electrodes

1125 and 1126 of the thin film transistor described above. The source and

drain electrodes

1125, 1126 are disposed in the same layer as the second conductor portions (320, 520).

In some examples of the utility model, as shown in fig. 6, the light emitting element 1140 is formed on the display area first planarization layer 1130, i.e., the light emitting element 1140 is disposed on the side of the first planarization layer 1130 away from the substrate 10. The light-emitting element 1140 includes a first electrode 1141, a light-emitting layer 1142, and a second electrode 1143. The first electrode 1141 of the light emitting element is electrically connected to the drain electrode 1126 through the via hole 1131 in the display region first planarization layer 1130. A pixel defining layer 1144 is formed on the first electrode 1141, and the pixel defining layer 1144 includes a plurality of openings to define a plurality of pixel units. Each opening exposes a corresponding first electrode 1141. The light emitting layer 1142 is disposed in the plurality of openings of the pixel defining layer 1144, and the second electrode 1143 is disposed on the pixel defining layer 1144 and the light emitting layer 1142, for example, the second electrode 1143 may be disposed in a part or the whole of the display region, so that it may be formed over the whole surface in the manufacturing process.

In some embodiments, the material of the display region first planarization layer 1130 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may also include an organic insulating material such as polyimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenol resin, which is not limited in this embodiment of the present invention.

In some embodiments, the first electrode 1141 may include a reflective layer, and the second electrode 1143 may include a transparent layer or a semi-transparent layer. Thereby, the first electrode 1141 may reflect light emitted from the light emitting layer 1142, and the portion of the light is emitted to the external environment through the second electrode 1143, so that light emitting rate may be provided. When the second electrode 1143 includes the semi-transmissive layer, some of the light reflected by the first electrode 1141 is reflected again by the second electrode 1143, and thus the first electrode 1141 and the second electrode 1143 form a resonance structure, so that light emission efficiency can be improved.

For example, the material of the first electrode 1141 may include at least one transparent conductive oxide material including Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), and the like. In addition, the first electrode 1141 may include a metal having a high reflectivity as a reflective layer, such as silver (Ag).

In some embodiments, for an OLED, the light emitting layer 1142 may include a small molecule organic material or a polymer molecule organic material, may be a fluorescent light emitting material or a phosphorescent light emitting material, may emit red light, green light, blue light, or may emit white light; the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer, as necessary. For QLEDs, the light emitting layer can include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, indium arsenide quantum dots, and the like, with the particle size of the quantum dots being 2-20 nm.

In some embodiments, the second electrode 1143 may include various conductive materials. For example, the second electrode 1143 may include a metal material such as lithium (Li), aluminum (a1), magnesium (Mg), silver (Ag), and the like.

In some embodiments, the material of the pixel defining layer 1144 may include an organic insulating material such as polyimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenol resin, or an inorganic insulating material such as silicon oxide and silicon nitride, which is not limited by the embodiments of the present invention.

In addition, the display substrate further includes a storage capacitor 1160, and the storage capacitor 1160 may include a first pole 1161 and a second pole 1162. A first pole 1161 of the storage capacitor 1160 is disposed between the display region first gate insulating layer 1128 and the display region second gate insulating layer 1129, and a second pole 1162 of the storage capacitor 1160 is disposed between the display region second gate insulating layer 1129 and the display region interlayer insulating layer 11210. The first and

second poles

1161 and 1162 are stacked to at least partially overlap in a direction perpendicular to the substrate base plate 10. The first and

second poles

1161 and 1162 form a storage capacitor using the display region second gate insulating layer 1129 as a dielectric material. The first pole 1161 is disposed on the same layer as the gate 11211 in the tft 1120 and the wire 1220 in the bonding region 12. Also, as noted above, in variations of the above example, the first and second poles of the storage capacitor 1160 may also be located in other layers, resulting in a different structure of the sub-pixel.

In another example, as a modification of the example shown in fig. 6, the first pole of the storage capacitor is still provided in the same layer as the gate electrode 11211, and the second pole of the storage capacitor is provided in the same layer as the source and

drain electrodes

1125 and 1126 in the thin film transistor (i.e., also in the first display metal layer 1127), whereby the first and second poles of the storage capacitor form a storage capacitor using the stack of the display-area second gate insulating layer 1129 and the display-area interlayer insulating layer 11210 as a dielectric material.

In yet another example, as a variation of the example shown in fig. 6, the first pole of the storage capacitor is no longer disposed at the same level as the gate electrode 11211 but is located between the display region second gate insulating layer 1129 and the display region interlayer insulating layer 11210, and the second pole of the storage capacitor is disposed at the same level as the source and

drain electrodes

1125 and 1126 in the thin film transistor (i.e., also in the first display metal layer 1127), whereby the first and second poles of the storage capacitor form a storage capacitor using the display region interlayer insulating layer 11210 as a dielectric material.

In some examples of the utility model, as shown in fig. 6, the display substrate may further include an encapsulation layer 1150 disposed on the light emitting element 1140. The encapsulation layer 1150 seals the light emitting element 1140, so that deterioration of the light emitting element 1140 caused by moisture and/or oxygen included in the environment may be reduced or prevented. The encapsulation layer 1150 may have a single-layer structure or a composite-layer structure including a structure in which inorganic layers and organic layers are stacked, for example, the encapsulation layer 1150 may include a first inorganic encapsulation layer 1151, a first organic encapsulation layer 1152, and a second inorganic encapsulation layer 1153, which are sequentially disposed. Encapsulation layer 1150 may extend to bonding area 12, which in the above example does not cover the contact pads.

For example, the material of the encapsulation layer may include an insulating material such as silicon nitride, silicon oxide, silicon oxynitride, or polymer resin. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high compactness and can prevent invasion of water, oxygen, and the like; the organic encapsulation layer may be made of a polymer material containing a desiccant, a polymer material capable of blocking moisture, or the like, such as a polymer resin, to planarize the surface of the display substrate, and may relieve stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and may further include a water-absorbing material such as a desiccant to absorb substances such as water, oxygen, and the like penetrating inside.

In some examples of the utility model, as shown in fig. 6, the display base plate may further include a display area blocking layer 1171 located on a side of the encapsulation layer 1150 away from the substrate base plate 10, the first touch electrode layer 1172 located on a side of the display area blocking layer 1171 away from the substrate base plate 10, the touch insulating layer 1174 located on a side of the first touch electrode layer 1172 away from the substrate base plate 10 and covering the first touch electrode layer 1172, and the second touch electrode layer 1173 located on a side of the touch insulating layer 1174 away from the substrate base plate 10. In fig. 6, the second touch electrode layer 1173 is electrically connected to the first touch electrode layer 1172 through a via hole in the touch insulating layer 1174, although the embodiment of the utility model is not limited thereto, and the first touch electrode layer 1172 and the second touch electrode layer 1173 may be arranged in other patterns as needed. The first touch electrode layer 1172 and the second touch electrode layer 1173 can be used to implement a capacitive type touch structure, which is a self-capacitive type or a mutual capacitive type.

The third conductor portion (330, 530) in the bonding region 12 may be disposed in the same layer as the second touch electrode layer 1173 in the display region, and the inorganic layer (350, 550) in the peripheral region in the bonding region 12 may be disposed in the same layer as the touch insulating layer 1174 in the display region.

In some embodiments, the third conductor portion (330, 530) may be disposed in the same layer as the first touch electrode layer 1172 of the display region, for example, formed by a patterning process using the same material layer, thereby simplifying the manufacturing process.

In some embodiments, the third conductor portion (330, 530) may include a third conductor first sub-portion and a third conductor second sub-portion sequentially stacked in a direction perpendicular to the substrate base plate 10, the third conductor first sub-portion being disposed in a same layer as the first touch electrode layer 1172, the third conductor second sub-portion being disposed in a same layer as the second touch electrode layer 1173.

Fig. 7 illustrates a cross-sectional view of a display region of a display substrate according to another embodiment of the present invention. The display region structure of fig. 7 is different from the display region structure of fig. 6 at least in that the display substrate further includes a transfer electrode 1180, a display region second planarization layer 1190, and a display region passivation layer 11110. For the sake of simplifying the description, the following description will mainly explain the difference in detail.

The transfer electrode 1180 is disposed on the display area first planarization layer 1130. The through electrode 1180 is electrically connected to the drain electrode 1126 through the via 1131, the through electrode 1180 may avoid forming a through hole with an excessively large diameter directly in the display area first planarization layer 1130 and the display area second planarization layer 1190, so as to improve the quality of the through hole electrical connection, and the through electrode 1180 may also be formed with an equivalent layer of other signal lines (such as a power line, etc.), so as not to increase the number of process steps.

In some embodiments, the contact pad in bonding region 12 may further include a conductor structure in addition to the first conductor portion, the second conductor portion, and the third conductor portion, which is located on a side of the second conductor portion facing away from the substrate base and electrically connected to the second conductor portion. The via electrode 1180 may be disposed in the same layer as the conductive structure of the contact pad, and therefore, the via electrode 1180 and the conductive structure may be formed in the same layer in a manufacturing process, for example, by a patterning process using the same material layer, thereby simplifying the manufacturing process.

In some embodiments, the second conductor portion (320, 520) may be disposed on the same layer as the via electrode 1180, and thus, the via electrode 1180 and the second conductor portion (320, 520) may be formed on the same layer in a manufacturing process, for example, by a patterning process using the same material layer, thereby simplifying the manufacturing process.

In some embodiments, the second conductor portion (320, 520) may include a second conductor first sub-portion and a second conductor second sub-portion sequentially stacked in a direction perpendicular to the substrate base plate 10, the second conductor first sub-portion being disposed at the same layer as at least one of the source and

drain electrodes

1125 and 1126, the second conductor second sub-portion being disposed at the same layer as the transit electrode 1180.

For example, the material of the transfer electrode 1180 may include a metal material or an alloy material, such as a metal single layer or a metal multilayer structure formed by molybdenum, aluminum, titanium, and the like.

In some examples of the utility model, as shown in fig. 7, a second planarization layer 1190 is disposed on a side of the via electrode 1180 away from the substrate 10 to provide a planarized surface on the side of the via electrode 1180 away from the substrate 10. A via 1191 is formed in the display region second planarization layer 1190. The first electrode 1141 of the light emitting device is electrically connected to the transfer electrode 1180 through the via 1191 in the second planarization layer 1190 in the display region.

The display region passivation layer 11110 is positioned between the thin film transistor 1120 and the display region first planarization layer 1130. A via 11111 may be disposed in the display region passivation layer 11110. The display region passivation layer 11110 may protect the source and drain electrodes of the thin film transistor from moisture. In some embodiments, the display region passivation layer 11110 may be thinned, or the display region passivation layer 11110 may not be provided.

Fig. 8 illustrates a schematic plan view of a display substrate according to another embodiment of the present invention. The display substrate of fig. 8 is similar to the display substrate of fig. 1A, except that at least the display substrate of fig. 8 further includes a plurality of connection contact pads P3. For the sake of simplifying the description, the following description will mainly explain the difference in detail.

As shown in FIG. 8, a plurality of connection pads P3 are located within bonding area 12 on a side of the plurality of input pads P1 facing away from the display area 11. The first conductor portion of input contact pad P1 is electrically connected to the connection contact pad P3 by a first lead W1 disposed at bonding area 12. A plurality of connection contact pads P3 may be used for connection to an external circuit, for example, through a flexible circuit board.

Fig. 9 shows a cross-sectional view along a2-B2 of one example of the connection contact pad P3 of the display substrate of fig. 8. The landing pad structure of fig. 9 is suitable for use in the display substrate of any of the embodiments described above.

As shown in fig. 9, the connection pad P3 includes a fourth conductor portion 920 and a fifth conductor portion 940. The fourth conductor portion 920 is located on the base substrate 10 and is provided in the same layer as the second conductor portions (320, 520). The fifth conductor part 940 is located on a side of the fourth conductor part 920 facing away from the substrate base plate 10, and the fifth conductor part 940 may be disposed in the same layer as the third conductor part (330, 530). The fifth conductor part 940 is electrically connected to the fourth conductor part 920 through the fourth via hole V4 provided in the peripheral region inorganic layer 930. The peripheral region inorganic layer 930 may be disposed on the same layer as the touch insulating layer 1174 of the display region. The contact pad insulating portion 950 is located on a side of the peripheral region inorganic layer 930 facing the substrate base plate 10, and covers an edge of the fourth conductor portion 920. In some embodiments, the projection of the fourth conductor portion 920 on the substrate base plate 10 may be rectangular, and the projection of the contact pad insulating portion 950 on the substrate base plate 10 may surround four sides of the rectangular projection in a stripe shape, and partially overlap with the edge of the rectangular projection. A portion of the contact pad insulating portion 950 covers the fourth conductor portion 920 and another portion contacts the peripheral-region insulating layer 910, and the sum D1 of the sizes of the two portions in the first direction (x direction) (i.e., the width of the stripe) is in a range of 2 μm to 5 μm, for example, may be in a range of 2 μm to 3 μm.

In this embodiment, the contact pad insulating portion 950 is disposed on the same layer as the peripheral region planarization layer, for example, the contact pad insulating portion 950 can be obtained by performing a patterning process on the peripheral region planarization layer. The peripheral region inorganic layer 930 is in contact with the fourth conductor portion 920 through a fifth via hole V5 provided in the peripheral region planarization layer. Since most of the peripheral-region planarization layer around the fourth conductor portion 920 is removed, the peripheral-region inorganic layer 930 is at least partially in direct contact with the peripheral-region insulating layer 910. The design can eliminate the rainbow texture phenomenon generated by peeling off the film layer. Further, since the contact pad insulating portion 950 is provided at the edge of the fourth conductor portion 920, it is possible to prevent generation of dark spots due to precipitation of Ag after the anode layer is etched to the side of the fourth conductor portion 920.

Fig. 10 shows a schematic view of another example of a connection contact pad of the display substrate of fig. 8 in a cross-section along a 2-B2. The landing pad structure of fig. 10 is suitable for use in the display substrate of any of the embodiments described above. The connector contact pad of fig. 10 is similar to that of fig. 9, except at least that the connector contact pad P3 shown in fig. 10 further includes a sixth conductor portion 1060 and a contact pad insulating portion 1070. For simplicity of explanation, the following description will mainly describe the difference in detail.

As shown in fig. 10, the sixth conductor portion 1060 is located on a side of the fourth conductor portion 1020 facing away from the substrate base plate 10. The contact pad insulating portion 1070 is located on a side of the peripheral region inorganic layer 1030 facing the substrate base plate 10, and covers an edge of the sixth conductor portion 1060. The sixth conductor portion 1060 may be provided in the same layer as the second touch electrode layer 1173.

A peripheral region passivation layer 1050 is also disposed in the bonding region 12 of the display substrate of fig. 10. The peripheral region passivation layer 1050 is located on the side of the sixth conductor portion 1060 facing the substrate base plate 10. The sixth conductor portion 1060 is electrically connected to the fourth conductor portion 1020 through a sixth via hole V6 provided in the peripheral region passivation layer 1050, and the third conductor portion 1040 is in contact with the sixth conductor portion 1060 through a seventh via hole V7 provided in the peripheral region inorganic layer 1030.

The passivation layer 1050 in the peripheral region may be disposed in the same layer as the passivation layer 11110 in the display region. Therefore, the passivation layer 1050 in the peripheral region and the passivation layer 11110 in the display region may be formed in the same layer in the manufacturing process, for example, by a patterning process using the same material layer.

The projection of the sixth conductor portion 1060 on the substrate base plate 10 may be rectangular, and the projection of the contact pad insulating portion 1070 on the substrate base plate 10 may surround four sides of the rectangular projection in a stripe shape, partially overlapping with the edge of the rectangular projection. A portion of the contact pad insulating portion 1070 covers the sixth conductor portion 1060 and another portion contacts the peripheral region passivation layer 1050, and the sum D2 of the sizes of the two portions in the first direction (x direction) (i.e., the width of the strip) is in a range of 2 μm to 5 μm, for example, may be in a range of 2 μm to 3 μm.

In this embodiment, the pad insulating portion 1070 is disposed on the same layer as the peripheral region planarization layer, for example, the pad insulating portion 1070 may be obtained by performing a patterning process on the peripheral region planarization layer. Since most of the peripheral region planarization layer around the sixth conductor portions 1060 is removed, the peripheral region inorganic layer 1030 is at least partially in direct contact with the peripheral region passivation layer 1050. This design eliminates the rainbow effect caused by the peeling of the film, and prevents the generation of dark spots due to the deposition of Ag after the side etching of the anode layer to the fourth conductor portion 920 because the contact pad insulating portion 1070 is provided at the edge of the fourth conductor portion 920.

The utility model also provides a display device which can comprise the display substrate of any one of the embodiments.

For example, in some embodiments, the display device may further include a flexible circuit board and a control chip. For example, a flexible circuit board is bonded to a bonding area of the display substrate, and the control chip is mounted on the flexible circuit board, thereby being electrically connected to the display area; alternatively, the control chip is directly bonded to the bonding area, thereby being electrically connected to the display area.

For example, the control chip may be a central processing unit, a digital signal processor, a system on a chip (SoC), and the like. For example, the control chip may further include a memory, a power module, and the like, and implement power supply and signal input and output functions through additionally provided wires, signal lines, and the like. For example, the control chip may also include hardware circuitry, computer executable code, and the like. The hardware circuits may include conventional Very Large Scale Integration (VLSI) circuits or gate arrays and off-the-shelf semiconductors such as logic chips, transistors, or other discrete components; the hardware circuitry may also include field programmable gate arrays, programmable array logic, programmable logic devices, or the like.

For example, the display device provided by at least one embodiment of the present invention may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.

It will be appreciated by those skilled in the art that the embodiments described above are exemplary and can be modified by those skilled in the art, and that the structures described in the various embodiments can be freely combined without conflict in structure or principle.

Having described preferred embodiments of the present invention in detail, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope and spirit of the appended claims, and the utility model is not to be limited to the exemplary embodiments set forth herein.

Claims

1. A display substrate, comprising:

a plurality of sub-pixels located in the display area and arranged in an array;

2. The display substrate of claim 1, further comprising:

3. The display substrate of claim 1, wherein the plurality of contact pads comprises:

a plurality of input contact pads arranged in a peripheral region on one side of the display region along a first direction, the first direction being a row direction of the array of the plurality of sub-pixels;

a plurality of output contact pads between the plurality of input contact pads and the display area and arranged along the first direction.

4. The display substrate of claim 3, further comprising:

5. The display substrate of claim 4, wherein the connection contact pad comprises:

6. The display substrate according to claim 5, further comprising a peripheral region planarization layer, wherein the peripheral region inorganic layer is in contact with the fourth conductor portion through a fifth via disposed in the peripheral region planarization layer, and wherein the contact pad insulating portion is disposed in the same layer as the peripheral region planarization layer.

7. The display substrate of claim 1, wherein a pitch between a projected edge of the first conductor portion on the substrate base and a projected edge of the second via on the substrate base is in a range of 1 μ ι η to 2 μ ι η.

8. The display substrate according to claim 7, wherein a geometric center of a projection of the first conductor portion on the substrate base substantially coincides with a geometric center of a projection of the second via on the substrate base, a dimension of the projection of the first conductor portion on the substrate base in a first direction is in a range of 12 μm to 14 μm, a dimension of the projection of the second via on the substrate base in the first direction is in a range of 14 μm to 16 μm, and the first direction is a row direction of the array of the plurality of sub-pixels.

9. The display substrate of claim 2, wherein a projection of the third via on the substrate base has a dimension in the first direction in a range of 16 μm to 20 μm.

10. The display substrate of claim 1, wherein a projection of the first via on the substrate base has a dimension in a first direction in a range of 7 μ ι η to 9 μ ι η.

11. The display substrate of claim 1,

the side wall of the second through hole in the inorganic layer in the peripheral area has a gradient angle theta 1 relative to the plane where the substrate base plate is located;

wherein theta 2 < theta 1.

12. The display substrate of claim 11, wherein the slope angle θ 1 is in a range of 80 degrees to 90 degrees and the slope angle θ 2 is in a range of 20 degrees to 30 degrees.

13. The display substrate of claim 1, wherein the edge of the second conductor portion has a first surface facing the substrate base, a second surface facing away from the substrate base, and a third surface connecting the first surface and the second surface, the third surface of the second conductor portion having a slope angle θ 3 with respect to a plane in which the substrate base is located;

wherein theta 5 is more than theta 3 and less than theta 4.

14. The display substrate of claim 13, wherein the bevel angle θ 3 is in a range of 55 degrees to 65 degrees, the bevel angle θ 4 is in a range of 58 degrees to 67 degrees, and the bevel angle θ 5 is in a range of 40 degrees to 50 degrees.

15. The display substrate of any one of claims 1 to 14, wherein at least one of the plurality of sub-pixels comprises a thin film transistor comprising a gate, a source, and a drain, wherein the first conductor portion of the plurality of contact pads is disposed on a same layer as the gate, and wherein the second conductor portion is disposed on a same layer as the source and the drain.

16. The display substrate according to claim 15, further comprising a light emitting element, an encapsulation layer, a first touch electrode layer, a second touch electrode layer and a touch insulating layer in a display region, wherein the light emitting element is located on a side of the thin film transistor facing away from the substrate, the encapsulation layer is located on a side of the light emitting element facing away from the substrate, the first touch electrode layer is located on a side of the encapsulation layer facing away from the substrate, the touch insulating layer is located on a side of the first touch electrode layer facing away from the substrate and covers the first touch electrode layer, and the second touch electrode layer is located on a side of the touch insulating layer facing away from the substrate;

17. The display substrate according to claim 15, wherein at least one of the plurality of sub-pixels further comprises a display region interlayer insulating layer between the gate electrode and the source and drain electrodes, a display region first gate insulating layer on a side of the display region interlayer insulating layer facing the substrate, and a display region second gate insulating layer between the display region interlayer insulating layer and the display region first gate insulating layer;

18. The display substrate according to any one of claims 1 to 14, wherein at least one of the plurality of sub-pixels comprises a thin film transistor and a via electrode, the thin film transistor comprises a gate electrode, a source electrode and a drain electrode, the via electrode is electrically connected to one of the source electrode and the drain electrode, and the second conductor portion is disposed in the same layer as at least one of the source electrode, the drain electrode and the via electrode.

19. A display device comprising the display substrate according to any one of claims 1 to 18.