CN215342600U - Image sensor with a plurality of pixels - Google Patents

Abstract

The utility model discloses an image sensor, comprising a plurality of pixel units formed in a semiconductor substrate, each pixel unit comprising: the transmission transistor is connected with the photosensitive area and the floating diffusion area and used for transferring an electric signal of the photosensitive area to the floating diffusion area; the conducting layer is used for conducting and connecting the grid electrode of the source electrode following transistor with the floating diffusion area, and the source electrode following transistor is used for amplifying and outputting an electric signal of the floating diffusion area; the conductive column is connected with the transistor in the pixel unit and the first metal layer, the conductive column and the first metal layer are located on different layers from the conductive layer, and the thickness of the conductive layer is smaller than that of the conductive column. The grid electrode of the source electrode following transistor is in conductive connection with the floating diffusion area through the conductive layer, so that parasitic capacitance formed by the floating diffusion area and the first metal layer is reduced, and conversion gain of the pixel circuit is improved.

Description

Image sensor with a plurality of pixels

Technical Field

The utility model relates to the technical field of image sensors, in particular to an image sensor.

Background

An image sensor refers to a device that converts an optical signal into an electrical signal, and image sensor chips generally used in large-scale commercial applications include two major types, a Charge Coupled Device (CCD) and a Complementary Metal Oxide Semiconductor (CMOS) image sensor chip. Compared with the traditional CCD sensor, the CMOS image sensor has the characteristics of low power consumption, low cost, compatibility with the CMOS process and the like, so that the CMOS image sensor is more and more widely applied. CMOS image sensors are now used not only in the field of consumer electronics, such as digital compact cameras (DSCs), cell phone cameras, video cameras and Digital Single Lens Reflex (DSLR), but also in the fields of automotive electronics, surveillance, biotechnology and medicine.

The pixel unit of the CMOS image sensor is a core device for realizing sensitization of the image sensor. The most common pixel cell is an active pixel structure comprising one photodiode and a plurality of transistors. The photodiode in these devices is a photosensitive unit to realize light collection and photoelectric conversion, and the other MOS transistors are control units to mainly realize the control of the selection, reset, signal amplification and readout of the photodiode.

The CMOS image sensor can be divided into a front-illuminated image sensor in which incident light enters the photodiode from a side close to the circuit connection layer and a back-illuminated image sensor in which incident light enters the photodiode from a side far from the circuit connection layer, according to the difference in the path of the incident light entering the photodiode.

In the design of a pixel circuit of a CMOS image sensor, a photodiode is usually adopted to convert an optical signal containing image information into an electrical signal through a photoelectric effect, charges are transferred to a floating diffusion region (FD) through a transfer Transistor (TX), and then transferred from the floating diffusion region (FD) to a source follower transistor (SF), the conversion gain of the pixel circuit is reduced when the capacitance value of the floating diffusion region is large, and the connection process of the floating diffusion region (FD) and the source follower transistor (SF) is complicated, and processes such as depositing a dielectric layer, etching a contact hole, preparing a conductive post covering the contact hole, and connecting the conductive post with a first metal layer (M1) are required, and the first metal layer also forms a parasitic capacitance with the floating diffusion region, thereby reducing the conversion gain of the pixel circuit. In the conventional CMOS image sensor, each pixel needs to be provided with a corresponding floating diffusion region (FD) and source follower transistor (SF), resulting in a low aperture ratio of the pixel.

SUMMERY OF THE UTILITY MODEL

In order to overcome the disadvantages and shortcomings of the prior art, an object of the present invention is to provide an image sensor to solve the problem of low conversion gain of the pixel circuit of the image sensor in the prior art.

The purpose of the utility model is realized by the following technical scheme:

the present invention provides an image sensor, comprising:

a plurality of pixel cells formed in a semiconductor substrate, each of the pixel cells comprising: the photosensitive area is used for converting optical signals containing image information into electric signals through a photoelectric effect in the exposure process; the transmission transistor is connected with the photosensitive area and the floating diffusion area and is used for transferring the electric signal of the photosensitive area to the floating diffusion area; the source electrode following transistor is used for amplifying and outputting an electric signal of the floating diffusion region;

a conductive layer conductively connecting a gate of the source follower transistor with the floating diffusion region;

the conductive column is connected with the transistor in the pixel unit and the first metal layer, the thickness of the conductive layer is smaller than that of the conductive column, and the upper surface of the conductive layer is lower than that of the conductive column.

Further, the projection of the gate of the source follower transistor on the semiconductor substrate and the floating diffusion region are mutually staggered.

Furthermore, an isolation structure is arranged between the source electrode following transistor and the floating diffusion region, and the conducting layer continuously covers the grid electrode of the source electrode following transistor, the isolation structure and the floating diffusion region.

Further, an insulating layer is further disposed on the semiconductor substrate, the insulating layer is provided with contact openings corresponding to the gate of the transmission transistor, the gate of the source follower transistor, and the floating diffusion region, the conductive pillar is electrically connected based on the contact openings corresponding to the gate of the transmission transistor, and the conductive layer is electrically connected based on the gate of the source follower transistor and the contact openings corresponding to the floating diffusion region.

Further, the source follower transistor and the floating diffusion region are each exposed through one of the contact openings with a portion of the insulating layer between the conductive layer and the semiconductor substrate; or the source follower transistor and the floating diffusion region are exposed together through one of the contact openings.

Further, the projection of the first metal layer on the semiconductor substrate has an overlapping region with the conductive layer.

Furthermore, two adjacent pixel units share the same floating diffusion region, and each floating diffusion region is electrically connected with the gates of the transfer transistors of the two adjacent pixel units.

Further, the gate of each source follower transistor is electrically connected to two floating diffusion regions.

Furthermore, the image sensor also comprises a reset transistor and a selection transistor, wherein the reset transistor is arranged between the two pixel units, and two adjacent pixel units in the same column are symmetrical along the reset transistor; the selection transistor is arranged between the two pixel units, and two adjacent pixel units in the same row are symmetrical along the selection transistor.

Further, the thickness of the conductive layer is between 50 and 1500 angstroms; and/or the thickness of the conductive post is between 2000 and 6000 angstroms.

The utility model has the beneficial effects that: the grid electrode of the source electrode following transistor is in conductive connection with the floating diffusion area through the conductive layer, so that parasitic capacitance formed by the floating diffusion area and the metal layer is reduced, and conversion gain of the pixel circuit is improved; and moreover, a conductive column does not need to be manufactured at the position of the source electrode following transistor and the floating diffusion region, so that the manufacturing process is simplified, and mass production is easier to realize.

Drawings

FIG. 1 is a circuit diagram of a pixel of an image sensor according to a first embodiment of the utility model;

FIG. 2 is a schematic plan view of an image sensor according to one embodiment of the present invention;

FIG. 3 is a schematic cross-sectional view of an image sensor according to an embodiment of the present invention;

FIG. 4 is a circuit diagram of a pixel of an image sensor according to a second embodiment of the present invention;

FIG. 5 is a schematic plan view of an image sensor according to a second embodiment of the present invention;

FIG. 6 is a schematic cross-sectional view of an image sensor according to a second embodiment of the present invention;

FIG. 7 is a schematic cross-sectional view of an image sensor according to a third embodiment of the present invention;

fig. 8a-8d are flow charts of the structure of the method for fabricating the image sensor of the present invention.

Detailed Description

To further illustrate the technical means and effects of the present invention for achieving the predetermined purpose of the utility model, the following detailed description of the embodiments, structures, features and effects of the image sensor according to the present invention with reference to the accompanying drawings and preferred embodiments is as follows:

[ example one ]

Fig. 1 is a pixel circuit diagram of an image sensor according to a first embodiment of the present invention, fig. 2 is a schematic plan view of the image sensor according to the first embodiment of the present invention, and fig. 3 is a schematic cross-sectional structure diagram of the image sensor according to the first embodiment of the present invention.

As shown in fig. 1 to 3, an image sensor according to an embodiment of the present invention includes a photosensitive region, a transfer transistor TX, a source follower transistor SF, a reset transistor RST and a row select transistor RS. The photosensitive area is used for converting an optical signal containing image information into an electrical signal through a photoelectric effect in an exposure process, and the photosensitive area can be provided with a photodiode PD (photo diode), or can be other photoelectric conversion elements to realize the functions; the transfer transistor TX is used to transfer an electrical signal of the photosensitive region to the floating diffusion region FD; the source follower transistor SF is used for amplifying and outputting an electric signal of the floating diffusion region FD; the reset transistor RST resets the voltage of the floating diffusion area FD according to a reset control signal; the selection transistor RS is used to selectively output the signal amplified by the source follower transistor SF to a column line (pioout).

The image sensor has a plurality of pixel units formed on a semiconductor substrate, and the plurality of pixel units are distributed in an array. Each pixel unit includes a photosensitive region (including a photodiode PD for example), a transfer transistor TX, a source follower transistor SF, a conductive layer 10, a conductive pillar CT, and a first metal layer M1.

The conductive layer 10 is a conductive film covering a semiconductor substrate, and the conductive layer 10 electrically connects the gate of the source follower transistor SF to the floating diffusion FD. In addition, in an example, the gate of the transmission transistor TX is electrically connected to the first metal layer M1 through the conductive pillar CT, the conductive pillar CT and the first metal layer M1 are both located at different layers from the conductive layer 10, the thickness of the conductive layer 10 is smaller than that of the conductive pillar CT, and the upper surface of the conductive layer is lower than that of the conductive pillar CT, so that the conductive layer 10 and the first metal layer M1 are located at different layers and do not contact with the first metal layer M1.

It should be noted that the first metal layer M1 is a metal layer electrically leading out a transistor in a pixel region in the image sensor, for example, the first metal layer M1 may implement a transfer transistor TX, a reset transistor RST, a gain control transistor DCG, a row selection transistor RS, and the like. Of course, in other examples, the image sensor may further include a second metal layer M2, a third metal layer M3, a fourth metal layer M4, and the like arranged from bottom to top, so that transistors and the like of the pixel region that need to be electrically led out are electrically led out through different metal layers (e.g., the first to fourth metal layers M1-M4).

In one example, the thickness of the conductive layer 10 is between 50-1500 angstroms, and may be, for example, 80 angstroms, 100 angstroms, 500 angstroms, 600 angstroms, 800 angstroms, 1000 angstroms, or the like. In addition, the thickness of the conductive pillar CT may be between 2000 and 6000 angstroms, for example, 2500 angstroms, 3000 angstroms or 5000 angstroms may be selected. The conductive layer 10, the conductive pillar CT and the first metal layer M1 are respectively manufactured by different processes, and the conductive layer 10 may be made of polysilicon, tungsten (W), copper (Cu), tantalum (Ta), aluminum (Al), titanium (Ti), or the like. The grid electrode of the source electrode following transistor SF is directly in conductive connection with the floating diffusion region FD through the conductive layer 10, parasitic capacitance formed by the floating diffusion region and the metal layer is reduced, conversion gain of the pixel circuit is improved, a conductive column does not need to be manufactured at the positions of the source electrode following transistor and the floating diffusion region, the manufacturing process is simplified, and mass production is easier to achieve.

In the present embodiment, the projection of the gate of the source follower transistor SF on the semiconductor substrate and the floating diffusion region FD are offset from each other, that is, there is no portion where the source follower transistor SF and the floating diffusion region FD overlap with each other in the vertical direction. An isolation structure 30 is provided between the source follower transistor SF and the floating diffusion region FD, and the conductive layer 10 continuously covers the gate of the source follower transistor SF, the isolation structure 30 and the floating diffusion region FD.

In one example, the conductive layer 10 covers the gate of the source follower transistor SF and the floating diffusion region FD between 1/4-2/3 of the gate dimension of the source follower transistor SF, and the width w of the underlying isolation structure 30 is 5-200nm, such as 10nm, 60nm, 100nm, 150 nm. For example, the dimension d1 for the conductive layer 10 to extend over the gate of the source follower transistor SF may be 1/3 or 1/2 of the gate dimension d of the source follower transistor SF; a dimension s1 of the conductive layer 10 extending over the gate of the floating diffusion region FD may be 1/3 or 1/2 of the dimension s of the floating diffusion region FD. In addition, when the gate of the source follower transistor SF and the floating diffusion FD are further formed with the insulating layer 20, both ends of the conductive layer 10 may further continue to extend to cover a portion of the insulating layer at the corresponding position, as shown in fig. 3.

Further, an insulating layer 20 is further disposed on the semiconductor substrate, the insulating layer 20 is provided with contact openings corresponding to the gate of the transfer transistor TX, the gate of the source follower transistor SF, and the floating diffusion region FD, and the gate of the transfer transistor TX, the gate of the source follower transistor SF, and the floating diffusion region FD are exposed from the contact openings. The conductive layer 10 fills the contact openings at the gate of the source follower transistor SF and the floating diffusion region FD, and electrically connects the gate of the source follower transistor SF and the floating diffusion region FD, that is, the conductive layer 10 is electrically connected based on the gate of the source follower transistor SF and the corresponding contact opening of the floating diffusion region FD. The conductive pillars CT fill the contact openings at the gate of the transfer transistor TX and electrically connect the gate of the transfer transistor TX with the first metal layer M1, i.e., the conductive pillars CT are electrically connected based on the corresponding contact openings at the gate of the transfer transistor TX.

In this embodiment, as shown in fig. 3. The source follower transistor SF and the floating diffusion region FD are exposed together through one contact opening, i.e., the insulating layer 20 has one contact opening etched at the source follower transistor SF and the floating diffusion region FD, the source follower transistor SF and the floating diffusion region FD are simultaneously exposed through one contact opening, and the insulating layer 20 between the source follower transistor SF and the floating diffusion region FD is also etched away. Of course, in other embodiments, referring to fig. 7, the source follower transistor SF and the floating diffusion region FD are each exposed through one contact opening, i.e., the insulating layer 20 etches one contact opening at the source follower transistor SF and the floating diffusion region FD, respectively, and the insulating layer 20 between the source follower transistor SF and the floating diffusion region FD remains, i.e., the region between the conductive layer 10 and the semiconductor substrate has a portion of the insulating layer 20.

In this embodiment, a projection of a part of the first metal layer M1 on the semiconductor substrate overlaps the conductive layer 10, i.e. a region above the conductive layer 10 may have a part of the first metal layer M1, so that the first metal layer M1 itself can be used for wiring or other functions.

In one example, the metal corresponding to the contact hole CT for electrically leading out the transfer transistor TX extends above the conductive layer 10, as shown in fig. 3. In another example, the first metal layer M1 electrically corresponding to other transistors and realizing the electrical lead-out of the transistors may extend continuously to the upper side of the conductive layer 10. Although the portion of the first metal layer M1 above the source follower transistor SF and the floating diffusion region FD does not electrically connect the source follower transistor SF and the floating diffusion region FD, the auxiliary metal portion may be continuously wired and used to connect other elements or perform other functions, so that the utilization rate of the first metal layer M1 may be increased to reduce the area of the first metal layer M1, and the layout of the image sensor may be more compact.

In the embodiment, as shown in fig. 2, the photodiode PD of each photosensitive region is connected to one transfer transistor TX, each floating diffusion FD is electrically connected to the gate of one transfer transistor TX, and the gate of each source follower transistor SF is electrically connected to one floating diffusion FD. Of course, in other embodiments, each floating diffusion region FD may be electrically connected to the gates of two transfer transistors TX, and the gate of each source follower transistor SF may be electrically connected to one floating diffusion region FD, that is, two pixel units share one floating diffusion region FD. Alternatively, referring to fig. 5, each floating diffusion region FD is electrically connected to the gates of two transfer transistors TX, and the gate of each source follower transistor SF is electrically connected to two floating diffusion regions FD, that is, two pixel units share one floating diffusion region FD, and four pixel units share one source follower transistor SF. Sharing one floating diffusion region FD or one source follower transistor SF with a plurality of pixel units makes the pixel circuit more compact, and improves the aperture ratio and conversion gain of the pixel units. In the structure of the embodiment, the source follower transistor SF and the floating diffusion region FD are close to each other, especially in a shared structure, such as a four-pixel shared structure, the interconnection between the source follower transistor SF and the floating diffusion region FD is easily realized by adopting the improved method of the utility model, the process is simple and convenient, the cost is low, in other structures, such as the source follower transistor SF and the floating diffusion region FD are far apart, or other parts are arranged in the middle, the effective realization through the design of the utility model is difficult, and the compatibility of the process and the shared structure is good.

In this embodiment, the reset transistor RST is disposed between two pixel units, and two adjacent pixel units in the same column are symmetrical along the reset transistor RST. The selection transistor RS is arranged between the two pixel units, the selection transistor RS and the source electrode following transistor SF are arranged in the same direction in a layout mode, and two adjacent pixel units in the same row are symmetrical along the selection transistor RS. Therefore, the layout design of the pixel circuit has better symmetry, the performance difference of each device is small, and the performance of the pixel circuit is favorably improved.

In this embodiment, as shown in fig. 1, the image sensor further includes a conversion gain control transistor DCG and a capacitor, so as to implement conversion gain control of the pixel circuit by switching between high and low gain modes, and improve the dynamic range of the image sensor. The conversion gain control transistor DCG is laid out in the same side direction as the reset transistor RST, and the conversion gain control transistor DCG is disposed on the side near the end of the floating diffusion FD (not shown in fig. 2).

[ example two ]

Fig. 4 is a pixel circuit diagram of an image sensor according to a second embodiment of the present invention, fig. 5 is a schematic plan view of the image sensor according to the second embodiment of the present invention, and fig. 6 is a schematic cross-sectional structure diagram of the image sensor according to the second embodiment of the present invention. As shown in fig. 4 to 6, an image sensor according to a second embodiment of the present invention is substantially the same as the image sensor according to the first embodiment (fig. 1 to 3), except that in this embodiment, each floating diffusion region FD is electrically connected to the gates of two transfer transistors TX, the gate of each source follower transistor SF is electrically connected to two floating diffusion regions FD, that is, two pixel units share one floating diffusion region FD, and four pixel units share one source follower transistor SF. Sharing one floating diffusion region FD or one source follower transistor SF with a plurality of pixel units makes the pixel circuit more compact, and improves the aperture ratio and conversion gain of the pixel units. As shown in fig. 4 and 5, four adjacent pixel units have a first photodiode PD1, a first transfer transistor TX1, a second photodiode PD2, a second transfer transistor TX2, a third photodiode PD3, a third transfer transistor TX3, a fourth photodiode PD4, and a fourth transfer transistor TX4 in this order, wherein the first transfer transistor TX1 and the second transfer transistor TX2 share a first floating diffusion region FD1, the third transfer transistor TX3 and the fourth transfer transistor TX4 share a second floating diffusion region FD2, and the first floating diffusion region FD1 and the second floating diffusion region FD2 share a source follower transistor SF.

As shown in fig. 6, in the present embodiment, the source follower transistor SF and the two left and right floating diffusion regions FD are exposed in common through one contact opening, that is, the insulating layer 20 has one contact opening etched at the source follower transistor SF and the two floating diffusion regions FD (the first floating diffusion region FD1 and the second floating diffusion region FD2), the source follower transistor SF and the two floating diffusion regions FD are simultaneously exposed through one contact opening, and the insulating layer 20 between the source follower transistor SF and the floating diffusion region FD is also etched away.

It should be understood by those skilled in the art that the rest of the structure and the operation principle of the present embodiment are the same as those of the first embodiment, and are not described herein again.

[ third example ]

Fig. 7 is a schematic cross-sectional structure diagram of an image sensor in the third embodiment of the present invention. As shown in fig. 7, an image sensor according to the second embodiment of the present invention is substantially the same as the image sensor according to the second embodiment (fig. 4 to 6), except that in the present embodiment, the source follower transistor SF and the two floating diffusion regions FD are each exposed through one contact opening, that is, the insulating layer 20 is formed by etching one contact opening at each of the source follower transistor SF and the two floating diffusion regions FD (the first floating diffusion region FD1 and the second floating diffusion region FD2), and the insulating layer 20 between the source follower transistor SF and the two floating diffusion regions FD is left.

It should be understood by those skilled in the art that the rest of the structure and the operation principle of the present embodiment are the same as those of the present embodiment, and are not described herein again.

As shown in fig. 8a to 8d, the present invention further provides a method for manufacturing an image sensor, the method for manufacturing an image sensor as described above, the method comprising:

as shown in fig. 8a, a layer of insulating material is deposited on the semiconductor substrate and covers the transfer transistor TX and the source follower transistor SF. Specifically, the insulating material layer is made of SiN (silicon nitride) or SiON (silicon oxynitride), and SiN (or SiON) is deposited on the semiconductor substrate as an etching stop layer of the subsequent contact opening. Before depositing the insulating material layer, a plurality of front-end device manufacturing processes are further included, for example, etching a trench and manufacturing a trench structure on the semiconductor substrate, manufacturing the transmission transistor TX and manufacturing the source follower transistor SF, and the like.

As shown in fig. 8b, the insulating material layer is etched and contact openings are formed, thereby obtaining an insulating layer 20, and the gate of the transfer transistor TX, the gate of the source follower transistor SF, and the floating diffusion region FD are exposed from the contact openings. In this embodiment, an etching patterning process is performed on the insulating material layer, the insulating layer 20 between the source follower transistor SF and the floating diffusion region FD and the underlying SiO2 layer are removed, and a part or all of the gate of the source follower transistor SF and a part of the silicon substrate in the floating diffusion region FD region are exposed, that is, the source follower transistor SF and the floating diffusion region FD are exposed through a contact opening. Of course, in other embodiments, the insulating layer 20 between the source follower transistor SF and the floating diffusion region FD may be left, and only the insulating layer 20 and the SiO2 layer on top of the source follower transistor SF and the floating diffusion region FD may be removed, i.e., the source follower transistor SF and the floating diffusion region FD are each exposed through one contact opening, as can be seen in fig. 7.

As shown in fig. 8c, a patterned conductive layer 10 is formed on the insulating layer 20 and filled in contact openings corresponding to the gate of the source follower transistor SF and the floating diffusion region FD, which are electrically connected through the conductive layer 10. Specifically, a layer of conductive material, such as Al/Cu/W/Ti/Ta/polysilicon, is deposited by CVD (Chemical Vapor Deposition)/PVD (Physical Vapor Deposition)/furnace thermal growth, and the like, and then an etching patterning process is performed on the layer of conductive material to remove the material that is not used in other areas, wherein the conductive material in the contact opening corresponding to the gate of the transfer transistor TX is also removed, and only the area where the source follower transistor SF and the floating diffusion area FD are connected is reserved, thereby realizing the local electrical connection between the source follower transistor SF and the floating diffusion area FD.

As shown in fig. 8d, finally, in the post-stage process, for example, the conductive pillars CT and the first metal layer M1 are fabricated, only one conductive pillar CT and one first metal layer M1 are shown in the figure, and in the actual fabrication, other conductive pillars and other metal layers need to be fabricated.

In this document, the terms of upper, lower, left, right, front, rear and the like are used to define the positions of the structures in the drawings and the positions of the structures relative to each other, and are only used for the sake of clarity and convenience in technical solution. It is to be understood that the use of the directional terms should not be taken to limit the scope of the claims. It is also to be understood that the terms "first" and "second," etc., are used herein for descriptive purposes only and are not to be construed as limiting in number or order.

Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the utility model as defined by the appended claims.

Claims (10)

1. An image sensor, comprising:

a plurality of pixel cells formed in a semiconductor substrate, each of the pixel cells comprising: the photosensitive area is used for converting optical signals containing image information into electric signals through a photoelectric effect in the exposure process; the transmission transistor is connected with the photosensitive area and the floating diffusion area and is used for transferring the electric signal of the photosensitive area to the floating diffusion area; the source electrode following transistor is used for amplifying and outputting an electric signal of the floating diffusion region;

a conductive layer conductively connecting a gate of the source follower transistor with the floating diffusion region;

the conductive column is connected with the transistor in the pixel unit and the first metal layer, the thickness of the conductive layer is smaller than that of the conductive column, and the upper surface of the conductive layer is lower than that of the conductive column.

2. The image sensor of claim 1, wherein a projection of the gate of the source follower transistor onto the semiconductor substrate is offset from the floating diffusion region.

3. The image sensor of claim 2, wherein the source follower transistor has an isolation structure between the source follower transistor and the floating diffusion region, and the conductive layer continuously overlies a gate of the source follower transistor, the isolation structure, and the floating diffusion region.

4. The image sensor as claimed in claim 1, wherein an insulating layer is further disposed on the semiconductor substrate, the insulating layer is provided with contact openings corresponding to the gate of the transfer transistor, the gate of the source follower transistor and the floating diffusion region, the conductive pillars are electrically connected based on the contact openings corresponding to the gate of the transfer transistor, and the conductive layer is electrically connected based on the gate of the source follower transistor and the contact openings corresponding to the floating diffusion region.

5. The image sensor of claim 4, wherein the source follower transistor and the floating diffusion region are each exposed through one of the contact openings with a portion of the insulating layer between the conductive layer and the semiconductor substrate; or the source follower transistor and the floating diffusion region are exposed together through one of the contact openings.

6. The image sensor of claim 1, wherein a projection of the first metal layer on the semiconductor substrate has an overlapping area with the conductive layer.

7. The image sensor of claim 1, wherein two adjacent pixel cells share the same floating diffusion region, and each floating diffusion region is electrically connected to the gates of the transfer transistors of the two adjacent pixel cells.

8. The image sensor of claim 7, wherein a gate of each of the source follower transistors is electrically connected to two of the floating diffusion regions.

9. The image sensor according to claim 1, further comprising a reset transistor and a select transistor, wherein the reset transistor is disposed between two of the pixel units, and two adjacent pixel units in a same column are symmetrical along the reset transistor; the selection transistor is arranged between the two pixel units, and two adjacent pixel units in the same row are symmetrical along the selection transistor.

10. The image sensor of any of claims 1-9, wherein the conductive layer has a thickness between 50-1500 angstroms; and/or the thickness of the conductive post is between 2000 and 6000 angstroms.

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