CN215342598U

CN215342598U - Display substrate and display device

Info

Publication number: CN215342598U
Application number: CN202121123861.0U
Authority: CN
Inventors: 王利忠; 宁策; 邸云萍; 童彬彬; 徐成福; 薛大鹏; 董水浪; 姚念琦
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2021-05-24
Filing date: 2021-05-24
Publication date: 2021-12-28
Anticipated expiration: 2031-05-24

Abstract

Display substrate and display device relates to and shows technical field. According to the display device, the first transistor group which adopts the oxide semiconductor as the active layer material is arranged on one side, far away from the substrate, of the second transistor group which adopts the polycrystalline silicon as the active layer material, the area formed by orthographic projections of all transistors in the first transistor group on the substrate is overlapped with the area formed by orthographic projections of all transistors in the second transistor group on the substrate, and in the manufacturing process of the first transistor group and the second transistor group which are positioned on different layers, the occupied area of a driving circuit can be reduced while the performance of all transistors included in the first transistor group and the second transistor group is stable, so that the frame width of the display device is reduced or the resolution of the display device is improved.

Description

Display substrate and display device

Technical Field

The present disclosure relates to display technologies, and particularly to a display substrate and a display device.

Background

With the continuous development of display technologies, people have higher requirements on the frame width, the resolution and the like of the display device, and the display device is gradually developed towards the directions of narrow frames, high resolution and the like.

However, in the conventional display device, the number of transistors in the driving circuit is large, which results in a wide frame or low resolution of the display device.

SUMMERY OF THE UTILITY MODEL

Some embodiments of the present application provide the following technical solutions:

in a first aspect, a display substrate is provided, including: the driving circuit comprises a substrate and a plurality of driving circuits arranged on the substrate, wherein each driving circuit comprises a first transistor group and a second transistor group, and the first transistor group is positioned on one side of the second transistor group away from the substrate;

the first transistor group and the second transistor group both comprise at least one transistor, the material of the active layer of each transistor in the first transistor group is oxide semiconductor, and the material of the active layer of each transistor in the second transistor group is polysilicon;

the area defined by orthographic projections of the transistors in the first transistor group on the substrate and the area defined by orthographic projections of the transistors in the second transistor group on the substrate are overlapped.

Optionally, an area surrounded by orthographic projections of the transistors in the first transistor group on the substrate is located in an area surrounded by orthographic projections of the transistors in the second transistor group on the substrate.

Optionally, the first transistor group includes a first transistor and a second transistor, the second transistor group includes a third transistor, and the third transistor is any one of the transistors of the driving circuit except for the first transistor and the second transistor;

the driving circuit further comprises a storage capacitor, and the second pole of the first transistor and the second pole of the second transistor are both connected with the first end of the storage capacitor.

Optionally, a gate of the third transistor is also connected to the first end of the storage capacitor;

wherein an orthographic projection of the gate of the first transistor and/or the gate of the second transistor on the substrate is positioned in an orthographic projection of the gate of the third transistor on the substrate.

Optionally, the first transistor and the second transistor are disposed on the same layer, and the first transistor and the second transistor are both separated from the third transistor by a first buffer layer.

Optionally, the second transistor is located on a side of the first transistor away from the third transistor;

a second buffer layer is disposed between the first transistor and the third transistor, and a third buffer layer is disposed between the first transistor and the second transistor.

Optionally, the first transistor is located on a side of the second transistor away from the third transistor;

a fourth buffer layer is disposed between the second transistor and the third transistor, and a fifth buffer layer is disposed between the second transistor and the first transistor.

Optionally, a planarization layer is disposed between the first transistor group and the second transistor group, and the planarization layer covers each transistor in the second transistor group.

Optionally, the material of the planarization layer is organic siloxane, and the thickness of the planarization layer is 0.5 μm to 2 μm.

Optionally, the driving circuit is a pixel driving circuit disposed in the display area of the display substrate and configured to drive the light emitting device to emit light;

the first transistor is a first reset transistor, the second transistor is a compensation transistor, and the third transistor is a driving transistor;

the grid electrode of the first reset transistor is connected with a first reset signal line, the first pole of the first reset transistor is connected with an initialization signal line, and the second pole of the first reset transistor is connected with the first end of the storage capacitor;

the grid electrode of the compensation transistor is connected with the first grid line, the first pole of the compensation transistor is connected with the second pole of the driving transistor, and the second pole of the compensation transistor is connected with the first end of the storage capacitor;

the gate of the driving transistor is connected to the first end of the storage capacitor.

Optionally, the second transistor group further includes a data writing transistor, a first light emission control transistor, a second light emission control transistor, and a second reset transistor;

the grid electrode of the data writing transistor is connected with the second grid line, the first pole of the data writing transistor is connected with the data line, and the second pole of the data writing transistor is connected with the first pole of the driving transistor;

a gate of the first light emission control transistor is connected to a light emission control signal line, a first pole of the first light emission control transistor is connected to a first power signal line, and a second pole of the first light emission control transistor is connected to a first pole of the driving transistor;

a gate of the second light emission control transistor is connected to the light emission control signal line, a first electrode of the second light emission control transistor is connected to a second electrode of the driving transistor, and the second electrode of the second light emission control transistor is connected to the first electrode of the light emitting device;

a gate of the second reset transistor is connected with the second gate line, a first pole of the second reset transistor is connected with the initialization signal line, and a second pole of the second reset transistor is connected with a first pole of the light emitting device;

a second terminal of the storage capacitor is connected to the first power signal line.

Optionally, the driving transistor, the data writing transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the second reset transistor are all disposed in the same layer.

Optionally, the driving circuit is a GOA circuit disposed in the non-display region of the display substrate;

the first transistor is a third reset transistor, the second transistor is an input transistor, and the third transistor is an output transistor;

a gate of the third reset transistor is connected to a second reset signal line, a first electrode of the third reset transistor is connected to a second power signal line, and a second electrode of the third reset transistor is connected to a first end of the storage capacitor;

the grid electrode and the first electrode of the input transistor are both connected with an input signal line, and the second electrode of the input transistor is connected with the first end of the storage capacitor;

the gate of the output transistor is also connected to the first end of the storage capacitor, the first pole of the output transistor is connected to a clock signal line, the second pole of the output transistor is connected to an output signal line,

the second end of the storage capacitor is also connected with the output signal line.

Optionally, the second transistor group further includes a fourth reset transistor;

a gate of the fourth reset transistor is connected to the second reset signal line, a first pole of the fourth reset transistor is connected to the second power signal line, and a second pole of the fourth reset transistor is connected to the output signal line.

Optionally, the output transistor and the fourth reset transistor are disposed in the same layer.

In a second aspect, a display device is provided, which includes the display substrate.

In the embodiment of the application, the first transistor group using the oxide semiconductor as the active layer material is arranged on the side, away from the substrate, of the second transistor group using the polysilicon as the active layer material, and the area surrounded by the orthographic projection of each transistor in the first transistor group on the substrate and the area surrounded by the orthographic projection of each transistor in the second transistor group on the substrate have an overlapping area.

Drawings

Fig. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a pixel driving circuit in an embodiment of the present application;

FIG. 3 is a schematic diagram of a GOA circuit as a driving circuit in the embodiment of the present application;

fig. 4 is a schematic diagram showing a projection relationship of gates of the first transistor, the second transistor, and the third transistor according to an embodiment of the present application;

FIG. 5 is a timing diagram illustrating operation of the pixel driving circuit shown in FIG. 2;

fig. 6 shows an operation timing diagram of the GOA circuit shown in fig. 3;

fig. 7 is a flowchart illustrating a method for manufacturing a display substrate according to an embodiment of the present disclosure.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.

Referring to fig. 1, a schematic diagram of a structure of a display substrate according to an embodiment of the present disclosure is shown, fig. 2 is a schematic diagram of a driving circuit in the embodiment of the present disclosure being a pixel driving circuit, and fig. 3 is a schematic diagram of a driving circuit in the embodiment of the present disclosure being a GOA circuit.

The embodiment of the application discloses a display substrate, includes: a substrate 10 and a plurality of driving circuits disposed on the substrate 10, each driving circuit including a first transistor group 20 and a second transistor group 30, the first transistor group 20 being located on a side of the second transistor group 30 away from the substrate 10; the first transistor group 20 and the second transistor group 30 each include at least one transistor, the active layer of each transistor in the first transistor group 20 is made of an oxide semiconductor, and the active layer of each transistor in the second transistor group 30 is made of polysilicon; the area defined by the orthographic projection of each transistor in the first transistor group 20 on the substrate 10 and the area defined by the orthographic projection of each transistor in the second transistor group 30 on the substrate 10 overlap each other.

In an actual product, the substrate 10 may be a rigid substrate, such as a glass substrate, and the substrate 10 may also be a flexible substrate, such as a PI (Polyimide) substrate.

A plurality of driving circuits are provided at one side of the substrate 10. The driving circuit may be a pixel driving circuit located in a display area of the display substrate and configured to drive the light Emitting device to emit light, and therefore, a pixel driving circuit is disposed in each sub-pixel area in the display area, and the light Emitting device connected to the pixel driving circuit is controlled to emit light by the pixel driving circuit, so as to display a picture, for example, in an OLED (organic light-Emitting Diode) display device, the pixel driving circuit controls the OLED light Emitting device to emit light; the driving circuit may also be a gate driver on Array (GOA) circuit located in a non-Display region of the Display substrate, and configured to provide corresponding signals to signal lines in the Display region, for example, in a Liquid Crystal Display (LCD) Display device, the GOA circuit is configured to provide gate signals to a row of gate lines arranged in the Display region to control on and off of thin film transistors connected to the row of gate lines.

Whether the driving circuits are pixel driving circuits disposed in the display region or GOA circuits disposed in the non-display region, the transistors in each driving circuit are divided into a first transistor group 20 and a second transistor group 30 according to the material of the active layer. Specifically, transistors in the driver circuit using an oxide semiconductor as an active layer material are divided into the first transistor group 20, and transistors in the driver circuit using a polysilicon as an active layer material are divided into the second transistor group 30.

The active layer material of each transistor in the first transistor group 20 is an Oxide semiconductor, which may be IGZO (Indium Gallium Zinc Oxide), wherein the atomic molar ratio of Indium, Gallium, and Zinc is 1:1:1, and of course, the atomic molar ratio of Indium, Gallium, and Zinc in IGZO may also be in other proportional relationships; alternatively, the Oxide semiconductor may be another material such as ITGO (Indium Tin Gallium Tin Oxide).

The first transistor group 20 is disposed on the side of the second transistor group 30 away from the substrate 10, that is, the second transistor group 30 is disposed on the substrate 10 first, and then the first transistor group 20 is disposed on the side of the second transistor group 30 away from the substrate 10, wherein each transistor in the first transistor group 20 is disposed on a different layer from each transistor in the second transistor group 30, and is stacked on the substrate 10; and the first transistor group 20 and the second transistor group 30 each include at least one transistor.

In addition, the area surrounded by the orthographic projection of each transistor in the first transistor group 20 on the substrate 10 and the area surrounded by the orthographic projection of each transistor in the second transistor group 30 on the substrate 10 have an overlapping area, so that the orthographic projection area of each driving circuit on the substrate 10 is reduced, namely, the area occupied by each driving circuit is reduced. If the driving circuits are GOA circuits, when the area occupied by each driving circuit is reduced, the width of the frame occupied by the driving circuits with the same quantity is reduced, and the width of the frame of the display device can be reduced; if the driving circuit is a pixel driving circuit, when the area occupied by each driving circuit is reduced, a larger number of pixel driving circuits can be arranged in the same area, that is, the number of sub-pixels arranged in the same area is larger, so that the resolution of the display device can be improved.

It should be noted that the first transistor group 20 using an oxide semiconductor as an active layer material is disposed on the side of the second transistor group 30 using a polysilicon as an active layer material, which is far away from the substrate 10, in order to ensure stable performance of each transistor in the driving circuit.

When the active layer of each transistor in the second transistor group 30 is fabricated, it is necessary to deposit an amorphous silicon thin film, perform patterning on the amorphous silicon thin film to obtain a patterned amorphous silicon layer, and then perform crystallization on the amorphous silicon layer by using a laser annealing process, so as to convert the amorphous silicon layer into a polysilicon layer to obtain the active layer of each transistor in the second transistor group 30. If the second transistor group 30 is disposed on the side of the first transistor group 20 away from the substrate 10, since the material of the active layer of each transistor in the first transistor group 20 is an oxide semiconductor, and the thermal conductivity of the oxide semiconductor is good, when the amorphous silicon layer in the second transistor group 30 is crystallized by the laser annealing process, heat will be conducted toward the active layer in the first transistor group 20, which results in poor crystallinity of the amorphous silicon layer in the second transistor group 30, and thus unstable performance of each transistor in the second transistor group 30; in addition, in the laser annealing process of the second transistor group 30, the laser also has a large influence on the performance of each transistor in the first transistor group 20, so that each transistor in the first transistor group 20 is also unstable.

Therefore, the embodiment of the present application can ensure stable performance of each transistor in the driving circuit by disposing the first transistor group 20 on the side of the second transistor group 30 away from the substrate 10.

Alternatively, the area enclosed by the orthographic projection of each transistor in the first transistor group 20 on the substrate 10 is located in the area enclosed by the orthographic projection of each transistor in the second transistor group 30 on the substrate 10.

At this time, an orthographic projection area of each driving circuit on the substrate 10, that is, an orthographic projection area of each transistor in the second transistor group 30 on the substrate 10, may further reduce an area occupied by each driving circuit to further increase a bezel width of the display device or further improve a resolution of the display device.

As shown in fig. 1 to 3, the first transistor group 20 includes a first transistor T1 and a second transistor T2, the second transistor group 30 includes a third transistor T3, and the third transistor T3 is any one of transistors of the driving circuit except for the first transistor T1 and the second transistor T2; the driving circuit further includes a storage capacitor Cst, and the second pole 152 of the first transistor T1 and the second pole 252 of the second transistor T2 are both connected to a first terminal of the storage capacitor Cst.

Since the leakage current of the transistor using the oxide semiconductor as the active layer material is smaller than the leakage current of the transistor using the polysilicon as the active layer material, in the driving circuit, for the first transistor T1 and the second transistor T2 connected to the storage capacitor Cst, the active layer thereof selects the oxide semiconductor, which can correspondingly prevent the storage capacitor Cst from leaking electricity to the first transistor T1 and the second transistor T2, so that the voltage stability of the storage capacitor Cst is better, and even at a low refresh frequency, the voltage of the storage capacitor Cst is more stable, thereby preventing the problem of screen flicker at the low refresh frequency, and the required power consumption is also lower.

In addition, the gate electrode 33 of the third transistor T3 is also connected to the first terminal of the storage capacitor Cst; an orthographic projection of the gate 13 of the first transistor T1 and/or the gate 23 of the second transistor T2 on the substrate 10 is located within an orthographic projection of the gate 33 of the third transistor T3 on the substrate 10.

In an actual product, the first terminal of the storage capacitor Cst is actually a first plate of the storage capacitor Cst, the first plate is a block electrode, an orthographic projection of the first plate on the substrate 10 is rectangular, and the gate 33 of the third transistor T3 is actually referred to as the first plate of the storage capacitor Cst.

Since the area of the gate 33 of the third transistor T3 is large, if the orthographic projection of the gate 13 of the first transistor T1 on the substrate 10 is set to be located within the orthographic projection of the gate 33 of the third transistor T3 on the substrate 10, the first transistor T1 can form a structure similar to a double gate, so that the stability of the first transistor T1 can be improved; accordingly, if the orthographic projection of the gate 23 of the second transistor T2 on the substrate 10 is set to be located within the orthographic projection of the gate 33 of the third transistor T3 on the substrate 10, the second transistor T2 can form a double-gate-like structure, thereby improving the stability of the second transistor T2.

As shown in fig. 4, the orthographic projections of the gate 13 of the first transistor T1 and the gate 23 of the second transistor T2 on the substrate 10 are located within the orthographic projection of the gate 33 of the third transistor T3 on the substrate 10, so that the stability of the first transistor T1 and the second transistor T2 can be improved

Note that 11 denotes an active layer of the first transistor T1, and 21 denotes an active layer of the second transistor T2; fig. 4 shows a corresponding projection relationship when the driving circuit is a pixel driving circuit, and at this time, the gate 13 of the first transistor T1 is connected to the first Reset signal line Reset1, and the gate 13 of the first transistor T1 is actually a portion of the first Reset signal line Reset1, which has an overlapping region with the active layer 11 of the first transistor T1; the Gate electrode 23 of the second transistor T2 is connected to the first Gate line Gate1, and the Gate electrode 23 of the second transistor T2 is actually a portion of the first Gate line Gate1 that overlaps the active layer 21 of the second transistor T2.

Of course, when the driving circuit is a GOA circuit, the gate projection relationship of the first transistor T1, the second transistor T2, and the third transistor T3 is similar to that of fig. 4, except that the gate 13 of the first transistor T1 is connected to the second Reset signal line Reset2 and the gate 23 of the second transistor T2 is connected to the Input signal line Input.

It is to be noted that, in the driving circuit, in addition to the first transistor T1 and the second transistor T2 being divided into the first transistor group 20, the active layer material of other transistors may be replaced by an oxide semiconductor, and the transistors whose active layer material is an oxide semiconductor may be divided into the first transistor group 20, which is not limited to only the first transistor T1 and the second transistor T2 being divided into the first transistor group 20, and the other transistors being divided into the second transistor group 30.

In addition, in order to ensure that the area surrounded by the orthographic projection of each transistor in the first transistor group 20 on the substrate 10 has an overlapping area with the area surrounded by the orthographic projection of each transistor in the second transistor group 30 on the substrate 10, each transistor in the first transistor group 20 and each transistor in the second transistor group 30 may be in one-to-one correspondence, that is, there is an overlapping area between the orthographic projection of one transistor in the first transistor group 20 and one transistor in the second transistor group 30 on the substrate 10, and there is an overlapping area between the orthographic projection of the other transistor in the first transistor group 20 and the orthographic projection of the other transistor in the second transistor group 30 on the substrate 10; alternatively, the plurality of transistors in the first transistor group 20 may be associated with one transistor in the second transistor group 30, so that an orthogonal projection of the plurality of transistors in the first transistor group 20 on the substrate 10 and an orthogonal projection of one transistor in the second transistor group 30 on the substrate 10 have an overlapping region.

For example, the orthographic projection of the first transistor T1 in the first transistor group 20 on the substrate 10 is set to have an overlapping region with the orthographic projection of the third transistor T3 in the second transistor group 30 on the substrate 10, and the orthographic projection of the second transistor T2 in the first transistor group 20 on the substrate 10 is set to have an overlapping region with the orthographic projection of the other transistors except the third transistor T3 in the second transistor group 30 on the substrate 10; alternatively, the orthographic projections of the first transistor T1 and the second transistor T2 in the first transistor group 20 on the substrate 10 and the orthographic projection of the third transistor T3 in the second transistor group 30 on the substrate 10 both have an overlapping region.

In practical products, when the first transistor group 20 includes a first transistor T1 and a second transistor T2, the first transistor T1 and the second transistor T2 may be disposed in the same layer or in different layers.

In some embodiments, as shown in fig. 1, the first transistor T1 and the second transistor T2 are disposed at the same layer, and the first transistor T1 and the second transistor T2 are both separated from the third transistor T3 by the first buffer layer 41.

At this time, the first transistor T1 includes a first active layer 11, a first gate insulating layer 12, a first gate electrode 13, a first interlayer dielectric layer 14, and first source and drain electrodes sequentially disposed along a direction perpendicular to the substrate 10 and away from the substrate 10, the first source and drain electrodes include a first source 151 and a first drain 152, and the first source 151 and the first drain 152 are both connected to the first active layer 11 through a via hole penetrating through the first interlayer dielectric layer 14 and the first gate insulating layer 12. Here, the first active layer 11 refers to an active layer of the first transistor T1, the first gate electrode 13 refers to a gate electrode of the first transistor T1, one of the first source electrode 151 and the first drain electrode 152 refers to a first pole of the first transistor T1, and the other refers to a second pole of the first transistor T1.

The second transistor T2 includes a second active layer 21, a first gate insulating layer 12, a second gate 23, a first interlayer dielectric layer 14, and a second source/drain electrode sequentially disposed away from the substrate 10 along a direction perpendicular to the substrate 10, the second source/drain electrode includes a second source 251 and a second drain 252, and the second source 251 and the second drain 252 are both connected to the second active layer 21 through a via hole penetrating through the first interlayer dielectric layer 14 and the first gate insulating layer 12. Here, the second active layer 21 refers to an active layer of the second transistor T2, the second gate electrode 23 refers to a gate electrode of the second transistor T2, one of the second source electrode 251 and the second drain electrode 252 refers to a first pole of the second transistor T2, and the other refers to a second pole of the second transistor T2.

The first active layer 11 and the second active layer 21 are disposed in the same layer, the first gate electrode 13 and the second gate electrode 23 are disposed in the same layer, and the first source-drain electrode and the second source-drain electrode are also disposed in the same layer.

In addition, the third transistor T3 includes a third active layer 31, a third gate insulating layer 32, a third gate electrode 33, a third interlayer dielectric layer 34, and a third source/drain electrode sequentially disposed away from the substrate 10 in a direction perpendicular to the substrate 10, the third source/drain electrode includes a third source 351 and a third drain 352, and the third source 351 and the third drain 352 are both connected to the third active layer 31 through a via hole penetrating through the third interlayer dielectric layer 34 and the third gate insulating layer 32. Here, the third active layer 31 refers to an active layer of the third transistor T3, the third gate electrode 33 refers to a gate electrode of the third transistor T3, one of the third source electrode 351 and the third drain electrode 352 refers to a first electrode of the third transistor T3, and the other refers to a second electrode of the third transistor T3.

At this time, the first transistor T1 and the second transistor T2 are both spaced apart from the third transistor T3 by the first buffer layer 41, and in particular, the first active layer 11 and the second active layer 21 are spaced apart from the third source-drain electrode of the third transistor T3 by the first buffer layer 41.

The first buffer layer 41 may be a single layer of a silicon oxide thin film having a thickness of

To

The first buffer layer 41 may also be a stacked silicon nitride film and silicon oxide film, and the silicon oxide film is disposed on a side of the silicon nitride film away from the third transistor T3.

The material of the first active layer 11 and the second active layer 21 is an oxide semiconductor and has a thickness of

To

The first gate insulating layer 12 is made of silicon oxide and has a thick bottom

To

The material of the first gate 13 and the second gate 23 is Mo, Cu or other alloy, stacked metal, etc., and the thick bottom thereof is

To

The first interlayer dielectric layer 14 may be a single silicon oxide film or a stacked silicon nitride film and silicon oxide film having a total thickness of

To

In other embodiments, the second transistor T2 is located on a side of the first transistor T1 away from the third transistor T3; a second buffer layer is disposed between the first transistor T1 and the third transistor T3, and a third buffer layer is disposed between the first transistor T1 and the second transistor T2.

At this time, in a direction away from the substrate 10, disposed are a third transistor T3, a first transistor T1, and a second transistor T2 in this order, the third transistor T3 being spaced apart from the first transistor T1 by a second buffer layer, and the first transistor T1 being spaced apart from the second transistor T2 by a third buffer layer. Wherein the second buffer layer and the third buffer layer are made of single-layer silicon oxide film, or laminated silicon nitride film and silicon oxide film, and the total thickness is

To

The first transistor T1 includes a first active layer 11, a first gate insulating layer 12, a first gate electrode 13, a first interlayer dielectric layer 14, and first source and drain electrodes disposed along a direction perpendicular to the substrate 10 and sequentially away from the substrate 10, and the second transistor T2 includes a second active layer 21, a second gate insulating layer, a second gate electrode 23, a second interlayer dielectric layer, and second source and drain electrodes disposed along a direction perpendicular to the substrate 10 and sequentially away from the substrate 10. Accordingly, the third source-drain electrode of the third transistor T3 is spaced apart from the first active layer 11 of the first transistor T1 by the second buffer layer, and the first source-drain electrode of the first transistor T1 is spaced apart from the second active layer 21 of the second transistor T2 by the third buffer layer.

In still other embodiments, the first transistor T1 is located on a side of the second transistor T2 away from the third transistor T3; a fourth buffer layer is disposed between the second transistor T2 and the third transistor T3, and a fifth buffer layer is disposed between the second transistor T2 and the first transistor T1.

At this time, in a direction away from the substrate 10, disposed are a third transistor T3, a second transistor T2, and a first transistor T1 in this order, the third transistor T3 is spaced apart from the second transistor T2 by a fourth buffer layer, and the second transistor T2 is spaced apart from the first transistor T1 by a fifth buffer layer. Wherein, the fourth buffer layer and the fifth buffer layer are made of single-layer silicon oxide film, or laminated silicon nitride film and silicon oxide film, and the total thickness is

To

The first transistor T1 includes a first active layer 11, a first gate insulating layer 12, a first gate electrode 13, a first interlayer dielectric layer 14, and first source and drain electrodes disposed along a direction perpendicular to the substrate 10 and sequentially away from the substrate 10, and the second transistor T2 includes a second active layer 21, a second gate insulating layer, a second gate electrode 23, a second interlayer dielectric layer, and second source and drain electrodes disposed along a direction perpendicular to the substrate 10 and sequentially away from the substrate 10. Accordingly, the third source-drain electrode of the third transistor T3 is spaced apart from the second active layer 21 of the second transistor T2 by the fourth buffer layer, and the second source-drain electrode of the second transistor T2 is spaced apart from the first active layer 11 of the first transistor T1 by the fifth buffer layer.

Further, a sixth buffer layer 42 is provided between the substrate 10 and the second transistor group 30, and the material of the sixth buffer layer 42 is also a single silicon oxide film or a stacked silicon nitride film and silicon oxide film.

As shown in fig. 1, a planarization layer 43 is disposed between the first transistor group 20 and the second transistor group 30, and the planarization layer 43 covers each transistor in the second transistor group 30.

Wherein the material of planarization layer 43 is SOG (Siloxane), and the thickness of planarization layer 43 is 0.5 μm to 2 μm, for example, the thickness of planarization layer 43 can be 0.5 μm, 1 μm, 1.5 μm, or 2 μm.

After the transistors in the second transistor group 30 are fabricated on the substrate 10, the planarization layer 43 covering the transistors in the second transistor group 30 is formed, and the organic siloxane is used as the material of the planarization layer 43, so that the structure before the fabrication of the first transistor group 20 is planarized, and the planarization effect is better than that of a common organic material.

Since the crystallization of the active layer material of each transistor in the second transistor group 30 and the patterning of the source-drain electrode of each transistor in the second transistor group 30 are affected when each transistor in the second transistor group 30 is fabricated, the surface of the fabricated second transistor group 30 is uneven, and if the first transistor group 20 is fabricated directly on the uneven second transistor group 30, the defect state of each transistor in the first transistor group 20 is increased due to the uneven interface. Therefore, in the embodiment of the present application, the organic siloxane is used as the material of the planarization layer 43, so that the structure before the first transistor group 20 is fabricated is planarized, and when the first transistor group 20 is fabricated on the planarization layer 43, the problem of defect increase caused by uneven interface of each transistor in the first transistor group 20 can be avoided.

In addition, when each transistor in the first transistor group 20 is fabricated on the planarization layer 43, after an active layer of which material is an oxide semiconductor is formed, it is necessary to perform annealing treatment on the oxide semiconductor to reduce the defect state of the oxide semiconductor, at an annealing temperature as high as 350 ℃. If a conventional organic material such as resin is used as the material of the planarization layer 43, it cannot withstand a high temperature of 350 ℃ or higher, which may cause a problem in the planarization layer 43. In the embodiment of the present application, since the organic siloxane is used as the material of the planarization layer 43, and the organic siloxane can form a material similar to silicon dioxide after being cured, and can withstand a high temperature of 350 ℃ or higher, when the active layer of each transistor in the first transistor group 20 is fabricated, the planarization layer 43 using the organic siloxane as the material is not damaged by the temperature when the oxide semiconductor is subjected to the annealing treatment, that is, the organic siloxane is used as the material of the planarization layer 43, so that the high temperature annealing process of the active layer of each transistor in the first transistor group 20 can be ensured to be normally performed, and the performance of each transistor in the first transistor group 20 can be ensured to be stable.

After the transistors in the second transistor group 30 are fabricated on the substrate 10, the planarization layer 43 covering the transistors in the second transistor group 30 is formed, and then a buffer layer is formed on the side of the planarization layer 43 away from the substrate 10, where the buffer layer may be the first buffer layer 41, the second buffer layer, or the fourth buffer layer, so as to separate the second transistor group 30 from the first transistor group 20.

In addition, if the driving circuit is a pixel driving circuit disposed in the display region of the display substrate and used for driving the light emitting device to emit light, after the first transistor group 20 is formed on the side of the second transistor group 30 away from the substrate 10, a planarization film is further coated on the surface of the first transistor group 20 away from the substrate 10, the planarization film may be made of resin and have a thickness of 1 μm to 3 μm, and then a via hole penetrating through the planarization film is formed by exposure and development processes, and then a patterned anode is formed on the planarization film and connected to the corresponding electrode of the second transistor group 30 in the lower layer through the via hole penetrating through the planarization film and other film layers, so as to obtain the final display substrate.

In an alternative embodiment, the driving circuit is a pixel driving circuit disposed in the display region of the display substrate and used for driving the light emitting device to emit light; as shown in fig. 3, the first transistor T1 is a first reset transistor, the second transistor T2 is a compensation transistor, and the third transistor T3 is a driving transistor; a gate of the first Reset transistor is connected to a first Reset signal line Reset1, a first pole of the first Reset transistor is connected to an initialization signal line Vinit, and a second pole of the first Reset transistor is connected to a first end of the storage capacitor Cst; a Gate electrode of the compensation transistor is connected to the first Gate line Gate1, a first electrode of the compensation transistor is connected to a second electrode of the driving transistor, and the second electrode of the compensation transistor is connected to the first end of the storage capacitor Cst; the gate of the driving transistor is connected to a first terminal of the storage capacitor Cst.

In an actual product, the first Reset transistor is configured to be turned on under the control of a first Reset signal input from the first Reset signal line Reset1, and transmit an initialization signal provided by the initialization signal line Vinit to the first terminal of the storage capacitor Cst and the gate of the driving transistor, so as to Reset the storage capacitor Cst and the gate of the driving transistor; the compensation transistor refers to a transistor that compensates for a threshold voltage of the driving transistor, and the driving transistor refers to a transistor that drives the light emitting device to emit light.

Since the driving transistor needs to drive the light emitting device to emit light, the driving transistor needs high carrier mobility, and by using polysilicon as an active layer material of the driving transistor so that the driving transistor has high carrier mobility, the driving transistor is divided into the second transistor group 30, and the first reset transistor and the compensating transistor need to have low leakage current to prevent the storage capacitor Cst from leaking current, and therefore, by using an oxide semiconductor as an active layer material of the first reset transistor and the compensating transistor so that the first reset transistor and the compensating transistor have low leakage current, the first reset transistor and the compensating transistor are divided into the first transistor group 20.

In addition, the second transistor group further includes a data write transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a second reset transistor T7; a Gate of the Data writing transistor T4 is connected to the second Gate line Gate2, a first pole of the Data writing transistor T4 is connected to the Data line Data, and a second pole of the Data writing transistor T4 is connected to the first pole of the driving transistor; a gate of the first light emission controlling transistor T5 is connected to the light emission control signal line EM, a first pole of the first light emission controlling transistor T5 is connected to the first power signal line VDD, and a second pole of the first light emission controlling transistor T5 is connected to the first pole of the driving transistor; a gate of the second emission controlling transistor T6 is connected to the emission controlling signal line EM, a first pole of the second emission controlling transistor T6 is connected to the second pole of the driving transistor, and a second pole of the second emission controlling transistor T6 is connected to the first pole of the light emitting device EL; a Gate electrode of the second reset transistor T7 is connected to the second Gate line Gate2, a first electrode of the second reset transistor T7 is connected to the initialization signal line Vinit, and a second electrode of the second reset transistor T7 is connected to the first electrode of the light emitting device EL; a second terminal of the storage capacitor Cst is connected to the first power signal line VDD; and a second pole of the light emitting device EL is connected to the third power supply signal line VSS.

Alternatively, the driving transistor, the data writing transistor T4, the first light emission controlling transistor T5, the second light emission controlling transistor T6, and the second reset transistor T7 are all disposed in the same layer.

That is, with respect to the driving transistor, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the second reset transistor T7, the active layers of the respective transistors in the second transistor group 30 are provided in the same layer, the gates of the respective transistors in the second transistor group 30 are provided in the same layer, and the source-drain electrodes of the respective transistors in the second transistor group 30 are also provided in the same layer.

At this time, the first transistor group 20 in the pixel driving circuit includes only the first reset transistor and the compensation transistor, and the second transistor group 30 includes the remaining other transistors of the driving circuit, i.e., the second transistor group 30 includes a driving transistor, a data writing transistor T4, a first light emission controlling transistor T5, a second light emission controlling transistor T6, and a second reset transistor T7.

Wherein the first reset transistor and the compensation transistor are N-type transistors, and the driving transistor, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the second reset transistor T7 are P-type transistors; the first Gate line Gate1 to which the compensation transistor is connected is not the same Gate line as the second Gate line Gate2 to which the data write transistor T4 is connected.

As shown in fig. 5, in the Reset phase t11, the first Reset signal inputted from the first Reset signal line Reset1 is a high level signal, so that the first Reset transistor is turned on, and the initialization signal inputted from the initialization signal line Vinit resets the storage capacitor Cst and the gate of the driving transistor; at this time, since the first Gate signal input from the first Gate line Gate1 is a low level signal, and the second Gate signal input from the second Gate line Gate2 and the emission control signal input from the emission control signal EM are both high level signals, the compensation transistor, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, and the second reset transistor T7 are all turned off.

In the Data writing phase T12, the first Gate signal input by the first Gate line Gate1 is a high level signal, the second Gate signal input by the second Gate line Gate2 is a low level signal, so that the compensation transistor and the Data writing transistor T4 are turned on, the Data signal input by the Data line Data charges the storage capacitor Cst through the Data writing transistor T4, the driving transistor and the compensation transistor, and the Gate voltage of the driving transistor is Vdata + Vth, where Vth refers to the threshold voltage of the driving transistor, and Vdata refers to the voltage of the Data signal. At this time, since the first Reset signal inputted from the first Reset signal line Reset1 is at a low level and the emission control signal inputted from the emission control signal EM is at a high level, the first Reset transistor T1, the first emission control transistor T5 and the second emission control transistor T6 are all turned off; accordingly, the second reset transistor T7 is also turned on, and the second reset transistor T7 resets the first electrode of the light emitting device EL by the initialization signal inputted through the initialization signal line Vinit.

In the light emitting period T13, the light emission control signal inputted from the light emission control signal line EM is a low level signal, so that the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, a driving current is supplied to the first electrode of the light emitting device EL through the first light emission control transistor T5, the driving transistor and the second light emission control transistor T6 to drive the light emitting device EL to emit light, and the magnitude of the driving current is related to the voltage VDD of the high level voltage signal supplied from the first power signal line VDD and the voltage Vdata of the data signal. At this time, since the first Reset signal inputted from the first Reset signal line Reset1 and the first Gate signal inputted from the first Gate line Gate1 are both low level signals, and the second Gate signal inputted from the second Gate line Gate2 is a high level signal, the first Reset transistor, the compensation transistor, the data write transistor T4, and the second Reset transistor T7 are all turned off.

In another alternative embodiment, the driving circuit is a GOA circuit disposed in the non-display area of the display substrate; as shown in fig. 3, the first transistor T1 is a third reset transistor, the second transistor T2 is an input transistor, and the third transistor T3 is an output transistor; a gate of the third Reset transistor is connected to the second Reset signal line Reset2, a first pole of the third Reset transistor is connected to the second power signal line VGL, and a second pole of the third Reset transistor is connected to the first end of the storage capacitor Cst; the gate and the first pole of the Input transistor are both connected to the Input signal line Input, and the second pole of the Input transistor is connected to the first end of the storage capacitor Cst; the gate of the Output transistor is also connected to the first terminal of the storage capacitor Cst, the first terminal of the Output transistor is connected to the clock signal line CLK, the second terminal of the Output transistor is connected to the Output signal line Output, and the second terminal of the storage capacitor Cst is also connected to the Output signal line Output.

In an actual product, the third reset transistor is used to reset the storage capacitor Cst, the input transistor is used to charge the storage capacitor Cst, and the Output transistor is used to Output a corresponding signal to the Output signal line Output under the action of the storage capacitor Cst, where the Output signal line Output is actually connected to a signal line provided in the display area and used to provide a corresponding signal to the signal line in the display area. For example, in the LCD display device, the Output signal line Output is connected to a row of gate lines for supplying a gate signal to the gate lines to control on and off of the thin film transistors connected to the row of gate lines.

In addition, the second transistor group further includes a fourth reset transistor T8; a gate of the fourth Reset transistor T8 is connected to the second Reset signal line Reset2, a first pole of the fourth Reset transistor T8 is connected to the second power signal line VGL, and a second pole of the fourth Reset transistor T8 is connected to the Output signal line Output. The fourth reset transistor T8 is used to reset the Output signal line Output.

Alternatively, the output transistor and the fourth reset transistor T8 are provided in the same layer. That is, the active layers of the output transistor and the fourth reset transistor T8 are disposed in the same layer, the gates of the output transistor and the fourth reset transistor T8 are disposed in the same layer, and the source-drain electrodes of the output transistor and the fourth reset transistor T8 are also disposed in the same layer.

At this time, the first transistor group 20 in the GOA circuit includes only the third reset transistor and the input transistor, and the second transistor group 30 includes the output transistor and the fourth reset transistor T8.

The third reset transistor, the input transistor, the output transistor, and the fourth reset transistor T8 are all N-type transistors.

As shown in fig. 6, in the first phase t21, the Input signal line Input inputs a high level signal, so that the Input transistor is turned on to charge the storage capacitor Cst. At this time, the Output transistor is also turned on, but since the clock signal input by the clock signal line CLK is at a low level, the Output transistor outputs a low level signal to the Output signal line Output; also, since the second Reset signal inputted from the second Reset signal line Reset2 is a low-level signal, the third and fourth Reset transistors T8 are turned off.

At the second stage t22, due to the bootstrap action of the storage capacitor Cst, the gate voltage of the Output transistor is further pulled high, the Output transistor is turned on, and the clock signal input by the clock signal line CLK is a high level signal, so that the Output of the Output transistor to the Output signal line Output is a high level signal; at this time, the Input signal line Input and the second Reset signal line Reset2 each Input a low-level signal, so that the third Reset transistor, the Input transistor, and the fourth Reset transistor T8 are all turned off.

In the third stage T23, the second Reset signal inputted from the second Reset signal line Reset2 is a high level signal, so that the third Reset transistor and the fourth Reset transistor T8 are turned on, the third Reset transistor pulls down the voltage at the first end of the storage capacitor Cst, and the fourth Reset transistor T8 pulls down the voltage at the Output signal line Output, so as to Reset the storage capacitor Cst and the Output signal line Output, respectively.

It should be noted that the GOA circuit is not limited to include only the third reset transistor, the input transistor, the output transistor, and the fourth reset transistor T8 described above, and may further include a transistor for controlling the potential of the pull-up node and/or the pull-down node, and the like, and according to actual needs, the transistor using an oxide semiconductor as the active layer material is divided into the first transistor group 20, and the transistor using a polysilicon as the active layer material is divided into the second transistor group 30, and the first transistor group 20 is disposed on the side of the second transistor group 30 away from the substrate 10.

Referring to fig. 7, a flowchart of a method for manufacturing a display substrate according to an embodiment of the present application is shown, which may specifically include the following steps:

in step 701, a substrate is provided.

In the embodiment of the present application, first, a substrate 10 is fabricated, and the substrate 10 may be a glass substrate or a PI substrate.

Step 702, forming a second transistor group corresponding to each driving circuit on the substrate respectively.

In the embodiment of the present application, the transistors in the second transistor group 30 corresponding to each driving circuit are respectively formed on the substrate 10.

The second transistor group 30 includes at least one transistor, and the active layer of each transistor in the second transistor group 30 is made of polysilicon.

In step 703, a first transistor group is formed on a side of each of the second transistor groups away from the substrate.

In the embodiment of the present application, after the second transistor group 30 corresponding to each driving circuit is fabricated, the transistors in the first transistor group 20 are formed on the side of each second transistor group 30 away from the substrate 10.

Wherein the first transistor group 20 includes at least one transistor, and the active layer of each transistor in the first transistor group 20 is made of oxide semiconductor; moreover, the area surrounded by the orthographic projection of each transistor in the first transistor group 20 on the substrate 10 and the area surrounded by the orthographic projection of each transistor in the second transistor group 30 on the substrate 10 have overlapping areas, so as to improve the resolution of the display device or reduce the frame width.

Optionally, after step 702, the method further includes: a planarization layer is formed overlying each transistor in the second group of transistors.

In the embodiment of the present application, after the second transistor group 30 corresponding to each driving circuit is fabricated, first, the planarization layer 43 covering each transistor in the second transistor group 30 is formed, and the material of the planarization layer 43 is organosiloxane. Specifically, the surface of the second transistor group 30 on the side away from the substrate 10 is coated with organosiloxane by a coating process, and then the organosiloxane is subjected to a curing process to obtain the planarization layer 43.

The embodiment of the application also provides a display device which comprises the display substrate.

In practical products, the display substrate can be applied to products such as an LCD display device, an OLED display device, a Mini LED display device, and a quantum dot LED display device, so as to reduce the frame width of the display device or improve the resolution of the display device.

In specific implementation, the display device provided in the embodiment of the present application may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

In addition, as to the specific structure of the display substrate in the display device, reference may be made to the description of the display substrate, and the effect is similar to that achieved by the display substrate, and for avoiding repetition, no further description is given here.

Reference herein to "one embodiment," "an embodiment," or "one or more embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Moreover, it is noted that instances of the word "in one embodiment" are not necessarily all referring to the same embodiment.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the disclosure may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The disclosure may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solutions of the present disclosure, not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present disclosure.

Claims

1. A display substrate, comprising: the driving circuit comprises a substrate and a plurality of driving circuits arranged on the substrate, wherein each driving circuit comprises a first transistor group and a second transistor group, and the first transistor group is positioned on one side of the second transistor group away from the substrate;

2. The display substrate of claim 1, wherein an area defined by orthographic projections of the transistors of the first transistor group on the substrate is located in an area defined by orthographic projections of the transistors of the second transistor group on the substrate.

3. The display substrate according to claim 1 or 2, wherein the first transistor group includes a first transistor and a second transistor, the second transistor group includes a third transistor, and the third transistor is any one of the transistors of the driving circuit except the first transistor and the second transistor;

4. The display substrate according to claim 3, wherein a gate of the third transistor is also connected to the first end of the storage capacitor;

5. The display substrate of claim 3, wherein the first transistor and the second transistor are disposed on a same layer, and wherein the first transistor and the second transistor are both separated from the third transistor by a first buffer layer.

6. The display substrate according to claim 3, wherein the second transistor is located on a side of the first transistor remote from the third transistor;

7. The display substrate according to claim 3, wherein the first transistor is located on a side of the second transistor remote from the third transistor;

8. The display substrate according to claim 1, wherein a planarization layer is disposed between the first transistor group and the second transistor group, and the planarization layer covers each of the transistors in the second transistor group.

9. The display substrate according to claim 8, wherein the material of the planarization layer is organosiloxane, and the thickness of the planarization layer is 0.5 μm to 2 μm.

10. The display substrate according to claim 3, wherein the driving circuit is a pixel driving circuit disposed in a display region of the display substrate and configured to drive a light emitting device to emit light;

11. The display substrate according to claim 10, wherein the second transistor group further comprises a data write transistor, a first light emission control transistor, a second light emission control transistor, and a second reset transistor;

12. The display substrate according to claim 11, wherein the driving transistor, the data writing transistor, the first light emission control transistor, the second light emission control transistor, and the second reset transistor are all provided in the same layer.

13. The display substrate according to claim 3, wherein the driving circuit is a GOA circuit disposed in a non-display region of the display substrate;

14. The display substrate according to claim 13, wherein the second transistor group further comprises a fourth reset transistor;

15. The display substrate according to claim 14, wherein the output transistor and the fourth reset transistor are disposed in the same layer.

16. A display device comprising the display substrate according to any one of claims 1 to 15.