CN215183979U - ESD protection transistor - Google Patents

Abstract

The utility model provides a ESD protection transistor, ESD protection transistor includes: the semiconductor device comprises a substrate, a buried dielectric layer formed on the substrate, and a surface semiconductor layer formed on the buried dielectric layer; wherein an open data link interface transistor is formed in the surface semiconductor layer. Based on the structural design of the ESD protection transistor, the protection capability of the transistor is improved, so that the CMOS device is effectively protected by ESD, and the problems of damage, failure or performance reduction of the CMOS device caused by ESD are solved.

Description

ESD protection transistor

Technical Field

The utility model relates to an electrostatic protection technical field, in particular to ESD protection transistor.

Background

Electrostatic discharge (ESD) is a charge discharge process that accumulates static electricity in an insulating material, but this process can cause damage, failure, or reduced performance to a large number of transistors, diodes, and other fine structures in an integrated circuit. Particularly, various CMOS devices are extremely sensitive to ESD, and electrostatic voltages of several tens of volts, even tens of volts or several volts can cause melting, soft breakdown, and hard breakdown of various fine structures. Therefore, ESD protection is a significant issue for the entire IC.

With the increasing integration level of ICs, the requirements for ESD protection technology are becoming more stringent, and those skilled in the art are always looking for a solution to meet this requirement for how to perform effective ESD protection on CMOS devices.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide an ESD protection transistor to CMOS device influences because of receiving the ESD among the solution prior art, leads to the damage of CMOS device, inefficacy or the problem of performance reduction.

In order to solve the above technical problem, the utility model provides a ESD protection transistor, ESD protection transistor includes: the semiconductor device comprises a substrate, a buried dielectric layer formed on the substrate, and a surface semiconductor layer formed on the buried dielectric layer; wherein an open data link interface transistor is formed in the surface semiconductor layer.

Optionally, in the ESD protection transistor, the open data link interface transistor is a first open data link interface transistor or a second open data link interface transistor, and a gate oxide layer thickness of the first open data link interface transistor is different from a gate oxide layer thickness of the second open data link interface transistor.

Optionally, in the ESD protection transistor, a gate oxide layer of the first open data link interface transistor has a thickness of

The gate oxide layer thickness of the second open data link interface transistor is

Optionally, in the ESD protection transistor, an operating voltage of the first open data link interface transistor is 1.2V, and an operating voltage of the second open data link interface transistor is 2.5V.

Optionally, in the ESD protection transistor, the first open data link interface transistor has a floating body structure.

Optionally, in the ESD protection transistor, the second open data link interface transistor has a floating body structure or a body contact structure.

Optionally, in the ESD protection transistor, the second open data link interface transistor is a T-type gate body contact structure.

Optionally, in the ESD protection transistor, a failure limit of the open data link interface transistor is determined by a maximum value of a drain-source voltage.

In the present invention, the ESD protection transistor comprises: the semiconductor device comprises a substrate, a buried dielectric layer formed on the substrate, and a surface semiconductor layer formed on the buried dielectric layer; wherein an open data link interface transistor is formed in the surface semiconductor layer. Based on the structural design of the ESD protection transistor, the protection capability of the transistor is improved, so that the CMOS device is effectively protected by ESD, and the problems of damage, failure or performance reduction of the CMOS device caused by ESD are solved.

Drawings

The foregoing and other objects, features and advantages of the disclosure will be apparent from the following more particular descriptions of exemplary embodiments of the disclosure as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the disclosure.

Fig. 1 is a schematic diagram of an ESD protection transistor according to an embodiment of the present invention;

FIG. 2 is a graph showing the maximum value of drain-source voltage of an NMOS transistor and the variation of gate bias voltage of three transistors, namely a floating body transistor, a body contact transistor and a body effect transistor, when the pulse width is 120 ns;

FIG. 3 is a graph showing the maximum value of drain-source voltage of a PMOS transistor and the gate bias voltage of three transistors, i.e., a floating body transistor, a body contact transistor and a body effect transistor, when the pulse width is 120 ns;

FIG. 4 is a graph of the maximum value of the drain-source voltage versus the pulse width for floating body NMOS and PMOS.

Detailed Description

The ESD protection transistor according to the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.

Furthermore, each embodiment described below has one or more technical features, which does not mean that all technical features of any embodiment need to be implemented simultaneously by a person using the present invention, or that all technical features of different embodiments can be implemented separately. In other words, in the implementation of the present invention, based on the disclosure of the present invention, and depending on design specifications or implementation requirements, a person skilled in the art can selectively implement some or all of the technical features of any embodiment, or selectively implement a combination of some or all of the technical features of a plurality of embodiments, thereby increasing the flexibility in implementing the present invention.

In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings.

Currently, the technical path for protecting against ESD includes two kinds, the first kind: the ESD protection of various devices is continuously optimized, and the ESD protection grade of the devices is continuously improved; and the second method comprises the following steps: various ESD protection networks are designed for the IC device, and the ESD attack resistance of the integrated circuit is improved. The utility model discloses a scheme is a technical exploration to a technical route to it shows the progress to make.

The utility model provides a novel ESD protection transistor, ESD protection transistor includes: the semiconductor device comprises a substrate, a buried dielectric layer formed on the substrate, and a surface semiconductor layer formed on the buried dielectric layer; wherein, an open data link interface transistor (also called ODI transistor) is formed in the surface semiconductor layer.

Specifically, the open data link interface transistor has two structures, and the two structures are different in the thickness of the gate oxide layer of the transistor, one is a first open data link interface transistor (hereinafter, abbreviated as an OD1 structure), and the other is a second open data link interface transistor (hereinafter, abbreviated as an OD2 structure). In this embodiment, the transistors of OD1 structure have

A gate oxide (gate oxide) having an operating voltage of 1.2V; the transistor with OD2 structure has

And the gate oxide layer has an operating voltage of 2.5V. OD1 has only floating body structures, OD2 has both floating body and body-contacted (body-tipped) structures.

Preferably, the second open data link interface transistor is a T-type gate body contact structure, and has a better ESD protection performance through verification. Specifically, fig. 1 is a schematic diagram of an ESD protection transistor in the present embodiment. As shown in fig. 1, the polysilicon gate (polysilicon gate) of such an ODI transistor has a T-shaped structure, allowing a body contact (see T-shaped gate in fig. 1) structure to be created. Since the breakdown characteristics of the body-contacted transistor depend on the body resistance, the width of the polysilicon is limited. Consider a cross-section of a transistor with a body contact d (labeled d in the figure), see fig. 1. If a stress voltage Vds is applied between the drain (drain in fig. 1) and the other electrode (source, gate, body contact, all grounded), the collector (collector) -base (base) junction (junction) will be reverse biased, resulting in avalanche current generation. This avalanche current creates a hole current that will effectively drift through the body contact resistance to ground, causing the body potential to increase, causing an avalanche junction in the transistor. This local body potential rise is high enough to forward bias the emitter-base junction (i.e., source) and the bipolar (bipolar) to turn on. Since the bulk resistance and the local bulk potential increase with distance d, the transistor channel width (channel width) is given as w (see fig. 1), and the voltage at which the first breakdown occurs when d is w defines the bulk structure cross-section is denoted as Vt 1. In order to ensure the uniformity of the volume resistance, the present embodiment assumes: the maximum channel width of the single body contact transistor was fixed to 2 μm. Therefore, large transistors, such as ESD clamps (rail clamps), must be laid out in a smaller part of the arrow arrangement (in an array of small segments). The same layout applies to a single device under test.

The utility model discloses an in the research and development process, utility model people have still carried out a large amount of pulse high current tests, the brief follows as follows: a50 omega/120 nm Transmission Line Pulse (TLP) test system is built in a field, an HP8114 pulse generator is used for searching the operation limit value of the ESD device, and a real network is arranged so as to optimize the design of the ESD device. The test system can change the control gate bias voltage of the tested structure, can directly provide a drain stress voltage, and can also directly apply pressure by using a resistor voltage divider.

Furthermore, the present inventors have studied how to determine the maximum value Vds _ max of the drain-to-source voltage before failure, so as to effectively know the failure limit of the open data link interface transistor (as the result of experimental verification of FIGS. 2-4: the failure limit of the open data link interface transistor is determined by Vds _ max), since Vds _ max determinants include the device type (including OD1 or OD2, whether floating or body contact, single or cascade), the applied gate bias Vgs, and the applied pulse width tpulse. Since It2 was very low for all devices tested, 2mA/μm or even lower. Therefore, engineering methods to determine failures by testing ESD discharge currents that exceed NMOS and PMOS buffers (buffers) sufficiently high are not easily implemented. As an alternative, this example uses a different but similar approach, the so-called bulk technologies: SOI devices were compared to corresponding 90nm bulk counterpart (bulk counter) devices. Refer specifically to fig. 2-4 for understanding.

Referring to fig. 2, it is shown that when the pulse width is 120ns, the maximum value of the drain-source voltage Vds _ max of the NMOS transistor and the gate bias variation curves of the Floating Body, the Body-contact Body-finished, and the Body-effect Bulk transistors are shown. For comparison, OD2 (shown in FIG. 2) ((1))

2.5V) bulk device (bulk device) is also labeled in fig. 2. Such transistor gate bias can be raised from 0V to a maximum voltage Vgs-Vds (this voltage is also known as the hot-gate voltage). For the OD2 transistor, this is already the lower voltage limit for its oxide layer to fail (about 10V). Note that Vds _ max corresponds to the greater of either Vt1 or Vt 2. For Vgs 0V, all such transistors are at Vt1>Vt2, showing a rapid reversal (i.e., a snap-back) on the id (vds) curve. For Vgs>0V, none of these transistors will be at Vt2>Vt1 shows this rapid reversal. Note that Vds _ max is significantly reduced to about 2V for either floating body or body contact SOI transistors. The value of Vds _ max for the OD2 floating body to body contact transistor is known to be almost the same at every point, except that Vgs is 0V, which shows about 1.8V above the floating body transistor Vds _ max. Only at a low impact ionization rate when Vgs 0V, the body contact transistor can suppress the body potential, delay NPN turn-on, and allow Vds to exceed 5V without damage. For higher gate bias, the body contact suppression is too strong and does not work.

Continuing to refer to fig. 2 (b), a plot of Vds _ max versus Vgs for the OD1 NMOS transistor and the cascode OD1 NMOS transistor is shown, as well as OD1 (b)

1.2V) bulk transistor related data for comparison. In pulse testing of the OD1 NMOS transistor, the gate bias was varied from 0V to Vgs-vds (hot gate) maximum. For cascode transistors, it is important to note that during the pulse test a correct gate bias voltage is applied to the upper limit (VDD), and that when a practical cascode output buffer design exists, the lower gate bias voltage is gradually increased from 0V to VDD. The worst scenario may be encountered when cascode NMOS output buffer boosting is applied: the applied stress is ESD of just positive polarity, and it is predicted that the ESD current path will flow through the diode to VDD and through the active MOSFET rail clamp to VSS. VDD is located at the midpoint of the ESD path, at a voltage near half the I/O pad voltage (Vds/2). Therefore, a blocking voltage divider is used in the pulse test of the device with the cascode structure to ensure that the gate bias voltage is equal to Vds/2 at the upper limit Vgs 1. The lower gate voltage is from 0V to Vgs2 Vds/2 (hot gate). The gate bias corresponds to an OD1 transistor oxide failure limit of about 5V. This limit is indicated by the vertical line in section (b) of FIG. 2. Note that the reliability of the transistor is limited by the first or second breakdown (Vds max) rather than the vertical line in fig. 2.

Continuing with FIG. 2, comparing the data for the floating body SOI transistor and the bulk effect transistor, it can be seen that the floating body NMOS transistor Vds _ max is relatively low, approximately 2.6-2.8V. The following reasoning can therefore be drawn: such devices are very difficult to protect when used in output buffer devices. However, as shown in part (b) of fig. 2, Vds _ max can be greatly increased by 2 cascode OD1 transistors. And the other one adds a group of output resistors and a secondary ESD diode, thereby improving the ESD protection performance of the OD1 NMOS output buffer area.

Please refer to fig. 3, which shows the maximum value of the drain-source voltage Vds _ max of the PMOS transistor and the gate bias variation curves of the Floating Body, the Body-contact Body-finished, and the Body-effect Bulk transistors. As shown in fig. 3, the corresponding body effect transistor data is shown together in fig. 3 for comparison. Note that the absolute value of Vds max again shows a significant reduction (approximately 2V) for SOI devices compared to bulk effect transistors. In part (a) of fig. 3, the body-contact type more floating body type Vds _ max shows some improvement in terms of the OD2 PMOS transistor. However, it is also shown in fig. 3 that Vds _ max exhibits the greatest ESD protection performance improvement during ESD events, especially when Vgs is Vds (hot gate). The Vds _ max minimum absolute value is present at Vgs from-0.5V to-2V.

In part (b) of fig. 3, the OD1 PMOS transistor Vds _ max exhibits a rather low absolute value. But higher than the NMOS transistor. For example, the worst case scenario is that Vds _ max for OD1 PMOS is-3.2V, while only 2.6V for OD1 NMOS. This again indicates that the failure limits of the OD1 and OD2 transistors are determined by Vds _ max, but not others, such as oxide quality.

For floating body transistors, there is a unique ESD phenomenon: vds max is very sensitive to pulse width (tpulse). This sensitivity to pulse width can be explained by a capacitance charging model. The parasitic bipolar on-time in such SOI structures varies from 100ps to several microseconds, depending on the presence or absence of a body contact and the magnitude of the applied voltage stress pulse. If the bulk resistance is small (for body-contacted SOI structures), the RC time constant for charging the source-body junction (source-body junction) during the pulse test is negligible (about 1ps), on the order of 100ns with respect to the stress pulse width, and certainly negligible. Holes created by ionization at the collector-base junction (collector-base junction) will charge the structural body, and once the charge reaches a certain value, the emitter-base junction (emitter-base junction) is forward biased, turning the bipolar on (Vt 1). Therefore, bipolar fast inversion will occur immediately during the pulse rise in body-contacted SOI transistors. If the body resistance is infinite (as with a floating body SOI transistor), the body potential will rise for two reasons, one drain junction (drain junction) and the other capacitive charging current. During the fast pulse expansion initiation period (about 1ns), the capacitive charging current dominates. However, it may not be sufficient to turn on the bipolar excitation. At this point, the impact ionization current further raises the body potential during the pulse steady state. If Vds and tpulse are sufficient to raise the body potential, the bipolar will excite on.

Please refer to fig. 4, which is a graph showing the variation of the maximum value Vds _ max of the drain-source voltage of the floating body NMOS and PMOS with the pulse width tpulse. As shown in fig. 4, Vds _ max decreases slightly as tpulse Vds _ max increases for all transistors and all Vgs voltages. The OD2 NMOS transistor decreases Vds _ max by the maximum (about 1V) when Vgs is 0 (see part (a) in fig. 4). This is because, for a given Vds, the OD2 transistor exhibits the lowest impact ionization current at Vgs 0. Here only, the floating body charge current is low enough to exhibit Vt1 significantly dependent on the pulse width tpulse. For PMOS, Vds _ max is very insignificant with pulse width (see section (b) in fig. 4). However, for the shortest pulse, Vds _ max goes to 0.5V. These pulse intervals require higher voltage amplitudes to fully charge the transistor body in order to turn on the parasitic bipolar. Because of this dependence on the pulse width tpulse, we reasonably assume that tpulse ═ 500ns can be defined as the transistor operating limit.

From the data and analysis results of fig. 2-4, it can be seen that the SOI transistor, whether of a floating body structure or a body contact structure, can be widely applied to 2.5V I/O designs. For the remaining I/O designs, an ESD network can be built using body contact OD2 transistors.

Accordingly, the present embodiment further provides an ESD protection method for a CMOS device, where the CMOS device uses the ESD protection transistor to perform ESD protection on the CMOS device, and the specific protection principle may refer to the relevant contents in fig. 1 to fig. 4, which is not described herein in detail. Preferably, the ESD protection transistor in this embodiment is suitable for protection devices: a 90nm double gate oxide technology device and a depletion type silicon-on-insulator technology device.

In summary, the present invention provides an ESD protection transistor, which includes: the semiconductor device comprises a substrate, a buried dielectric layer formed on the substrate, and a surface semiconductor layer formed on the buried dielectric layer; wherein an open data link interface transistor is formed in the surface semiconductor layer. Based on the structural design of the ESD protection transistor, the protection capability of the transistor is improved, so that the CMOS device is effectively protected by ESD, and the problems of damage, failure or performance reduction of the CMOS device caused by ESD are solved.

The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure are all within the scope of the claims.

Claims (8)

1. An ESD protected transistor, comprising: the semiconductor device comprises a substrate, a buried dielectric layer formed on the substrate, and a surface semiconductor layer formed on the buried dielectric layer; wherein an open data link interface transistor is formed in the surface semiconductor layer.

2. The ESD protection transistor of claim 1, wherein the open data link interface transistor is a first open data link interface transistor or a second open data link interface transistor, a gate oxide thickness of the first open data link interface transistor being different than a gate oxide thickness of the second open data link interface transistor.

3. The ESD protection transistor of claim 2, wherein a gate oxide layer thickness of the first open data link interface transistor is 18 a and a gate oxide layer thickness of the second open data link interface transistor is 50 a.

4. The ESD protection transistor of claim 3, wherein the operating voltage of the first open data link interface transistor is 1.2V and the operating voltage of the second open data link interface transistor is 2.5V.

5. The ESD protection transistor of claim 2, wherein the structure of the first open data link interface transistor is a floating body structure.

6. The ESD protection transistor of claim 2, wherein the structure of the second open data link interface transistor is a floating body structure or a body contact structure.

7. The ESD protection transistor of claim 6, wherein the second open data link interface transistor is a T-type gate body contact structure.

8. The ESD protection transistor of claim 1, wherein the failure limit of the open data link interface transistor is determined by a maximum value of the drain-source voltage.

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