CN215117516U

CN215117516U - Acquisition system based on USB bus

Info

Publication number: CN215117516U
Application number: CN202121585654.7U
Authority: CN
Inventors: 赵斌
Original assignee: Beijing Xinchaorenda Technology Ltd
Current assignee: Beijing Xinchaorenda Technology Ltd
Priority date: 2021-07-13
Filing date: 2021-07-13
Publication date: 2021-12-10
Anticipated expiration: 2031-07-13

Abstract

The utility model relates to the technical field of data acquisition, in particular to an acquisition system based on a USB bus, which comprises a USB bus module, an FPGA synchronous clock setting module and an AD conversion module; an external analog signal is connected into an AD conversion module through a connector, the AD conversion module is connected with an FPGA synchronous clock setting module, and the FPGA synchronous clock setting module is connected with a USB bus through a USB bus chip. After the structure is adopted, the utility model discloses a frequency of the external synchronous clock of output is reduced through the means of frequency division and frequency multiplication, and the frequency of the external synchronous clock of input is risen through the means of frequency multiplication, realizes using lower synchronous clock to accomplish the clock synchronization function of high frequency; the multi-card expansion can be realized, and the number of cards is not limited; the system can provide a synchronous clock by setting different modes, and is convenient for the construction of an acquisition system.

Description

Acquisition system based on USB bus

Technical Field

The utility model relates to a data acquisition technical field, especially a collection system based on USB bus.

Background

At present, when using many usb data acquisition cards to carry out data acquisition, often have clock synchronization's user demand, but every sampling data that many cards gathered like this all can the one-to-one, but along with the increase of synchronous clock frequency can have very high requirement to synchronous clock connection signal line, the relative low frequency signal of transmission distance simultaneously also shortens greatly. To the problem that exists when using the high frequency clock as synchronous clock, the utility model provides an effective feasible solution.

Chinese utility model patent CN101719169A discloses a three-in-one USB data acquisition card, which comprises an analog-digital conversion circuit, and is characterized in that it is provided with a microcontroller control circuit with a first USB interface, a working mode switch, a USB master/peripheral controller control circuit and a second USB interface, the microcontroller control circuit is connected with the analog-digital conversion circuit and the USB master/peripheral controller control circuit through a general CPU bus, the USB master/peripheral controller control circuit is correspondingly connected with the second USB interface; the microcontroller control circuit determines the working mode of the data acquisition card according to the level of the level signal input by the moving contact of the working mode switch.

Disclosure of Invention

The utility model discloses the signal transmission problem that exists when the technical problem that needs to solve uses high frequency synchronous clock.

In order to solve the technical problem, the utility model discloses an acquisition system based on a USB bus, which comprises a USB bus module, a FPGA synchronous clock setting module and an AD conversion module; an external analog signal is connected into an AD conversion module through a connector, the AD conversion module is connected with an FPGA synchronous clock setting module, and the FPGA synchronous clock setting module is connected with a USB bus through a USB bus chip.

Preferably, the FPGA synchronous clock setting module is connected with a memory, and the memory is connected with a USB bus chip.

Preferably, the USB bus adopts a USB2.0 bus.

Preferably, the FPGA synchronous clock setting module is connected with a 4-bit dial.

After the structure is adopted, the utility model discloses a frequency of the external synchronous clock of output is reduced through the means of frequency division and frequency multiplication, and the frequency of the external synchronous clock of input is risen through the means of frequency multiplication, realizes using lower synchronous clock to accomplish the clock synchronization function of high frequency; the multi-card expansion can be realized, and the number of cards is not limited; the system can provide a synchronous clock by setting different modes, and is convenient for the construction of an acquisition system.

Drawings

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

Fig. 1 is the utility model relates to an acquisition system frame schematic diagram based on USB bus.

Fig. 2 is a schematic diagram of the master-slave card cascade of the present invention.

Fig. 3 is a schematic diagram of the signal interface of the present invention.

Fig. 4 is a schematic diagram of the USB chip interface of the present invention.

Fig. 5 is the utility model discloses the synchronous clock of synchronous clock setting module of FPGA sets up the module schematic diagram.

Detailed Description

As shown in fig. 1, the utility model discloses an acquisition system based on USB bus, which comprises a USB bus module, a FPGA synchronous clock setting module and an AD conversion module; external analog signals are connected into the AD conversion module through the connector, the AD conversion module is connected with the FPGA synchronous clock setting module, the FPGA synchronous clock setting module is connected with the USB bus through the USB bus chip, and the FPGA synchronous clock setting module is connected with the 4-bit dial. The FPGA synchronous clock setting module is connected with a memory, and the memory is connected with a USB bus chip. In this embodiment, the USB bus module adopts a USB2.0 bus, the connector adopts a SCSI68 connector, and the USB bus chip adopts a chip CY 68013A. The signal interface is shown in fig. 3, the USB chip interface is shown in fig. 4, and the FPGA synchronous clock setting module is shown in fig. 5.

The utility model discloses a mode is as follows:

1. the method is characterized in that the SDRAM is FIFO-based, the high-speed AD data is buffered by the FIFO, and then the AD data is transmitted to the host computer through the USB by the FIFO state.

2. Each card has an external trigger mode, in which an external trigger signal needs to be accessed, after a user configures a sampling frequency and a synchronous channel, an AD is started, and the AD does not start to work immediately, but waits for the arrival of the external trigger signal and starts to work after an effective level is given. The trigger source is TTL level signal (digital trigger), the external trigger is default to be input mode, and the external trigger signal is input. When the main card is in a soft trigger mode, the main card sets the external trigger pin to be in an output mode through a jumper wire, and outputs an external trigger signal when the main card receives a soft trigger starting instruction so as to synchronously trigger the starting of the slave cards.

3. Each card is provided with an external clock mode, and the external trigger clock mode or the multi-card synchronous clock can be selected for use. External trigger clock mode: the sampling frequency is determined by the clock, and each CLK rising edge collects a point; synchronizing the clock: the clock is used for an ADC working clock, a specific clock is required to be provided for normal work, and a synchronous clock is required to be connected with a stable clock signal before collection is started. With specific reference to analog input pin definitions.

The technical scheme comprises the following functional modules: USB2.0 bus module, AD conversion module, data storage, etc.

AD conversion: external analog signals are accessed through a SCSI68 connector, enter an ADC through a pre-stage operational amplifier, and an AD control time sequence is completed through an FPGA.

Data storage: the result of the AD conversion is stored in the SDRAM. The time sequence of reading and writing data is controlled by the FPGA.

4. Through the above two modes, two multi-card synchronous acquisition implementation schemes can be constructed. 1: cascading a master card and a slave card; 2: common external trigger + common external synchronous clock;

scheme 1: and (4) cascading the master card and the slave card. The schematic diagram of the connection mode is shown in fig. 2, the external trigger can ensure that the slave card and the master card can acquire data simultaneously, and the external synchronous clock can ensure that long-time data acquisition cannot generate offset.

Setting a main card: the main card uses an internal clock + soft start mode and adopts an external trigger output mode (EXT _ TRG _ OUT), the external clock output mode adopts a synchronous clock mode, and the acquisition mode adopts a soft start mode.

The slave card is provided with: the slave card adopts an external clock + external trigger (rising edge trigger) mode and is used for receiving a synchronous clock and a trigger signal of the master card. An external trigger input mode (EXT _ TRG _ IN) is adopted, the external clock input mode is a 'synchronous clock' mode, the acquisition mode is an 'external trigger' mode, and the trigger direction is as follows: the rising edge triggers.

Scheme 2: the master card and the slave card jointly trigger the + external clock mode. Compared with scheme 1, all board cards are set to be in a slave card mode: setting each card to be IN an external trigger input mode (EXT _ TRG _ IN), wherein the external clock input adopts a synchronous clock mode, the acquisition mode adopts an external trigger mode, and the trigger direction is as follows: the rising edge triggers. The external trigger signal and the external synchronous clock mode are provided by third-party equipment, and multi-card synchronous acquisition can be completed.

Although specific embodiments of the present invention have been described above, it will be appreciated by those skilled in the art that these are merely examples and that many changes and modifications may be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims.

Claims

1. An acquisition system based on a USB bus is characterized in that: the device comprises a USB bus module, an FPGA synchronous clock setting module and an AD conversion module; an external analog signal is connected into an AD conversion module through a connector, the AD conversion module is connected with an FPGA synchronous clock setting module, and the FPGA synchronous clock setting module is connected with a USB bus through a USB bus chip.

2. A USB bus based acquisition system according to claim 1, wherein: the FPGA synchronous clock setting module is connected with a memory, and the memory is connected with a USB bus chip.

3. A USB bus based acquisition system according to claim 1, wherein: the USB bus module adopts a USB2.0 bus.

4. A USB bus based acquisition system according to claim 1, wherein: the FPGA synchronous clock setting module is connected with the 4-bit dial.