CN214477449U - Multi-chip packaging structure and micro-system thereof - Google Patents
Multi-chip packaging structure and micro-system thereof Download PDFInfo
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Abstract
The utility model relates to a multi-chip package technical field, concretely relates to multi-chip packaging structure and microsystem thereof. The multi-chip package structure includes: the working voltage monitor is connected with the input ends of the working voltage vdd1 of the first chip and the working voltage vdd2 of the second chip respectively and used for outputting the working voltage comparison results of vdd1 and vdd 2; and the input end of the input driver is connected with the output end of the working voltage monitor and used for controlling the working mode of the input driver according to the working voltage comparison result so that the first chip works in a working mode which is adaptive to the working mode of the input driver. The utility model discloses according to the operating voltage comparison result of first operating voltage vdd1 and second operating voltage vdd2, the mode of operation of control input driver to make first chip work at the mode of operation that suits with the mode of operation of input driver, reduced that operating condition is incorrect, the interference of circumstances such as electric leakage to tests such as chip sieve piece, improved the system function debugging efficiency of multi-chip package.
Description
Technical Field
The utility model relates to a multi-chip package technical field, concretely relates to multi-chip packaging structure and microsystem thereof.
Background
In recent years, the development of semiconductor technology under the guidance of "moore's law" in the deep submicron stage is slow due to physical limitations. In order to meet the trend of high bandwidth, high complexity and functional diversity of computer or electronic systems, advanced multi-chip packaging technology becomes a key innovative path for continuously optimizing system performance and cost, and is a continuation of moore's law on computer or electronic systems.
Multi-chip package (multi-chip package) is a package that integrates a plurality of chips with different sizes, different manufacturing processes, and different materials into a package, including stacking 2D, 2.5D, 3D chips, and is applied to advanced mobile communication/computing and high bandwidth memory systems.
Because the chips in the multi-chip package are not electrically connected through the interconnection lines before the packaging, or even if the multi-chip package is completed, because a certain chip is not electrified or is not electrified, the input and output circuit of the chip is in a suspended state, the working state of the chip is incorrect, the electric leakage and other conditions occur, the screening of a fault chip is interfered, and the debugging of the whole system function of the multi-chip package is influenced.
Therefore, how to improve the system function debugging efficiency of multi-chip package is a technical problem that needs to be solved at present.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a multi-chip packaging structure and microsystem thereof to improve multi-chip packaging's system function debugging efficiency.
In order to achieve the above object, the embodiment of the present invention provides the following solutions:
in a first aspect, an embodiment of the present invention provides a multi-chip package structure, the inside of the structure includes a first chip and a second chip, the structure further includes:
an operating voltage monitor, the input terminals of which are respectively connected with the operating voltage vdd1 of the first chip and the operating voltage vdd2 of the second chip, for outputting the operating voltage comparison results of vdd1 and vdd 2;
the input end of the input driver is connected with the output end of the working voltage monitor and used for controlling the working mode of the input driver according to the working voltage comparison result so that the first chip works in a working mode which is adaptive to the working mode of the input driver; wherein the second chip accesses the first chip through the input driver.
In one possible embodiment, the operating voltage monitor comprises a first voltage divider circuit, a second voltage divider circuit, a first comparator, a second comparator, an en _ lvsft output, and a flag _ vdd2on output;
the first voltage division circuit is connected between the vdd2 and the ground and comprises a first voltage division point;
the second voltage division circuit is connected between the vdd1 and the ground and comprises a high-voltage division point and a low-voltage division point;
the first voltage division point is respectively connected with the reverse input end of the first comparator and the forward input end of the second comparator;
the high-voltage division point is connected with the positive input end of the first comparator;
the low-voltage division point is connected with the reverse input end of the second comparator;
the output end of the first comparator is connected with the en _ lvsft output end; the en _ lvsft output end is connected with the en _ ls input end of the input driver;
the output end of the second comparator is connected with the output end of the flag _ vdd2 on; wherein the flag _ vdd2on output terminal is connected to the en _ in input terminal of the input driver.
In one possible embodiment, the input driver includes a level shifter path and a buffer path;
the levelshifter path is used for converting a vdd2 voltage domain input signal into a vdd1 voltage domain output signal when k · vdd1 is greater than vdd2 and is less than or equal to vdd1, so that the first chip works in a normal working mode in which the second chip is powered on; the buffer path is used for converting a vdd2 voltage domain input signal into a vdd1 voltage domain output signal when vdd1 < vdd2 so as to enable the first chip to work in the normal working mode; k is a positive number less than 1.
In one possible embodiment, the levelshifter path is configured such that:
the signal input end of the input driver is connected with the grid electrode of the first MOS tube through the first phase inverter and the second phase inverter in sequence; the second MOS tube and the third MOS tube are connected in parallel between the vdd1 and the source electrode of the first MOS tube; the drain electrode of the first MOS tube is grounded;
the fourth MOS tube and the fifth MOS tube are connected between the drain electrode of the sixth MOS tube and the ground in parallel; the source electrode of the sixth MOS tube is connected with vdd 1; the grid electrode of the sixth MOS tube is connected with the source electrode of the first MOS tube; the grid electrode of the third MOS tube is connected with the drain electrode of the sixth MOS tube; the grid electrode of the fourth MOS tube is connected with the output end of the first phase inverter;
the seventh MOS tube, the eighth MOS tube, the ninth MOS tube and the tenth MOS tube are connected between the vdd1 and the ground in series; the drain electrode of the sixth MOS tube is respectively connected with the grid electrode of the eighth MOS tube and the grid electrode of the ninth MOS tube;
the en _ in input end of the input driver is connected with the grid electrode of the second MOS tube; the en _ in input end is also connected with a grid electrode of a fifth MOS tube through a third inverter;
the en _ ls input end of the input driver is connected with the grid electrode of the seventh MOS tube; the en _ ls input end is also connected with a grid electrode of a tenth MOS tube through a fourth inverter;
the drain electrode of the eighth MOS tube is connected with the signal output end of the input driver through a fifth inverter;
the channel types of the first MOS tube, the fourth MOS tube, the fifth MOS tube, the ninth MOS tube and the tenth MOS tube are the same; the channel types of the second MOS tube, the third MOS tube, the sixth MOS tube, the seventh MOS tube and the eighth MOS tube are the same; the channel types of the first MOS tube and the second MOS tube are different.
In one possible embodiment, in the buffer path:
an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube and a fourteenth MOS tube are connected between vdd2 and the ground in series; the signal input end of the input driver is respectively connected with the grid electrode of the twelfth MOS tube and the grid electrode of the thirteenth MOS tube;
the en _ ls input end is also connected with a grid electrode of an eleventh MOS tube; the en _ ls input end is also connected with a grid electrode of a fourteenth MOS tube through a fourth inverter;
the drain electrode of the twelfth MOS tube is connected with the signal output end of the input driver through a fifth inverter;
the channel types of the eleventh MOS tube and the twelfth MOS tube are the same as the channel type of the second MOS tube; the channel type of the thirteenth MOS tube and the channel type of the fourteenth MOS tube are the same as the channel type of the first MOS tube.
In a possible embodiment, the input driver is further provided with an internal pull-down mode or an internal pull-up mode for outputting a pull-down signal or a pull-up signal when vdd2 is ≦ k · vdd1, so that the first chip operates in a default operating mode in which the second chip is not normally powered on.
In one possible embodiment, the first chip is connected to the second chip through an output driver.
In one possible embodiment, the output driver includes a sixth inverter and a seventh inverter;
and the signal input end of the output driver is connected with the signal output end of the output driver through a sixth inverter and a seventh inverter in sequence.
In a second aspect, an embodiment of the present invention provides a multi-chip packaged microsystem, including: the multi-chip package structure of any one of the first aspect.
Compared with the prior art, the utility model, following advantage and beneficial effect have:
the utility model provides a working voltage monitor can obtain the working voltage comparative result of first working voltage vdd1 and second working voltage vdd2 to can control the mode of operation of input driver according to this working voltage comparative result, so that first chip work with the mode of operation that the mode of operation of input driver suited has reduced the interference of the condition such as operating condition is incorrect, electric leakage to tests such as chip sieve piece, has improved the system function debugging efficiency of multi-chip package.
Drawings
In order to more clearly illustrate the embodiments of the present specification or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present specification, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a typical microsystem consisting of a 3D multi-chip package;
FIG. 2 is a schematic diagram of the microsystem of FIG. 1;
fig. 3 is a flowchart of a method for controlling a chip operating mode in a multi-chip package according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a multi-chip package structure according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a multi-chip package structure according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of the connection of the voltage monitor for operation of vdd2 in the multi-chip package configuration shown in FIG. 5;
FIG. 7 is a schematic diagram of the connections of the input drivers in the multi-chip package structure shown in FIG. 5;
FIG. 8 is a schematic diagram of the connections of the output drivers in the multi-chip package configuration shown in FIG. 5;
FIG. 9 is a schematic diagram of the operation of the multi-chip package structure shown in FIG. 5;
fig. 10 is a block diagram of an embodiment of the present invention further providing a control apparatus for controlling the operating mode of the chip in the multi-chip package.
Description of reference numerals: dieA is a first chip, dieB is a second chip, 100 is a working voltage monitor, 101 is a first comparator, 102 is a second comparator, 103 is a first voltage dividing circuit, 104 is a second voltage dividing circuit, 200 is an input driver, 210 is a levelshifter channel, 211 is a first inverter, 212 is a second inverter, 213 is a third inverter, 214 is a fourth inverter, 215 is a fifth inverter, 220 is a buffer channel, 300 is an output driver, 301 is a sixth inverter, 302 is a seventh inverter, M1 is a first MOS transistor, M2 is a second MOS transistor, M3 is a third MOS transistor, M4 is a fourth MOS transistor, M5 is a fifth MOS transistor, M6 is a sixth MOS transistor, M7 is a seventh MOS transistor, M8 is an eighth MOS transistor, M9 is a ninth MOS transistor, M10 is a tenth MOS transistor, M11 is an eleventh MOS transistor, M12 is a twelfth MOS transistor, M5392 is a fourteenth MOS transistor.
Detailed Description
The technical solution in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by those skilled in the art based on the embodiments of the present invention belong to the protection scope of the embodiments of the present invention.
Fig. 1 is a schematic diagram of a typical microsystem composed of 3D multi-chip packages, which includes 2 chips: the chip dieA and the chip dieB are provided, wherein the working voltages of the two chips are different, and the functions of the chips can be the same or different; the signal interconnection connectors (e.g., through-silicon vias TSV, hybrid Bonding wires, etc.) can achieve electrical connection between dieA and dieB, and the signal interconnection connectors (e.g., common Bonding wires, Solder bumps Solder Bump, etc.) achieve electrical connection between the chip and the chip, and between the chip and the outside through metal wires in the package base substrate.
Since each chip in the multi-chip package operates in a different power domain and implements the same or different functions, each chip requires a suitable input/output circuit (i.e., an InputOutput circuit, hereinafter referred to as an IO circuit) to implement communication between different chips and between the chip and the outside, thereby implementing a complete microsystem function. FIG. 2 is a schematic diagram of the microsystem of FIG. 1, wherein the dieA is composed of a core circuit dieA _ core and an input/output circuit IOA, and implements functions such as control, computation, etc.; a dieB, which is composed of a core circuit dieB _ core and an input/output circuit IOB, and realizes functions such as storage, digital/analog conversion, data exchange and the like; the input/output circuit IOA includes a plurality of output drivers and a plurality of input drivers, the dieA output drivers enhance the driving capability of the signals processed by the dieA _ core and then output the signals to the input drivers of the dieB through the interconnection line 31, the dieA input drivers are vdd 2-vdd 1 level shifters (i.e., levelshifters), and the input vdd2 power domain signals IO _ n are converted to vdd1 power domain and then transmitted to the dieA _ core 121. The dieB on the right side works in a vdd2 power domain and consists of a core circuit dieB _ core and an input and output circuit IOB; the dieB _ core implements its corresponding functions (e.g., storage, digital/analog conversion, data exchange, etc.); the input/output circuit IOB includes a plurality of output drivers and input drivers, the dieB output drivers enhance the driving capability of the signals processed by the dieB _ core and output the signals to the input driver of the dieA11 through the interconnection line 3n, the dieB input drivers are vdd1 to vdd2 level shifters, and the input vdd1 power domain signal IO _1 is converted to a vdd2 power domain and then is transmitted to the dieB _ core.
The utility model discloses a utility model people discover when carrying out the analysis research to the not high technical problem of the system function debugging scheme of multi-chip package among the prior art's efficiency:
before the chip encapsulation, the IO circuit of each chip does not carry out electric connection through the interconnect line, and the input of its IO circuit is in unsettled state, and this operating condition that probably leads to the chip is incorrect, has the electric leakage simultaneously to disturb the test result of chip, be unfavorable for screening bad chip.
Even if one die is not powered on or is not powered on after the packaging of a plurality of chips is finished, the input of the IO circuit in the other die connected with the die is in a floating state, which may cause that the working state of the die is uncertain, and thus, the debugging of the function of the whole system is not facilitated.
The above reasons all affect the efficiency of the system function debugging scheme of multi-chip package in the prior art.
In addition, since each die operates in different power domains, and some dice have a wider range of power supply voltages in different operating modes, an input driver composed of a single level shifter (levelshifter) may not satisfy the requirements of functions and performance in a wide range of power supply voltages at the same time.
Therefore, the utility model discloses hope through the mode of operation of chip in the accurate control multi-chip package, reduce because the improper mode of operation of chip is to the interference of multi-chip package's system function debugging to improve the debugging efficiency of multi-chip package's system function.
Fig. 3 is a flowchart illustrating a method for controlling a chip operation mode in a multi-chip package according to an embodiment of the present invention, which can be applied to a multi-chip package structure described below, and specifically includes steps 11 to 12.
In step 11, the comparison result of the operating voltages of the first operating voltage vdd1 and the second operating voltage vdd2 is obtained.
Wherein vdd1 is the operating voltage of the first chip dieA; vdd2 is the operating voltage of the second chip dieB.
Specifically, the operation voltage comparison operation of the first operation voltage vdd1 and the second operation voltage vdd2 may be implemented based on the operation voltage monitor 100 with a voltage comparison function, specifically including step 21.
And step 21, acquiring the working voltage comparison result according to the output signal of the working voltage monitor 100.
Specifically, the operating voltage monitor 100 may be internally provided with a voltage comparator to implement the operating voltage comparison operation of the first operating voltage vdd1 and the second operating voltage vdd 2.
Of course, the first operating voltage vdd1 and the second operating voltage vdd2 may also be converted into corresponding digital signals, and the magnitudes of the voltages of the two signals are directly used to compare the voltages, and other schemes may also be used to implement the operation of this step based on the purpose of this step, which is not limited herein.
Step 12, controlling the operation mode of the input driver 200 according to the comparison result of the operation voltage, so that the first chip dieA operates in the operation mode corresponding to the operation mode of the input driver 200.
Wherein the second chip dieB is connected to the first chip dieA through the input driver 200.
Specifically, since the input/output lines cannot be directly detected between the first chip dieA and the second chip dieB, the first chip dieA and the second chip dieB may not be electrically connected to each other; even if the first chip dieA and the second chip dieB are electrically connected, the second chip dieB may be in an unpowered state or in an unpowered unfinished state, and at this time, the first chip dieA is prone to leakage, incorrect working state and the like, which affects debugging detection of multi-chip package.
Meanwhile, in some cases, the voltage domain range of the input signal is too wide, and the input driver 200 composed of a single level shifter (levelshifter) may not meet the requirements of both function and performance, so that even if the first chip dieA operates in the normal operation mode, a failure such as performance mismatch may occur.
In this embodiment, the working mode of the first chip dieA is matched with the working mode of the input driver 200, so that the first chip dieA can work in a correct working mode, the first chip dieA is prevented from working in a working mode which does not adapt to the working mode of the input driver 200, interference of incorrect working state, electric leakage and other conditions on the chip probe test is reduced, and the system function debugging efficiency of multi-chip package is improved.
Here, the present embodiment further provides a control scheme of the input driver 200, specifically including step 31 to step 33.
Specifically, when vdd1 and vdd2 satisfy vdd2 is not greater than k · vdd1 in the comparison result of the operating voltages, it indicates that the electrical connection between the first chip dieA and the second chip dieB is abnormal, the second chip dieB is not powered on, or the second chip dieB is not powered on normally, at this time, the input driver 200 is adjusted to the internal pull-down mode or the internal pull-up mode, and directly outputs a pull-down low level signal or a pull-up high level signal to the first chip dieA, so as to trigger the first chip dieA to enter the default operating mode for dealing with the situation that the second chip dieB is not powered on normally.
Specifically, the selection of the k value can be flexibly selected based on the requirements of the actual application scene.
Step 32, if vdd1 and vdd2 in the comparison result of the operating voltages satisfy k · vdd1 < vdd2 > or less than vdd1, controlling the input driver 200 to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal through the levelshifter path 210, so that the first chip dieA operates in a normal operating mode in which the second chip dieB is powered on. Here, the levelshifter path may be a level shifter circuit capable of performing a shift between the vdd1 voltage domain and the vdd2 voltage domain.
Specifically, when vdd1 and vdd2 satisfy k · vdd1 < vdd2 ≦ vdd1 in the operation voltage comparison result, this step directly uses levelshifter path 210 in input driver 200 to convert the vdd2 voltage domain input signal and limit the voltage of the input signal between 0 and vdd 1. The levelshifter path 210 may be implemented by using an existing levelshifter circuit, which is not described herein in detail.
In step 33, if vdd1 and vdd2 in the comparison result of the operating voltages satisfy vdd1 < vdd2, the input driver 200 is controlled to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal through the buffer path 220, so that the first chip dieA operates in the normal operating mode.
Specifically, when vdd1 and vdd2 satisfy vdd1 < vdd2 in the comparison result of the operating voltages, this step directly uses buffer path 220 in input driver 200 to convert the input signal in the vdd2 voltage domain, and limit the voltage of the input signal to be between 0 and vdd 1. The buffer path 220 can be implemented by using an existing buffer circuit, which is not described herein.
In this embodiment, through the cooperation of step 32 and step 33, the vdd2 voltage domain input signal with a wider voltage domain can be adapted, and the adaptability of the chip is improved.
The above method embodiment may be implemented based on any multi-chip package structure described below, and may also be implemented using other multi-chip package structures, which are not limited herein.
Based on the same utility model with the method, the embodiment of the utility model provides a multi-chip packaging structure is still provided, and this multi-chip packaging structure can realize above-mentioned method embodiment. Fig. 4 is a schematic structural diagram of the multi-chip package structure, which includes 2 first chips dieA and second chips dieB for implementing different functions.
The structure further includes: an operating voltage monitor 100, the input terminals of which are respectively connected to the operating voltage vdd1 of the first chip dieA and the operating voltage vdd2 of the second chip dieB, for outputting the operating voltage comparison results of vdd1 and vdd 2; an input driver 200, the input terminal of which is connected to the output terminal of the operating voltage monitor 100, for controlling the operating mode of the input driver 200 according to the operating voltage comparison result, so that the first chip dieA operates in the operating mode corresponding to the operating mode of the input driver 200; wherein the second chip dieB is connected to the first chip dieA through the input driver 200.
Specifically, since the input/output lines cannot be directly detected between the first chip dieA and the second chip dieB, the first chip dieA and the second chip dieB may not be electrically connected to each other; even if the first chip dieA and the second chip dieB are electrically connected, the second chip dieB may be in an unpowered state or in an unpowered unfinished state, and at this time, the first chip dieA is prone to leakage, incorrect working state and the like, which affects debugging detection of multi-chip package.
Meanwhile, in some cases, the voltage domain range of the input signal is too wide, and the input driver 200 composed of a single level shifter (levelshifter) may not meet the requirements of both function and performance, so that even if the first chip dieA operates in the normal operation mode, a failure such as performance mismatch may occur.
In this embodiment, the working mode of the first chip dieA is matched with the working mode of the input driver 200, so that the first chip dieA can work in a correct working mode, interference of the incorrect working state, electric leakage and the like of the first chip dieA on chip screening test is avoided, and the system function debugging efficiency of multi-chip packaging is improved.
In addition, in the present embodiment, through the cooperation of the level shifter path 210 and the buffer path 220, the input signal with the wider voltage domain vdd2 can be adapted, and the adaptive capability of the chip is improved.
Fig. 5 is a schematic structural diagram of a multi-chip package structure according to an embodiment of the present invention, and fig. 6 is a schematic connection diagram of a vdd2 operating voltage monitor in the multi-chip package structure shown in fig. 5. Wherein: the operating voltage monitor 100 is a vdd2 operating voltage monitor, and includes a first voltage dividing circuit 103, a second voltage dividing circuit 104, a first comparator 101, a second comparator 102, an en _ lvsft output terminal, and a flag _ vdd2on output terminal.
The first voltage dividing circuit 103, connected between vdd2 and ground, includes a first voltage dividing point vr _ vdd 2. Fig. 5 illustrates a series connection of two resistors to construct the first voltage divider circuit 103, but other voltage divider circuit implementations may be used.
And the second voltage division circuit 104 is connected between the vdd1 and the ground and comprises a high-voltage division point vrh _ vdd1 and a low-voltage division point vrl _ vdd 1. vrh _ vdd1 is higher than vrl _ vdd1, and fig. 6 shows a series connection of three resistors to form the second voltage divider 104, although other voltage divider implementations may be used.
The first voltage division point vr _ vdd2 is respectively connected to the inverting input terminal of the first comparator 101 and the positive input terminal of the second comparator 102; the high voltage dividing point vrh _ vdd1 is connected to the positive input terminal of the first comparator 101; the low voltage divider point vrl _ vdd1 is connected to the inverting input of the second comparator.
The output end of the first comparator 101 is connected with an en _ lvsft output end, and the en _ lvsft output end can output an en _ lvsft signal; wherein, the en _ lvsft output terminal is connected to the en _ ls input terminal of the input driver 200; the output end of the second comparator 102 is connected with the output end of the flag _ vdd2on, and the output end of the second comparator can output a flag _ vdd2on signal; wherein the flag _ vdd2on output is connected to the en _ in input of the input driver 200.
The en _ lvsft signal is a high level signal or a low level signal, and is specifically determined as a high level signal or a low level signal according to a voltage amplitude of the en _ lvsft signal, where the high level signal is a signal exceeding a high voltage threshold, and the low level signal is a signal lower than a low voltage threshold, for example, when the en _ lvsft signal exceeds 2.2V, the en _ lvsft signal is a high level signal, and when the en _ lvsft signal is lower than 0.5V, the en _ lvsft signal is a low level signal.
In the connection diagram of the vdd2 operation voltage monitor shown in fig. 6, when the voltage at the positive input terminal of the first comparator 101 is greater than the voltage at the negative input terminal thereof, the en _ lvsft signal output by the first comparator 101 is a high level signal; conversely, the en _ lvsft signal output by the first comparator 101 is a low level signal.
The flag _ vdd2on signal is a high level signal or a low level signal, and is specifically determined as a high level signal or a low level signal by using the voltage amplitude of the flag _ vdd2on signal, where the high level signal is a signal exceeding a high voltage threshold, the low level signal is a signal lower than a low voltage threshold, for example, when the flag _ vdd2on signal exceeds 2.2V, the flag _ vdd2on signal is a high level signal, and when the flag _ vdd2on is lower than 0.5V, the flag _ vdd2on signal is a low level signal.
In the connection diagram of the vdd2 operation voltage monitor shown in fig. 6, when the voltage at the positive input terminal of the second comparator 102 is greater than the voltage at the negative input terminal thereof, the flag _ vdd2on signal output by the second comparator 102 is a high level signal; conversely, the flag _ vdd2on signal output by the second comparator 102 is a low signal.
In this embodiment, based on the level of the en _ lvsft signal and the level of the flag _ vdd2on signal, the comparison between vdd1 and vdd2 can be implemented, so as to obtain a specific working voltage comparison result.
Fig. 7 is a schematic connection diagram of an input driver in the multi-chip package structure shown in fig. 5, where the input driver 200 includes a level shifter path 210 and a buffer path 220;
the level shifter path 210 is configured to convert a vdd2 voltage domain input signal into a vdd1 voltage domain output signal when k · vdd1 is greater than vdd2 and is less than or equal to vdd1, so that the first chip dieA operates in a normal operation mode in which the second chip dieB is powered on; the buffer path 220 is used for converting the vdd2 voltage domain input signal into a vdd1 voltage domain output signal when vdd1 < vdd2, so that the first chip dieA operates in a normal operation mode; k is a positive number less than 1.
The input driver 200 is further provided with an internal pull-down mode or an internal pull-up mode for outputting a pull-down signal or a pull-up signal when vdd1 and vdd2 satisfy vdd2 ≦ k · vdd1 in the comparison result of the operating voltages, so that the first chip dieA operates in a default operating mode in which the second chip dieB is not normally powered up.
Specifically, when vdd1 and vdd2 satisfy k · vdd1 < vdd2 ≦ vdd1 in the operation voltage comparison result, this step directly uses levelshifter path 210 in input driver 200 to convert the vdd2 voltage domain input signal and limit the voltage of the input signal between 0 and vdd 1. The levelshifter path 210 may be implemented by using an existing levelshifter circuit, which is not described herein in detail.
Specifically, when vdd1 and vdd2 satisfy vdd1 < vdd2 in the comparison result of the operating voltages, this step directly uses buffer path 220 in input driver 200 to convert the input signal in the vdd2 voltage domain, and limit the voltage of the input signal to be between 0 and vdd 1. The buffer path 220 can be implemented by using an existing buffer circuit, which is not described herein.
Specifically, the value of the k value is related to specific resistance values of voltage dividing resistors in the first voltage dividing circuit 103 and the second voltage dividing circuit 104, and can be flexibly set according to actual needs.
In the levelshifter path 210 of fig. 6: the signal input end of the input driver 200 is connected with the gate of the first MOS transistor M1 through a first inverter 211 and a second inverter 212 in sequence; the second MOS transistor M2 and the third MOS transistor M3 are connected in parallel between vdd1 and the source electrode of the first MOS transistor M1; the drain of the first MOS transistor M1 is grounded.
The fourth MOS transistor M4 and the fifth MOS transistor M5 are connected between the drain of the sixth MOS transistor M6 and the ground in parallel; the source of the sixth MOS transistor M6 is connected with vdd 1; the grid electrode of the sixth MOS transistor M6 is connected with the source electrode of the first MOS transistor M1; the gate of the third MOS transistor M3 is connected to the drain of the sixth MOS transistor M6; the gate of the fourth MOS transistor M4 is connected to the output terminal of the first inverter 211.
A seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9 and a tenth MOS transistor M10 are connected in series between vdd1 and the ground; the drain of the sixth MOS transistor M6 is connected to the gate of the eighth MOS transistor M8 and the gate of the ninth MOS transistor M9, respectively.
The en _ in input end of the input driver 200 is connected with the gate of the second MOS transistor M2; the en _ in input terminal is also connected to the gate of the fifth MOS transistor M5 through the third inverter 213.
The en _ ls input end of the input driver 200 is connected to the gate of the seventh MOS transistor M7; the en _ ls input terminal is also connected to the gate of the tenth MOS transistor M10 through the fourth inverter 214.
The drain of the eighth MOS transistor M8 is connected to the signal output terminal of the input driver 200 through the fifth inverter 215.
The channel types of the first MOS transistor M1, the fourth MOS transistor M4, the fifth MOS transistor M5, the ninth MOS transistor M9 and the tenth MOS transistor M10 are the same; the channel types of the second MOS transistor M2, the third MOS transistor M3, the sixth MOS transistor M6, the seventh MOS transistor M7 and the eighth MOS transistor M8 are the same; the channel types of the first MOS transistor M1 and the second MOS transistor M2 are different. Namely: when the first MOS transistor M1, the fourth MOS transistor M4, the fifth MOS transistor M5, the ninth MOS transistor M9 and the tenth MOS transistor M10 are PMOS transistors, the second MOS transistor M2, the third MOS transistor M3, the sixth MOS transistor M6, the seventh MOS transistor M7 and the eighth MOS transistor M8 are NMOS transistors; when the first MOS transistor M1, the fourth MOS transistor M4, the fifth MOS transistor M5, the ninth MOS transistor M9 and the tenth MOS transistor M10 are NMOS transistors, the second MOS transistor M2, the third MOS transistor M3, the sixth MOS transistor M6, the seventh MOS transistor M7 and the eighth MOS transistor M8 are PMOS transistors.
In the buffer path 220 of fig. 6: an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13 and a fourteenth MOS tube M14 are connected in series between vdd1 and the ground; the signal input end of the input driver 200 is respectively connected with the gate of the twelfth MOS transistor M12 and the gate of the thirteenth MOS transistor M13; the en _ ls input end is also connected with the grid electrode of an eleventh MOS transistor M11; the en _ ls input end is also connected with the gate of the fourteenth MOS transistor M14 through the fourth inverter 214; the drain of the twelfth MOS transistor M12 is connected to the signal output terminal of the input driver 200 through the fifth inverter 215; the channel types of the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are the same as the channel type of the second MOS transistor M2; the channel types of the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14 are the same as the channel type of the first MOS transistor M1.
The first chip dieA is connected to the second chip dieB through the output driver 300.
Specifically, the output driver 300 may be implemented using a buffer circuit.
Here, a typical buffer circuit is provided to implement the output driver 300, as shown in fig. 8, which is a connection diagram of the output driver in the multi-chip package structure shown in fig. 5, specifically:
the output driver 300 includes a sixth inverter 301 and a seventh inverter 302; the signal input terminal of the output driver 300 is connected to the signal output terminal of the output driver 300 via the sixth inverter 301 and the seventh inverter 302 in this order.
To more clearly illustrate the operation process of the multi-chip package structure provided in this embodiment, the operation process of this embodiment is illustrated by taking the multi-chip package structure shown in fig. 5 as an example.
Specifically, the dieA operates in the vdd1 power domain, and the dieA _ core implements its corresponding functions (e.g., control, calculation, etc.); the IO circuit IOA of dieA includes a plurality of output drivers 300, a plurality of input drivers 200, and a vdd2 operating voltage monitor 100; the input terminal in of the output driver 300 is connected to the dieA _ core, the output terminal out is connected to the interconnection line 31, and the signal processed by the dieA _ core is output to the input driver of the dieB through the interconnection line 31 after the driving capability is enhanced; an in input end of the dieA input driver 200 is connected with an interconnection line 3n, an en _ in input end and an en _ ls input end are respectively connected with a flag _ vdd2on output end and an en _ lvsft output end of the vdd2 working voltage monitor 100, an output end is connected with the dieA _ core, and an input vdd2 power domain signal IO _ n is converted into a vdd1 power domain and then is transmitted into the dieA _ core; the pwrdet input of the vdd2 working voltage monitor 100 is connected to the ddeb power supply vdd2 through the power interconnection line 3AB2, and the output signals flag _ vdd2on and en _ lvsft are respectively connected to the en _ in input terminal and en _ ls input terminal of the input driver 200, so as to control the input driver 200 to work in different modes by monitoring the status of vdd 2. The structure of dieB is similar to that of dieA, and will not be described herein.
The working voltage monitor 100 of vdd2 is composed of two groups of resistor voltage dividing strings and two comparators, wherein, vdd1 is used as reference voltage after being subjected to voltage division by the resistor voltage dividing strings, the reference voltage is compared with the voltage dividing value of vdd2 through the comparators to judge the power state of vdd2, and the output signals of the comparator are flag _ vdd2on signal and en _ lvsft signal to control the input driver 200 to work in a proper mode; the input driver 200 is divided into a levelshifter path 210 and a buffer path 220; the output driver 300 is a typical buffer composed of inverters.
As mentioned above, the voltage monitor controls the input driver 200 to operate in different modes by monitoring the state of the power supply of the other side, and as shown in fig. 9, the schematic diagram of the operating principle of the multi-chip package structure shown in fig. 5 mainly includes the following three modes: (the output of the signal from dieA to dieB is similar to the output of the signal from dieB to dieA, and the working process of this embodiment will be described by taking the output of the signal from dieB to dieA as an example)
Mode one, when the supply voltage vdd2 of dieB is lower than k times the supply voltage vdd1 of dieA (where k is constant, for example k is 1/2), the output signal flag _ vdd2on of the vdd2 voltage monitor is low, en _ lvsft is high, indicating that dieB is not connected to dieA (i.e., before multi-chip packaging) or that dieB is not powered up or not powered up, then the input driving circuit internally defaults to pull down (or pull up), and dieA enters its default operating mode.
In the second mode, when the supply voltage vdd2 of dieB is higher than k times the supply voltage vdd1 of dieA and still lower than vdd1, flag _ vdd2on is high, en _ lvsft is high, which indicates that dieB is connected to dieA (i.e. after multi-chip packaging) or that the power-up of dieB is completed, and then the input signal IO _ n of vdd2 power domain is converted into a signal of vdd1 power domain through the levelsfilter channel in the input driver 200 and sent to dieA _ core, and the system enters the normal operation mode.
In the third mode, when the supply voltage vdd2 of dieB is higher than the supply voltage vdd1 of dieA, flag _ vdd2on is high, and en _ lvsft is low, the input signal IO _ n of vdd2 power domain is converted into the signal of vdd1 power domain through the buffer path 220 in the input driver 200 and then sent to the dieA _ core, and the system enters the normal operation mode.
Compared with the prior art, the embodiment has the following advantages and beneficial effects:
1. each die working power supply is connected to the die of the other party through an interconnection line (such as power interconnection lines 3AB1 and 3AB2) so as to monitor the power state of the die of the other party; according to the states of the power supplies, the input driver 200 is automatically controlled to work in a proper mode, so that IO works in a correct state;
2. before multi-Chip packaging, an input driving circuit in an IO circuit is internally pulled down (or pulled up) in a default mode, and when a Chip works in a default determined state, no electric leakage exists, so that bad Chip screening can be conveniently carried out through a Chip Probing test;
3. after the multi-chip is packaged, even if the power-on of a certain die is not carried out or the power-on is not carried out, the IO working state of another die is also determined, and the debugging of the whole system function can be continued;
4. each die works in different voltage domains, the power supply voltage range of some dice under different working modes is wider, and the power supply monitor controls the input driver 200 to select the levelshifter passage 210 or the buffer passage 220 according to the power supply state, so that the requirements of functions and performance can be met at the same time;
5. in the same way, the control scheme can be extended to the second chip;
6. in the same way, the encapsulation scheme can be extended to multiple die, that is, the same or similar connection and IO signal processing mode can be adopted between every two dice.
Based on the same utility model concept with the method, the embodiment of the utility model provides a control device of chip mode among multi-chip package is still provided, as shown in fig. 10 for the device's schematic structure diagram, specifically include:
a first obtaining module 41, configured to obtain an operating voltage comparison result between the first operating voltage vdd1 and the second operating voltage vdd 2; wherein vdd1 is the operating voltage of the first chip dieA; vdd2 is the operating voltage of the second chip dieB;
a first control module 42, configured to control an operating mode of the input driver 200 according to the comparison result of the operating voltages, so that the first chip dieA operates in an operating mode corresponding to the operating mode of the input driver 200; wherein the second chip dieB is connected to the first chip dieA through the input driver 200.
In a possible embodiment, the first obtaining module includes:
and a second obtaining module, configured to obtain the working voltage comparison result according to the output signal of the working voltage monitor 100.
In one possible embodiment, the first control module includes:
a second control module, configured to adjust the input driver 200 to an internal pull-down mode or an internal pull-up mode when vdd1 and vdd2 satisfy vdd2 ≦ k · vdd1 in the comparison result of the operating voltages, so that the first chip dieA operates in a default operating mode where the second chip dieB is not normally powered on; wherein k is a positive number less than 1;
a third control module, configured to control the input driver 200 to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal through a levelshifter path 210 when vdd1 and vdd2 satisfy k · vdd1 < vdd2 ≦ vdd1 in the operation voltage comparison result, so that the first chip dieA operates in a normal operation mode where power on of the second chip dieB is completed;
and a fourth control module, configured to control the input driver 200 to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal through the buffer path 220 when vdd1 and vdd2 satisfy vdd1 < vdd2 in the comparison result of the operating voltages, so that the first chip dieA operates in the normal operating mode.
Based on the same utility model with the method, the embodiment of the utility model provides a still provides a micro-system of multi-chip package, include: a multi-chip package structure as claimed in any preceding claim.
Based on the same utility model concept as the method, the embodiment of the utility model also provides a computer system, including the microsystem of multi-chip package, the microsystem of multi-chip package carries out the step of any one of the above-mentioned method.
The embodiment of the utility model provides an in the technical scheme who provides, following technological effect or advantage have at least:
the embodiment of the utility model provides a working mode according to the working voltage comparison result of first working voltage vdd1 and second working voltage vdd2, control input driver, so that first chip work with the working mode that the working mode of input driver suits has reduced the interference of circumstances such as first chip operating condition is incorrect, the electric leakage to chip probe test, has improved multi-chip package's system function debugging efficiency.
While the preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. A multi-chip package structure, the inside of structure includes first chip and second chip, its characterized in that, the structure still includes:
an operating voltage monitor, the input terminals of which are respectively connected with the operating voltage vdd1 of the first chip and the operating voltage vdd2 of the second chip, for outputting the operating voltage comparison results of vdd1 and vdd 2;
the input end of the input driver is connected with the output end of the working voltage monitor and used for controlling the working mode of the input driver according to the working voltage comparison result so that the first chip works in a working mode which is adaptive to the working mode of the input driver; wherein the second chip accesses the first chip through the input driver.
2. The multi-chip package structure of claim 1, wherein the operating voltage monitor comprises a first voltage divider circuit, a second voltage divider circuit, a first comparator, a second comparator, an en _ lvsft output, and a flag _ vdd2on output;
the first voltage division circuit is connected between the vdd2 and the ground and comprises a first voltage division point;
the second voltage division circuit is connected between the vdd1 and the ground and comprises a high-voltage division point and a low-voltage division point;
the first voltage division point is respectively connected with the reverse input end of the first comparator and the forward input end of the second comparator;
the high-voltage division point is connected with the positive input end of the first comparator;
the low-voltage division point is connected with the reverse input end of the second comparator;
the output end of the first comparator is connected with the en _ lvsft output end; the en _ lvsft output end is connected with the en _ ls input end of the input driver;
the output end of the second comparator is connected with the output end of the flag _ vdd2 on; wherein the flag _ vdd2on output terminal is connected to the en _ in input terminal of the input driver.
3. The multi-chip package structure of claim 2, wherein the input driver includes a level shifter path and a buffer path therein;
the levelshifter path is used for converting a vdd2 voltage domain input signal into a vdd1 voltage domain output signal when k · vdd1 is greater than vdd2 and is less than or equal to vdd1, so that the first chip works in a normal working mode in which the second chip is powered on; the buffer path is used for converting a vdd2 voltage domain input signal into a vdd1 voltage domain output signal when vdd1 < vdd2 so as to enable the first chip to work in the normal working mode; k is a positive number less than 1.
4. The multi-chip package structure of claim 3, wherein in the levelshifter path:
the signal input end of the input driver is connected with the grid electrode of the first MOS tube through the first phase inverter and the second phase inverter in sequence; the second MOS tube and the third MOS tube are connected in parallel between the vdd1 and the source electrode of the first MOS tube; the drain electrode of the first MOS tube is grounded;
the fourth MOS tube and the fifth MOS tube are connected between the drain electrode of the sixth MOS tube and the ground in parallel; the source electrode of the sixth MOS tube is connected with vdd 1; the grid electrode of the sixth MOS tube is connected with the source electrode of the first MOS tube; the grid electrode of the third MOS tube is connected with the drain electrode of the sixth MOS tube; the grid electrode of the fourth MOS tube is connected with the output end of the first phase inverter;
the seventh MOS tube, the eighth MOS tube, the ninth MOS tube and the tenth MOS tube are connected between the vdd1 and the ground in series; the drain electrode of the sixth MOS tube is respectively connected with the grid electrode of the eighth MOS tube and the grid electrode of the ninth MOS tube;
the en _ in input end of the input driver is connected with the grid electrode of the second MOS tube; the en _ in input end is also connected with a grid electrode of a fifth MOS tube through a third inverter;
the en _ ls input end of the input driver is connected with the grid electrode of the seventh MOS tube; the en _ ls input end is also connected with a grid electrode of a tenth MOS tube through a fourth inverter;
the drain electrode of the eighth MOS tube is connected with the signal output end of the input driver through a fifth inverter;
the channel types of the first MOS tube, the fourth MOS tube, the fifth MOS tube, the ninth MOS tube and the tenth MOS tube are the same; the channel types of the second MOS tube, the third MOS tube, the sixth MOS tube, the seventh MOS tube and the eighth MOS tube are the same; the channel types of the first MOS tube and the second MOS tube are different.
5. The multi-chip package structure of claim 4, wherein in the buffer path:
an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube and a fourteenth MOS tube are connected between vdd2 and the ground in series; the signal input end of the input driver is respectively connected with the grid electrode of the twelfth MOS tube and the grid electrode of the thirteenth MOS tube;
the en _ ls input end is also connected with a grid electrode of an eleventh MOS tube; the en _ ls input end is also connected with a grid electrode of a fourteenth MOS tube through a fourth inverter;
the drain electrode of the twelfth MOS tube is connected with the signal output end of the input driver through a fifth inverter;
the channel types of the eleventh MOS tube and the twelfth MOS tube are the same as the channel type of the second MOS tube; the channel type of the thirteenth MOS tube and the channel type of the fourteenth MOS tube are the same as the channel type of the first MOS tube.
6. The multi-chip package structure of claim 3, wherein the input driver further has an internal pull-down mode or an internal pull-up mode for outputting a pull-down signal or a pull-up signal when vdd2 is smaller than or equal to k-vdd 1, so that the first chip operates in a default operating mode where the second chip is not normally powered up.
7. The multi-chip package structure of any one of claims 1-6, wherein the first chip is connected to the second chip through an output driver.
8. The multi-chip package structure of claim 7, wherein the output driver includes a sixth inverter and a seventh inverter;
and the signal input end of the output driver is connected with the signal output end of the output driver through a sixth inverter and a seventh inverter in sequence.
9. A multi-chip packaged microsystem, comprising: a multi-chip package structure as claimed in any one of claims 1 to 8.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113078073A (en) * | 2021-04-28 | 2021-07-06 | 西安紫光国芯半导体有限公司 | Control method and device for chip working mode and multi-chip packaging structure |
| CN115454017A (en) * | 2022-08-02 | 2022-12-09 | 安徽宇升智能装备有限公司 | Automatic test system of household appliance production line industrial acquisition module |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113078073A (en) * | 2021-04-28 | 2021-07-06 | 西安紫光国芯半导体有限公司 | Control method and device for chip working mode and multi-chip packaging structure |
| CN113078073B (en) * | 2021-04-28 | 2025-05-27 | 西安紫光国芯半导体股份有限公司 | A chip operating mode control method, device and multi-chip packaging structure |
| CN115454017A (en) * | 2022-08-02 | 2022-12-09 | 安徽宇升智能装备有限公司 | Automatic test system of household appliance production line industrial acquisition module |
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