CN214228230U - Latch, data operation unit and chip - Google Patents
Latch, data operation unit and chip Download PDFInfo
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- CN214228230U CN214228230U CN202120189190.1U CN202120189190U CN214228230U CN 214228230 U CN214228230 U CN 214228230U CN 202120189190 U CN202120189190 U CN 202120189190U CN 214228230 U CN214228230 U CN 214228230U
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Abstract
The embodiment of the utility model provides a latch, data arithmetic unit and chip, the latch includes: an input terminal for inputting data; a clock signal terminal for providing a clock signal; the latch unit is connected with the input end and used for latching the data input from the input end under the control of a clock signal; the output unit is connected with the latch unit and used for transmitting the data output by the latch unit; a data storage node is arranged between the output unit and the latch unit; an output terminal for reading out data from the output unit; and the electric leakage compensation unit is electrically connected between the data storage node and the output end, and when the latch unit is in a high-impedance state under the control of the clock signal, the electric leakage compensation unit is used for performing electric leakage compensation on the data storage node based on the data output by the output end. The utility model discloses latch can delay the speed of data storage node electric leakage, avoids the problem of data loss in the latch.
Description
Technical Field
The embodiment of the utility model provides a relate to semiconductor device technical field, especially relate to a latch, data arithmetic unit and chip.
Background
A latch is a pulse level sensitive circuit of memory cells that can change state under a specific input pulse level. Latching is the temporary storage of signals to maintain a certain level state. The most important role of the latch is buffering.
Existing latches typically include: the latch unit and the output unit are connected in series. When the latch unit is in a conducting state under the control of the clock signal, the data of the input latch sequentially passes through the latch unit and the output unit and can be directly output from the output end; when the latch unit is in a high-resistance state (off state) under the control of the clock signal, the input terminal cannot continue inputting data, and the parasitic capacitance (gate capacitance) of the transistor in the output unit temporarily stores data at the data storage node between the latch unit and the output unit. In this way, the level state at the data storage node can be maintained based on the charge in the parasitic capacitance, thereby causing the output unit to continue outputting data.
However, the semiconductor element has a leakage current, that is: in the off state, a minute current also exists in the semiconductor element. When the latch unit is in a cut-off state, the leakage phenomenon occurs at the data storage node due to the leakage current in the latch unit, so that the data in the latch is lost.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a latch, data arithmetic unit and chip for delay the speed of electric leakage, avoid the problem that data lost in the latch.
The utility model discloses a first aspect of the embodiment provides a latch, include:
an input terminal for inputting data;
a clock signal terminal for providing a clock signal;
the latch unit is connected with the input end and used for latching the data input from the input end under the control of the clock signal;
the output unit is connected with the latch unit and used for transmitting the data output by the latch unit; a data storage node is arranged between the output unit and the latch unit;
an output terminal for reading out data from the output unit;
and the electric leakage compensation unit is electrically connected between the data storage node and the output end, and when the latch unit is in a high-impedance state under the control of the clock signal, the electric leakage compensation unit is used for performing electric leakage compensation on the data storage node based on the data output by the output end.
Optionally, the leakage compensation unit includes: a first leakage compensation circuit and a second leakage compensation circuit;
one end of the first leakage compensation circuit is connected with the data storage node, and the other end of the first leakage compensation circuit is connected with the output end; when the data storage node is in a high level state, the first leakage compensation circuit is used for performing leakage compensation on the data storage node;
one end of the second leakage compensation circuit is connected with the data storage node, and the other end of the second leakage compensation circuit is connected with the output end; when the data storage node is in a low level state, the second leakage compensation circuit is used for performing leakage compensation on the data storage node.
Optionally, the first leakage compensation circuit includes: a first PMOS transistor and a second PMOS transistor;
the source electrode of the first PMOS transistor is connected with a power supply, and the grid electrode of the first PMOS transistor is connected with the output end; the drain electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor;
the grid electrode of the second PMOS transistor is connected with a power supply; a drain of the second PMOS transistor is connected to the data storage node;
the second leakage compensation circuit includes: a first NMOS transistor and a second NMOS transistor;
the source electrode of the first NMOS transistor is connected with the ground, and the grid electrode of the first NMOS transistor is connected with the output end; the drain electrode of the first NMOS transistor is connected with the source electrode of the second NMOS transistor;
the grid electrode of the second NMOS transistor is connected with the ground; the drain of the second PMOS transistor is connected to the data storage node.
Optionally, the latch unit includes: an inverter and a first transmission gate;
the inverter is connected with the input end and is used for carrying out inverting operation on data input by the input end;
the first transmission gate is connected with the inverter and is used for transmitting the data inverted by the inverter; the first transmission gate is connected to the clock signal terminal, and is configured to control a state of the latch unit, where the state of the latch unit includes: a high resistance state or an on state.
Optionally, the first transmission gate is an anti-leakage device.
Optionally, the latch unit includes: a second transmission gate or a tri-state inverter.
The utility model discloses a second aspect of the embodiment provides a data operation unit, data operation unit includes: at least one latch according to the first aspect above.
The utility model discloses the third aspect of the embodiment provides a chip, the chip includes: at least one data operation unit according to the second aspect.
According to the utility model provides a latch, data arithmetic unit and chip, wherein, the latch includes: an input terminal for inputting data; a clock signal terminal for providing a clock signal; the latch unit is connected with the input end and used for latching the data input from the input end under the control of the clock signal; the output unit is connected with the latch unit and used for transmitting the data output by the latch unit; a data storage node is arranged between the output unit and the latch unit; an output terminal for reading out data from the output unit; and the electric leakage compensation unit is electrically connected between the data storage node and the output end, and when the latch unit is in a high-impedance state under the control of the clock signal, the electric leakage compensation unit is used for performing electric leakage compensation on the data storage node based on the data output by the output end.
The embodiment of the utility model provides an in the latch, when the latch unit is in the high resistance state, can carry out electric leakage compensation to the data storage node through the electric leakage compensation unit of electric connection between data storage node and output to delay the speed of data storage node electric leakage, avoid the problem of data loss in the latch.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1 is a circuit diagram of a latch according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a latch according to a second embodiment of the present invention;
fig. 3 is a circuit diagram of a latch according to a third embodiment of the present invention;
fig. 4 is a circuit diagram of a latch according to a fourth embodiment of the present invention;
fig. 5 is a circuit diagram of a latch according to a fifth embodiment of the present invention;
fig. 6 is a circuit diagram of a latch according to a sixth embodiment of the present invention;
fig. 7 is a schematic structural diagram of a data operation unit according to a seventh embodiment of the present invention;
fig. 8 is a schematic structural diagram of an eighth embodiment of the present invention.
Description of the reference symbols
D: an input end; CLKP, CLKN: a clock signal; 101: latch unit
102: an output unit; s: a data storage node; q, QN: an output end; 103: a leakage compensation unit;
1031: a first leakage compensation circuit; 1032: a second leakage compensation circuit;
1031P 1: a first PMOS transistor in the first leakage compensation circuit;
1031P 2: a second PMOS transistor in the first leakage compensation circuit;
1032N 1: a first NMOS transistor in the second leakage compensation circuit;
1032N 2: a second NMOS transistor in the second leakage compensation circuit;
101P 3: a third PMOS transistor in the latch unit;
101P 4: a fourth PMOS transistor in the latch unit;
101N 3: a third NMOS transistor in the latch unit;
101N4 fourth NMOS transistor in the latch unit;
700: a data operation unit; 701: a control circuit in the data arithmetic unit;
702: an arithmetic circuit in the data arithmetic unit; 703: a latch;
800: a chip; 801: a control unit of the chip.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely configured to illustrate the relevant invention and not to limit the invention. It should be noted that, for convenience of description, only the portions related to the present application are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Referring to fig. 1, fig. 1 is a circuit diagram of a latch according to an embodiment of the present invention, the latch includes: an input end D for inputting data; a clock signal terminal, configured to provide a clock signal, specifically: for providing two clock signals that are in anti-phase with each other: a clock signal CLKP and a clock signal CLKN; a latch unit 101 connected to the input terminal D for latching data input from the input terminal D under the control of the clock signals CLKP and CLKN; the output unit 102 is connected with the latch unit 101 and is used for transmitting the data output by the latch unit 101, and a data storage node S is arranged between the output unit 102 and the latch unit 101; an output terminal Q for reading out data from the output unit 102; the leakage compensation unit 103 is electrically connected between the data storage node S and the output terminal Q, and when the latch unit 101 is in a high impedance state under the control of the clock signal, the leakage compensation unit 103 is configured to perform leakage compensation on the data storage node S based on the data output by the output terminal Q.
The embodiment of the utility model provides an in, output unit 102 is used for transmitting the data of latching unit 101 output, and with output Q and data storage node S shielding isolation, the data of avoiding output Q department exert an influence to data storage node S' S data. The output unit 102 may be any combinational logic device with driving capability, and the specific structure of the output unit 102 is not limited herein. For example, as shown in fig. 1, the output unit 102 may be an inverter to perform an inversion operation on the data output by the latch unit 101 and transmit the inverted data to the output terminal Q; for another example, the output unit 102 may be a buffer formed by two inverters connected in series to transfer data output by the latch unit 101.
Referring to fig. 1, the latch unit 101 may include: an inverter and a first transmission gate; the inverter is connected with the input end D and is used for performing inverting operation on data input by the input end D; the first transmission gate is connected with the inverter and is used for transmitting the data inverted by the inverter; the first transmission gate is connected to the clock signal terminal, and is configured to control a state of the latch unit 101, where the state of the latch unit 101 includes: a high resistance state or an on state.
Specifically, when the latch unit 101 is in a conducting state under the control of the clock signal, the data input from the input terminal D sequentially passes through the inverter in the latch unit 101, the first transmission gate in the latch unit 101, and the output unit 102, and can be directly output from the output terminal Q; when the latch unit 101 is in a high-impedance state (off state) under the control of the clock signal, the input terminal D cannot continue inputting data, and the parasitic capacitance (gate capacitance) of the transistor in the output unit 102 temporarily stores data at the data storage node S, so that the level state at the data storage node S can be maintained based on the charge in the parasitic capacitance, thereby enabling the output unit 102 to continue outputting data.
Referring to fig. 1, the leakage compensation unit 103 may include: a first leakage compensation circuit 1031 and a second leakage compensation circuit 1032; one end of the first leakage compensation circuit 1031 is connected to the data storage node S, and the other end is connected to the output terminal Q; when the data storage node S is in a high level state, the first leakage compensation circuit 1031 is configured to perform leakage compensation on the data storage node S; one end of the second leakage compensation circuit 1032 is connected to the data storage node S, and the other end is connected to the output terminal Q; the second leakage compensation circuit 1032 is configured to perform leakage compensation on the data storage node S when the data storage node S is in a low state.
Further, the first leakage compensation circuit 1031 may include: a first PMOS transistor 1031P1 and a second PMOS transistor 1031P 2; a source of the first PMOS transistor 1031P1 is connected to the power supply, and a gate of the first PMOS transistor 1031P1 is connected to the output terminal Q; a drain of the first PMOS transistor 1031P1 is connected to a source of the second PMOS transistor 1031P 2; a gate of the second PMOS transistor 1031P2 is connected to a power supply; a drain of the second PMOS transistor 1031P2 is connected to the data storage node S; the second leakage compensation circuit 1032 includes: a first NMOS transistor 1032N1 and a second NMOS transistor 1032N 2; the source of the first NMOS transistor 1032N1 is connected to ground, and the gate of the first NMOS transistor 1032N1 is connected to the output; the drain of the first NMOS transistor 1032N1 is connected to the source of the second NMOS transistor 1032N 2; the gate of the second NMOS transistor 1032N2 is connected to ground; the drain of the second PMOS transistor 1032N2 is connected to the data storage node S.
For the sake of understanding, before explaining the leakage compensation process of the latch according to the first embodiment of the present invention, the leakage phenomenon will be explained first:
when only the latch unit 101 and the output unit 102 are included in fig. 1, and the leakage compensation unit 103 is not provided, a leakage phenomenon exists at the data storage node S, and specifically, the leakage phenomenon is divided into two types:
the first leakage phenomenon: when the clock signal CLKP is at a low level, the clock signal CLKN is at a high level, and the data input from the input terminal D is "0", the latch unit 101 is in a conducting state, and the data input from the input terminal D can be normally written into the latch, specifically: the inverter in the latch unit 101 inverts the data "0" input by the input terminal D to obtain data "1", and then sequentially transmits the data "1" to the first transmission gate and the data storage node S, and stores the data "1" in the parasitic capacitance of the transistor in the output unit 102; if the clock signal is inverted, then: CLKP becomes high, CLKN becomes low, and the latch unit 101 becomes high impedance, specifically, referring to fig. 1, the first transmission gate in the latch unit 101 is in off state, at this time, if the input data of the input terminal D changes: when the "0" is changed to "1", the NMOS transistor 101N1 in the inverter is turned on, and since the first transmission gate has a leakage current in the off state and the source of the NMOS transistor 101N1 is grounded, the data "1" at the data storage node S leaks through the first transmission gate and 101N1, and the data "1" at the data storage node S is changed to "0" over time, i.e., a data loss problem occurs.
Second leakage phenomenon: when the clock signal CLKP is at a low level, the clock signal CLKN is at a high level, and the data input from the input terminal D is "1", the latch unit 101 is in a conducting state, and the data input from the input terminal D can be normally written into the latch, specifically: the inverter in the latch unit 101 inverts the data "1" input from the input terminal D to obtain the data "0", and then transmits the data "0" to the node S; if the clock signal is inverted, then: CLKP becomes high, CLKN becomes low, and the latch unit 101 becomes high impedance, specifically, referring to fig. 1, the first transmission gate in the latch unit 101 is in off state, at this time, if the input data of the input terminal D changes: when the "1" is changed to "0", the PMOS transistor 101P1 in the latch unit 101 is turned on, and since the first transmission gate has a leakage current in the off state and the source of the PMOS transistor 101P1 is connected to the power supply, the data "0" at the data storage node S is leaked through the first transmission gate and 101P1, that is: the power supply charges the data storage node S. Over time, data "0" at data storage node S will become "1", i.e., a data loss problem occurs.
The above process is summarized:
the first leakage phenomenon: when the latch unit 101 is changed from the on state to the off state, and the data input by the input end D is changed from "0" to "1", the data storage node S is subjected to electric leakage, the data is changed from "1" to "0", and the data loss problem occurs; second leakage phenomenon: when the latch unit 101 is turned from the on state to the off state, and the data input from the input terminal D is changed from "1" to "0", the leakage occurs at the data storage node S, and the data is changed from "0" to "1", thereby causing a data loss problem.
The following describes the leakage compensation process of the latch according to the first embodiment of the present invention in detail:
for the first leakage phenomenon, the leakage compensation process of the leakage compensation unit 103 in the latch shown in fig. 1 for the data storage node S is as follows:
at the moment when the latch unit 101 changes from the on state to the off state and the data input from the input terminal D changes from "0" to "1", the data at the data storage node S is still "1", and after being inverted by the output unit 102, the data output from the output terminal Q is "0". Since the second PMOS transistor 1031P2 is in a normally-off state, and the first PMOS transistor 1031P1 is turned on at this time, and the source of the first PMOS transistor 1031P1 is connected to the power supply, a pull-up leakage current is formed between the data storage node S and the power supply via the first PMOS transistor 1031P1 and the second PMOS transistor 1031P2, so as to charge the data storage node S for leakage compensation, and delay the leakage speed, so that the data "1" at the data storage node S is not changed, that is, the first leakage compensation circuit 1031 in the leakage compensation unit 103 inputs a weak compensation signal at the data storage node S, so that the data at the data storage node S is always "1". In addition, the compensation signal is obtained based on the leakage current, so the compensation signal is weak and does not influence the normal data writing process of the latch.
For the second leakage phenomenon, the leakage compensation process of the leakage compensation unit 103 in the latch shown in fig. 1 for the data storage node S is as follows:
at the moment when the latch unit 101 changes from the on state to the off state and the data input from the input terminal D changes from "1" to "0", the data at the data storage node S is still "0", and after being inverted by the output unit 102, the data output from the output terminal Q is "1". Since the second NMOS transistor 1032N2 is in a normally-off state, and the first NMOS transistor 1032N1 is turned on at this time, and the source of the first NMOS transistor 1032N1 is connected to ground, a drain current pulled down between the data storage node S and ground is formed through the first NMOS transistor 1032N1 and the second NMOS transistor 1032N2, so as to discharge the data storage node S for leakage compensation, and slow down the leakage speed, so that the data "0" at the data storage node S is not changed, that is, the second leakage compensation circuit 1032 in the leakage compensation unit 103 inputs a weak compensation signal at the data storage node S, so that the data at the data storage node S is always "0". In addition, the compensation signal is obtained based on the leakage current, so the compensation signal is weak and does not influence the normal data writing process of the latch.
Further, in some optional embodiments, a leakage-resistant device may be optionally used as the first transmission gate, so that when the latch unit 101 is in a high-impedance state, the first transmission gate may delay the speed of leakage at the data storage node. Specifically, the leakage-resistant device may be a low-leakage device having a large threshold voltage, or may be a device having a long gate length.
In the latch shown in fig. 1, when the latch unit 101 is in a high impedance state, the leakage compensation unit 103 electrically connected between the data storage node S and the output terminal Q may perform leakage compensation on the data storage node S, so as to avoid the problem of data loss in the latch due to leakage.
Based on the latch provided by the embodiment shown in fig. 1, the present invention also provides another latch. Referring to fig. 2, fig. 2 is a circuit structure diagram of a latch according to a second embodiment of the present invention, in the first leakage compensation circuit 1031 of this embodiment, the connection relationship between the first PMOS transistor 1031P1 and the second PMOS transistor 1031P2 may also be: a source of the first PMOS transistor 1031P1 is connected to a power supply, and a gate of the first PMOS transistor 1031P1 is connected to the power supply; a drain of the first PMOS transistor 1031P1 is connected to a source of the second PMOS transistor 1031P 2; the gate of the second PMOS transistor 1031P2 is connected to the output Q; a drain of the second PMOS transistor 1031P2 is connected to the data storage node S.
Correspondingly, in the second leakage compensation circuit 1032 of the latch shown in fig. 2, the connection relationship between the first NMOS transistor 1032N1 and the second NMOS transistor 1032N2 may be: the source of the first NMOS transistor 1032N1 is connected to ground, and the gate of the first NMOS transistor 1032N1 is connected to ground; the drain of the first NMOS transistor 1032N1 is connected with the source of the second NMOS transistor 1032N 2; the gate of the second NMOS transistor 1032N2 is connected to the output Q; the drain of the second PMOS transistor 1032N2 is connected to the data storage node S.
In the latch shown in fig. 2, the connection relationship of other parts is the same as that of the latch shown in fig. 1, and the same advantageous effects as those of the embodiment shown in fig. 1 can be obtained, and the description is omitted here.
Referring to fig. 3, fig. 3 is a circuit diagram of a latch according to a third embodiment of the present invention, where the latch includes: an input end D for inputting data; a clock signal terminal, configured to provide a clock signal, specifically: for providing two clock signals that are in anti-phase with each other: a clock signal CLKP and a clock signal CLKN; a latch unit 101 connected to the input terminal D for latching data input from the input terminal D under the control of the clock signals CLKP and CLKN; the output unit 102 is connected with the latch unit 101 and is used for transmitting the data output by the latch unit 101, and a data storage node S is arranged between the output unit 102 and the latch unit 101; an output terminal QN for reading out data from the output unit 102; the leakage compensation unit 103 is electrically connected between the data storage node S and the output terminal QN, and when the latch unit 101 is in a high impedance state under the control of the clock signal, the leakage compensation unit 103 is configured to perform leakage compensation on the data storage node S based on the data output by the output terminal QN.
The embodiment of the utility model provides an in, output unit 102 is used for transmitting the data of latching unit 101 output, and with output Q and data storage node S shielding isolation, the data of avoiding output Q department exert an influence to data storage node S' S data. The output unit 102 may be any combinational logic device with driving capability, and the specific structure of the output unit 102 is not limited herein. For example, as shown in fig. 3, the output unit 102 may be an inverter to perform an inversion operation on the data output by the latch unit 101 and transmit the inverted data to the output terminal Q; for another example, the output unit 102 may be a buffer formed by two inverters connected in series to transfer data output by the latch unit 101.
Referring to fig. 3, the latch unit 101 may include: a second transmission gate.
Specifically, when the second transmission gate is in a conducting state under the control of the clock signal, the data input from the input end D sequentially passes through the second transmission gate and the output unit 102, and after being inverted by the output unit 102, the data can be directly output from the output end QN; when the second transmission gate is in a high-impedance state (off state) under the control of the clock signal, the input terminal D cannot continue inputting data, and the parasitic capacitance (gate capacitance) of the transistor in the output unit 102 temporarily stores the data at the data storage node S, so that the level state at the data storage node S can be maintained based on the charge in the parasitic capacitance, thereby enabling the output unit 102 to continue outputting data.
Referring to fig. 3, the leakage compensation unit 103 may include: a first leakage compensation circuit 1031 and a second leakage compensation circuit 1032; one end of the first leakage compensation circuit 1031 is connected to the data storage node S, and the other end is connected to the output terminal QN; when the data storage node S is in a high level state, the first leakage compensation circuit 1031 is configured to perform leakage compensation on the data storage node S; one end of the second leakage compensation circuit 1032 is connected to the data storage node S, and the other end is connected to the output terminal QN; the second leakage compensation circuit 1032 is configured to perform leakage compensation on the data storage node S when the data storage node S is in a low state.
Further, the first leakage compensation circuit 1031 may include: a first PMOS transistor 1031P1 and a second PMOS transistor 1031P 2; a source of the first PMOS transistor 1031P1 is connected to the power supply, and a gate of the first PMOS transistor 1031P1 is connected to the output terminal QN; a drain of the first PMOS transistor 1031P1 is connected to a source of the second PMOS transistor 1031P 2; a gate of the second PMOS transistor 1031P2 is connected to a power supply; a drain of the second PMOS transistor 1031P2 is connected to the data storage node S; the second leakage compensation circuit 1032 includes: a first NMOS transistor 1032N1 and a second NMOS transistor 1032N 2; the source of the first NMOS transistor 1032N1 is connected to ground, and the gate of the first NMOS transistor 1032N1 is connected to the output QN; the drain of the first NMOS transistor 1032N1 is connected to the source of the second NMOS transistor 1032N 2; the gate of the second NMOS transistor 1032N2 is connected to ground; the drain of the second PMOS transistor 1032N2 is connected to the data storage node S.
The following describes in detail the leakage compensation process of the latch according to the third embodiment of the present invention:
at the moment when the latch unit 101 changes from the on state to the off state and the data input from the input terminal D changes from "0" to "1", the data at the data storage node S is still "0", and after being inverted by the output unit 102, the data output from the output terminal QN is "1". Since the second NMOS transistor 1032N2 is in a normally-off state, and the first NMOS transistor 1032N1 is turned on at this time, and the source of the first NMOS transistor 1032N1 is connected to ground, a drain current pulled down between the data storage node S and ground through the first NMOS transistor 1032N1 and the second NMOS transistor 1032N2 is formed, and the data storage node S is discharged to perform the leakage compensation, so that the leakage speed is slowed down, and the data "0" at the data storage node S is not changed, that is, the second leakage compensation circuit 1032 in the leakage compensation unit 103 inputs a weak compensation signal at the data storage node S, so that the data at the data storage node S is always "0". In addition, the compensation signal is obtained based on the leakage current, so the compensation signal is weak and does not influence the normal data writing process of the latch.
At the moment when the latch unit 101 changes from the on state to the off state and the data input from the input terminal D changes from "1" to "0", the data at the data storage node S is still "1", and after being inverted by the output unit 102, the data output from the output terminal QN is "0". Since the second PMOS transistor 1031P2 is in a normally-off state, and the first PMOS transistor 1031P1 is turned on at this time, and the source of the first PMOS transistor 1031P1 is connected to the power supply, a pull-up leakage current is formed between the data storage node S and the power supply via the first PMOS transistor 1031P1 and the second PMOS transistor 1031P2, so as to charge the data storage node S for leakage compensation, and delay the leakage speed, so that the data "1" at the data storage node S is not changed, that is, the first leakage compensation circuit 1031 in the leakage compensation unit 103 inputs a weak compensation signal at the data storage node S, so that the data at the data storage node S is always "1". In addition, the compensation signal is obtained based on the leakage current, so the compensation signal is weak and does not influence the normal data writing process of the latch.
In the latch in the embodiment shown in fig. 3, when the latch unit 101 is in a high impedance state, the leakage compensation unit 103 electrically connected between the data storage node S and the output QN may perform leakage compensation on the data storage node S, so as to avoid the problem of data loss in the latch due to leakage.
Based on the latch provided by the embodiment shown in fig. 3, the present invention also provides another latch. Referring to fig. 4, fig. 4 is a circuit structure diagram of a latch according to a fourth embodiment of the present invention, in the first leakage compensation circuit 1031 of this embodiment, a connection relationship between the first PMOS transistor 1031P1 and the second PMOS transistor 1031P2 may also be: a source of the first PMOS transistor 1031P1 is connected to a power supply, and a gate of the first PMOS transistor 1031P1 is connected to the power supply; a drain of the first PMOS transistor 1031P1 is connected to a source of the second PMOS transistor 1031P 2; a gate of the second PMOS transistor 1031P2 is connected to the output terminal QN; a drain of the second PMOS transistor 1031P2 is connected to the data storage node S.
Correspondingly, in the second leakage compensation circuit 1032 of the latch shown in fig. 4, the connection relationship between the first NMOS transistor 1032N1 and the second NMOS transistor 1032N2 may be: the source of the first NMOS transistor 1032N1 is connected to ground, and the gate of the first NMOS transistor 1032N1 is connected to ground; the drain of the first NMOS transistor 1032N1 is connected with the source of the second NMOS transistor 1032N 2; the gate of the second NMOS transistor 1032N2 is connected to the output QN; the drain of the second PMOS transistor 1032N2 is connected to the data storage node S.
In the latch shown in fig. 4, the connection relationship of other parts is the same as that of the latch shown in fig. 3, and the same advantageous effects as those of the embodiment shown in fig. 3 can be obtained, and the description thereof is omitted.
Referring to fig. 5, fig. 5 is a circuit diagram of a latch according to an embodiment of the present invention, the latch includes: an input end D for inputting data; a clock signal terminal, configured to provide a clock signal, specifically: for providing two clock signals that are in anti-phase with each other: a clock signal CLKP and a clock signal CLKN; a latch unit 101 connected to the input terminal D for latching data input from the input terminal D under the control of the clock signals CLKP and CLKN; the output unit 102 is connected with the latch unit 101 and is used for transmitting the data output by the latch unit 101, and a data storage node S is arranged between the output unit 102 and the latch unit 101; an output terminal Q for reading out data from the output unit 102; the leakage compensation unit 103 is electrically connected between the data storage node S and the output terminal Q, and when the latch unit 101 is in a high impedance state under the control of the clock signal, the leakage compensation unit 103 is configured to perform leakage compensation on the data storage node S based on the data output by the output terminal Q.
The embodiment of the utility model provides an in, output unit 102 is used for transmitting the data of latching unit 101 output, and with output Q and data storage node S shielding isolation, the data of avoiding output Q department exert an influence to data storage node S' S data. The output unit 102 may be any combinational logic device with driving capability, and the specific structure of the output unit 102 is not limited herein. For example, as shown in fig. 5, the output unit 102 may be an inverter to perform an inversion operation on the data output by the latch unit 101 and transmit the inverted data to the output terminal Q; for another example, the output unit 102 may be a buffer formed by two inverters connected in series to transfer data output by the latch unit 101.
Referring to fig. 5, the latch unit 101 may include: a tri-state inverter. Further, the tri-state inverter includes: a third PMOS transistor 101P3, a fourth PMOS transistor 101P4, a third NMOS transistor 101N3, and a fourth NMOS transistor 101N 4; the third PMOS transistor 101P3, the fourth PMOS transistor 101P4, the third NMOS transistor 101N3, and the fourth NMOS transistor 101N4 are sequentially connected in series between the power supply and the ground.
The clock signal terminals are respectively connected to the gate of the fourth PMOS transistor 101P4 and the gate of the third NMOS transistor 101N3, for controlling the state of the latch unit 101, which includes: a high resistance state or an on state; the input terminals are respectively connected to the gate of the third PMOS transistor 101P3 and the gate of the fourth NMOS transistor 101N4, for transmitting the data inputted from the input terminal D to the latch unit 101.
The following describes in detail the leakage compensation process of the latch according to the fifth embodiment of the present invention:
at the moment when the latch unit 101 changes from the on state to the off state and the data input from the input terminal D changes from "0" to "1", the data at the data storage node S is still "1", and after being inverted by the output unit 102, the data output from the output terminal Q is "0". Since the second PMOS transistor 1031P2 is in a normally-off state, and the first PMOS transistor 1031P1 is turned on at this time, and the source of the first PMOS transistor 1031P1 is connected to the power supply, a pull-up leakage current is formed between the data storage node S and the power supply via the first PMOS transistor 1031P1 and the second PMOS transistor 1031P2, so as to charge the data storage node S for leakage compensation, and delay the leakage speed, so that the data "1" at the data storage node S is not changed, that is, the first leakage compensation circuit 1031 in the leakage compensation unit 103 inputs a weak compensation signal at the data storage node S, so that the data at the data storage node S is always "1". In addition, the compensation signal is obtained based on the leakage current, so the compensation signal is weak and does not influence the normal data writing process of the latch.
At the moment when the latch unit 101 changes from the on state to the off state and the data input from the input terminal D changes from "1" to "0", the data at the data storage node S is still "0", and after being inverted by the output unit 102, the data output from the output terminal Q is "1". Since the second NMOS transistor 1032N2 is in a normally-off state, and the first NMOS transistor 1032N1 is turned on at this time, and the source of the first NMOS transistor 1032N1 is connected to ground, a drain current pulled down between the data storage node S and ground is formed through the first NMOS transistor 1032N1 and the second NMOS transistor 1032N2, so as to discharge the data storage node S for leakage compensation, and slow down the leakage speed, so that the data "0" at the data storage node S is not changed, that is, the second leakage compensation circuit 1032 in the leakage compensation unit 103 inputs a weak compensation signal at the data storage node S, so that the data at the data storage node S is always "0". In addition, the compensation signal is obtained based on the leakage current, so that the compensation signal is weak and does not influence the normal data writing process of the memory.
In the latch in the embodiment shown in fig. 5, when the latch unit 101 is in a high impedance state, the leakage compensation unit 103 electrically connected between the data storage node S and the output terminal Q may perform leakage compensation on the data storage node S, so as to avoid the problem of data loss in the latch due to leakage.
In another embodiment of the present invention, the connection relationship between each transistor in the tri-state inverter and the clock control terminal and the input terminal D can also be as follows: clock signal terminals are respectively connected to the gates of the third PMOS transistor 101P3 and the fourth NMOS transistor 101N4 for controlling the states of the latch unit, including: a high resistance state or an on state; the input terminal D is connected to the gate of the fourth PMOS transistor 101P4 and the gate of the third NMOS transistor 101N3, respectively, for transmitting data input from the input terminal D to the latch unit. In this embodiment, the connection relationship of other parts of the latch is the same as the latch shown in fig. 5, and the description thereof is omitted.
In addition, based on the latch provided by the embodiment shown in fig. 5, the present invention also provides another latch. Referring to fig. 6, fig. 6 is a circuit structure diagram of a latch according to a sixth embodiment of the present invention, in the first leakage compensation circuit 1031 of this embodiment, the connection relationship between the first PMOS transistor 1031P1 and the second PMOS transistor 1031P2 may also be: a source of the first PMOS transistor 1031P1 is connected to a power supply, and a gate of the first PMOS transistor 1031P1 is connected to the power supply; a drain of the first PMOS transistor 1031P1 is connected to a source of the second PMOS transistor 1031P 2; the gate of the second PMOS transistor 1031P2 is connected to the output Q; a drain of the second PMOS transistor 1031P2 is connected to the data storage node S.
Correspondingly, in the second leakage compensation circuit 1032 of the latch shown in fig. 6, the connection relationship between the first NMOS transistor 1032N1 and the second NMOS transistor 1032N2 may be: the source of the first NMOS transistor 1032N1 is connected to ground, and the gate of the first NMOS transistor 1032N1 is connected to ground; the drain of the first NMOS transistor 1032N1 is connected with the source of the second NMOS transistor 1032N 2; the gate of the second NMOS transistor 1032N2 is connected to the output Q; the drain of the second PMOS transistor 1032N2 is connected to the data storage node S.
In the latch shown in fig. 6, the connection relationship of other parts is the same as that of the latch shown in fig. 5, and the same advantageous effects as those of the embodiment shown in fig. 5 can be obtained, and the description thereof is omitted.
The embodiment of the utility model provides an in the latch that provides can regard as the standard cell of a customization, realize the storage of data in the general calculation scene. For example: the method can be used as a CPU/a calculation core unit in the CPU and used for data storage in a super-large scale calculation scene; the system can also be used as a calculation processing unit in an AI (Artificial Intelligence) chip for data storage in a high-density calculation scene; the System-level data storage unit can also be used as a System-level computing unit such as a System On Chip (SOC)/Field Programmable Gate Array (FPGA) and the like, and is used for data storage in the scenes such as low power consumption computation and the like.
The embodiment of the utility model provides a still provide a data arithmetic unit, figure 7 is the utility model provides a seven structural schematic diagrams of data arithmetic unit. As shown in fig. 7, the data operation unit 700 includes a control circuit 701, an operation circuit 702, and a plurality of latches 703. The control circuit 701 refreshes data in the latch 703 and reads the data from the latch 703, and the arithmetic circuit 702 performs arithmetic on the read data and outputs an arithmetic result from the control circuit 701.
The embodiment of the utility model provides a still provide a chip, fig. 8 is the utility model provides a chip's in eight structural schematic diagrams. As shown in fig. 8, the chip 800 includes a control unit 801, and one or more data operation units 700. The control unit 801 inputs data to the data operation unit 700 and processes the data output by the data operation unit 700.
The expressions "first", "second", "first" or "second" used in various embodiments of the present disclosure may modify various components regardless of order and/or importance, but these expressions do not limit the respective components. The above description is only configured for the purpose of distinguishing elements from other elements. For example, the first user equipment and the second user equipment represent different user equipment, although both are user equipment. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.
When an element (e.g., a first element) is referred to as being "operably or communicatively coupled" or "connected" (operably or communicatively) to "another element (e.g., a second element) or" connected "to another element (e.g., a second element), it is understood that the element is directly connected to the other element or the element is indirectly connected to the other element via yet another element (e.g., a third element). In contrast, it is understood that when an element (e.g., a first element) is referred to as being "directly connected" or "directly coupled" to another element (a second element), no element (e.g., a third element) is interposed therebetween.
The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be understood by those skilled in the art that the scope of the present invention is not limited to the specific combination of the above-mentioned features, but also covers other embodiments formed by any combination of the above-mentioned features or their equivalents without departing from the spirit of the present invention. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (10)
1. A latch, comprising:
an input terminal for inputting data;
a clock signal terminal for providing a clock signal;
the latch unit is connected with the input end and used for latching the data input from the input end under the control of the clock signal;
the output unit is connected with the latch unit and used for transmitting the data output by the latch unit; a data storage node is arranged between the output unit and the latch unit;
an output terminal for reading out data from the output unit;
and the electric leakage compensation unit is electrically connected between the data storage node and the output end, and when the latch unit is in a high-impedance state under the control of the clock signal, the electric leakage compensation unit is used for performing electric leakage compensation on the data storage node based on the data output by the output end.
2. The latch according to claim 1,
the leakage compensation unit includes: a first leakage compensation circuit and a second leakage compensation circuit;
one end of the first leakage compensation circuit is connected with the data storage node, and the other end of the first leakage compensation circuit is connected with the output end; when the data storage node is in a high level state, the first leakage compensation circuit is used for performing leakage compensation on the data storage node;
one end of the second leakage compensation circuit is connected with the data storage node, and the other end of the second leakage compensation circuit is connected with the output end; when the data storage node is in a low level state, the second leakage compensation circuit is used for performing leakage compensation on the data storage node.
3. The latch of claim 2,
the first leakage compensation circuit includes: a first PMOS transistor and a second PMOS transistor;
the source electrode of the first PMOS transistor is connected with a power supply, and the grid electrode of the first PMOS transistor is connected with the output end; the drain electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor;
the grid electrode of the second PMOS transistor is connected with a power supply; a drain of the second PMOS transistor is connected to the data storage node;
the second leakage compensation circuit includes: a first NMOS transistor and a second NMOS transistor;
the source electrode of the first NMOS transistor is connected with the ground, and the grid electrode of the first NMOS transistor is connected with the output end; the drain electrode of the first NMOS transistor is connected with the source electrode of the second NMOS transistor;
the grid electrode of the second NMOS transistor is connected with the ground; the drain of the second PMOS transistor is connected to the data storage node.
4. The latch of claim 2,
the first leakage compensation circuit includes: a first PMOS transistor and a second PMOS transistor;
the source electrode of the first PMOS transistor is connected with a power supply, and the grid electrode of the first PMOS transistor is connected with the power supply; the drain electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor;
the grid electrode of the second PMOS transistor is connected with the output end; a drain of the second PMOS transistor is connected to the data storage node;
the second leakage compensation circuit includes: a first NMOS transistor and a second NMOS transistor;
the source electrode of the first NMOS transistor is connected with the ground, and the grid electrode of the first NMOS transistor is connected with the ground; the drain electrode of the first NMOS transistor is connected with the source electrode of the second NMOS transistor;
the grid electrode of the second NMOS transistor is connected with the output end; the drain of the second PMOS transistor is connected to the data storage node.
5. The latch according to any one of claims 1 to 3,
the latch unit includes: an inverter and a first transmission gate;
the inverter is connected with the input end and is used for carrying out inverting operation on data input by the input end;
the first transmission gate is connected with the inverter and is used for transmitting the data inverted by the inverter; the first transmission gate is connected to the clock signal terminal, and is configured to control a state of the latch unit, where the state of the latch unit includes: a high resistance state or an on state.
6. The latch of claim 5 wherein the first transmission gate is an anti-leakage device.
7. A latch as claimed in any one of claims 1 to 3, characterized in that said latch unit comprises: a second transmission gate.
8. A latch as claimed in any one of claims 1 to 3, characterized in that said latch unit comprises: a tri-state inverter.
9. A data arithmetic unit comprising interconnected control circuitry, arithmetic circuitry, and a plurality of latches, said latches being as claimed in any one of claims 1 to 8.
10. A chip comprising at least one data arithmetic unit as claimed in claim 9.
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| CN202120189190.1U CN214228230U (en) | 2021-01-21 | 2021-01-21 | Latch, data operation unit and chip |
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| CN202120189190.1U CN214228230U (en) | 2021-01-21 | 2021-01-21 | Latch, data operation unit and chip |
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Effective date of registration: 20240305 Address after: No. 519, 2nd Street, Baiyang Street, Qiantang New District, Hangzhou City, Zhejiang Province, China, 4-1301 Patentee after: Hangzhou Yuanhe Technology Co.,Ltd. Country or region after: China Address before: 100176 room 606c, 6 / F, block B, building 1, yard 19, Ronghua Middle Road, economic development zone, Daxing District, Beijing Patentee before: Beijing Yuanqi Advanced Microelectronics Co.,Ltd. Country or region before: China |