CN213936191U

CN213936191U - Array substrate, display panel and display device

Info

Publication number: CN213936191U
Application number: CN202022780386.6U
Authority: CN
Inventors: 袁永
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2020-11-25
Filing date: 2020-11-25
Publication date: 2021-08-10
Anticipated expiration: 2030-11-25

Abstract

The utility model discloses an array substrate, display panel and display device, array substrate include pixel circuit, and pixel circuit includes first transistor and second transistor, and first transistor includes the first active layer, and the second transistor includes the second active layer, and first active layer and second active layer all include silicon; the array substrate further comprises a first inorganic layer, a second inorganic layer and a first via hole, wherein the first via hole is located above the first active layer and at least penetrates through the second inorganic layer. The first active layer is only subjected to high-temperature processing through the first via hole, so that the concentration of hydrogen ions in the first crystal active layer is smaller than that of hydrogen ions in the second active layer, the performance of the first transistor is ensured to be good, the times of high-temperature processing of the second transistor are reduced, the subthreshold swing of the second transistor is ensured to be small, the turn-off characteristic is good, the leakage current is small, and the overall characteristic of the pixel circuit is ensured to be good.

Description

Array substrate, display panel and display device

Technical Field

The embodiment of the utility model provides a relate to and show technical field, especially relate to an array substrate, display panel and display device.

Background

Organic light emitting display is the mainstream technology of displays such as mobile phones, televisions and computers at present. Compared with the traditional liquid crystal display, the organic light emitting display has the advantages of low energy consumption, low cost, self luminescence, wide viewing angle, high corresponding speed and the like. Therefore, organic light emitting display is becoming mainstream display technology.

Since the organic light emitting display belongs to current driving, a stable current is required to control light emission thereof, and the magnitude and stability of the driving current of the organic light emitting display mainly depend on the driving transistor in the pixel circuit of the organic light emitting display. Therefore, in the related art, a pixel circuit of an organic light emitting display generally includes a driving transistor and a switching transistor, and the driving transistor and the switching transistor may be the same type of transistor. The same process is generally adopted for manufacturing the same type of driving transistor and switching transistor, and the same characteristics are obtained. However, since the driving transistor and the switching transistor have different functions, the driving transistor and the switching transistor manufactured by the same process often cannot meet the actual display requirements.

SUMMERY OF THE UTILITY MODEL

The utility model provides an array substrate, display panel and display device, through add first via hole in array substrate's position that corresponds drive transistor, the first via hole of accessible only carries out the high temperature processing procedure to the active layer of first transistor, guarantees that second transistor turn-off characteristic is good when guaranteeing that first transistor characteristic is good, and the leakage current is little, guarantees that pixel circuit overall characteristic is good.

In a first aspect, an embodiment of the present invention provides an array substrate, including:

a substrate base plate;

a pixel circuit on one side of the substrate, the pixel circuit including a first transistor including a first active layer and a second transistor including a second active layer, the first and second active layers including silicon;

the array substrate further comprises a first inorganic layer and a second inorganic layer which are positioned on one side of the first active layer far away from the substrate, wherein the first inorganic layer is positioned on one side close to the first active layer, and the second inorganic layer is positioned on one side far away from the first active layer;

the array substrate further comprises a first through hole, the first through hole at least penetrates through the second inorganic layer, and the vertical projection of the first active layer on the plane of the substrate covers the vertical projection of one end, close to the first active layer, of the first through hole on the plane of the substrate.

In a second aspect, the embodiment of the present invention further provides a display panel, which includes the array substrate provided in the first aspect.

In a third aspect, the embodiment of the present invention further provides a display device, which includes the display panel provided in the second aspect.

The embodiment of the utility model provides an array substrate includes the pixel circuit, and the pixel circuit includes first transistor and second transistor, and the first active layer in the first transistor and the second active layer in the second transistor all include silicon. Through add first via hole in the array substrate, first via hole runs through at least partial inorganic layer above the first active layer, accessible first via hole only carries out high temperature process to first active layer, so hydrogen ion concentration in the first active layer is less than the hydrogen ion concentration in the second active layer, guarantee that first transistor performance is good on the one hand, on the other hand reduces the high temperature process number of times of second transistor, guarantee that the subthreshold swing of second transistor is less, guarantee that second transistor turn-off characteristic is good, the second transistor leakage current is little, promote pixel circuit's whole work effect, guarantee that pixel circuit overall characteristic is good.

Drawings

Fig. 1 is a schematic structural view of an array substrate in the related art;

FIG. 2 is a diagram illustrating a sub-threshold swing curve of a driving transistor in the related art;

FIG. 3 is a diagram illustrating a sub-threshold swing curve of a switching transistor in the related art;

fig. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;

fig. 10 is a schematic flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the present invention;

FIGS. 11-17 are flow charts of fabrication processes corresponding to the fabrication method provided in FIG. 10;

fig. 18 is a schematic flow chart illustrating another method for manufacturing an array substrate according to an embodiment of the present invention;

FIGS. 19-23 are partial flow diagrams of fabrication processes corresponding to the fabrication method provided in FIG. 18;

fig. 24 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 25 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Since the organic light emitting device is a current driving device, it is general for an array substrate of an organic light emitting display to include both a driving transistor and a switching transistor. Fig. 1 is a schematic structural view of an array substrate in the related art, and as shown in fig. 1, an array substrate 10 includes a driving transistor 11 and a switching transistor 12, the driving transistor 11 includes a first active layer 111, and the switching transistor 12 includes a second active layerThe active layer 121, the first active layer 111, and the second active layer 121 may each include silicon, and optionally, the first active layer 111 and the second active layer 121 may each include polysilicon. For transistors comprising silicon, such as polysilicon transistors, it is generally necessary to repair defects in the active layer by a high temperature process, while the transistor performance is adjusted by a high temperature process to dehydrogenate the active layer. However, the sub-threshold swing of the transistor may be changed by the high temperature process, specifically, fig. 2 is a schematic diagram of a sub-threshold swing curve of a driving transistor in the related art, fig. 3 is a schematic diagram of a sub-threshold swing curve of a switching transistor in the related art, and in combination with fig. 2 and 3, in order to alleviate the problem of display non-uniformity, the sub-threshold swing value of the driving transistor 11 is generally increased by increasing the number of times of the high temperature process (the number of the high temperature process is positively correlated to the sub-threshold swing value). However, for the switching transistor 12, the sub-threshold swing curve of the switching transistor 12 is right-shifted under the same high temperature process times as the driving transistor 11, which results in that the leakage current of the switching transistor 12 reaches 10 when the gate-source voltage difference is zero^-11On the order of magnitude, a high leakage current causes deterioration of the switching characteristics of the switching transistor 12, and particularly in the case of low-frequency driving, a long data refresh period and a long-time leakage current cause deterioration of the stability of the switching transistor. How to ensure the characteristics of the driving transistor and the small leakage current of the switching transistor becomes a technical problem to be solved urgently.

In view of the above technical problem, an embodiment of the present invention provides an array substrate, including a substrate base plate; a pixel circuit on one side of the substrate, the pixel circuit including a first transistor including a first active layer and a second transistor including a second active layer, the first and second active layers both including silicon; the array substrate further comprises a first inorganic layer and a second inorganic layer, wherein the first inorganic layer and the second inorganic layer are positioned on one sides of the first active layers, which are far away from the substrate, the first inorganic layer is positioned on one side close to the first active layers, and the second inorganic layer is positioned on one side far away from the first active layers; the array substrate further comprises a first through hole, the first through hole at least penetrates through the second inorganic layer, and the vertical projection of the first active layer on the plane of the substrate covers the vertical projection of one end, close to the first active layer, of the first through hole on the plane of the substrate. By adopting the technical scheme, the first through hole is additionally arranged in the array substrate and penetrates through at least part of the inorganic layer above the first active layer, and only high-temperature processing can be carried out on the first active layer through the first through hole, so that hydrogen ions in the first active layer escape through the first through hole, the concentration of the hydrogen ions in the first active layer is smaller than that of the hydrogen ions in the second active layer, on one hand, the good performance of the first transistor is ensured, on the other hand, the times of the high-temperature processing of the second transistor are reduced, the small subthreshold swing of the second transistor is ensured, the good turn-off characteristic of the second transistor is ensured, the leakage current of the second transistor is small, the overall working effect of the pixel circuit is improved, and the good overall characteristic of the pixel circuit is ensured.

Above is the core thought of the embodiment of the utility model, and the following will combine the drawings in the embodiment of the utility model to clearly and completely describe the technical scheme in the embodiment of the utility model. Based on the embodiments in the present invention, under the premise that creative work is not done by ordinary skilled in the art, all other embodiments obtained all belong to the protection scope of the present invention.

Fig. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present invention, and as shown in fig. 4, an array substrate 20 according to an embodiment of the present invention includes a substrate 21; a pixel circuit 22 on one side of the substrate 21, the pixel circuit 22 including a first transistor 221 and a second transistor 222, the first transistor 221 including a first active layer 2211, the second transistor 222 including a second active layer 2221, the first active layer 2211 and the second active layer 2221 both including silicon, optionally, the first active layer 111 and the second active layer 121 may both include polysilicon; the array substrate 20 further includes a first inorganic layer 23 and a second inorganic layer 24 on the first active layer 2211 far away from the substrate 21, the first inorganic layer 23 is on the side close to the first active layer 2211, and the second inorganic layer 24 is on the side far away from the first active layer 2211; the array substrate 20 further includes a first via 25, the first via 25 at least penetrates through the second type inorganic layer 24, and a vertical projection of the first active layer 2211 on the plane of the substrate 21 covers a vertical projection of an end of the first via 25 close to the first active layer 2211 on the plane of the substrate 21.

For example, in the array substrate provided by the embodiment of the present invention, the pixel circuit 22 may include two transistors (2T) or seven transistors (7T), the embodiment of the present invention does not limit the specific structure of the pixel circuit 22, and fig. 4 only illustrates two transistors by way of example.

Specifically, as shown in fig. 4, the pixel circuit 22 includes a first transistor 221 and a second transistor 222, wherein the first transistor 221 includes a first active layer 2211, the second transistor 222 includes a second active layer 2221, and the first active layer 2211 and the second active layer 2221 both include Silicon, and optionally both include polysilicon, that is, polysilicon active layers, such as Low Temperature Polysilicon (LTPS) active layers. Further, the array substrate 20 further includes a first inorganic layer 23 and a second inorganic layer 24 located on a side of the first active layer 2211 away from the substrate 21, the first inorganic layer 23 is located on a side close to the first active layer 2211, the second inorganic layer 24 is located on a side away from the first active layer 2211, wherein the first inorganic layer 23 may be one or more inorganic layers, and the second inorganic layer 24 may be one or more inorganic layers, which is not limited in the embodiments of the present invention. On this basis, the array substrate 20 further includes a first via 25, a vertical projection of the first via 25 on the plane of the substrate 21 is located within a coverage of a vertical projection of the first active layer 2211 on the plane of the substrate 21, and the first via 25 at least penetrates through the second type inorganic layer 24, so that a high temperature process can be performed on the first active layer 2211 through the first via 25, and hydrogen ions in the first active layer 2211 can escape through the first via 25. Since the perpendicular projection of the first active layer 2211 on the plane of the substrate base 21 covers the perpendicular projection of one end of the first via 25 near the first active layer 2211 on the plane of the substrate base 21, the process of performing the high temperature process on the first active layer 2211 through the first via 25 does not affect the second active layer 2221, that is, such that the hydrogen ion concentration in the first active layer 2211 is smaller than that in the second active layer 2221, so that the hydrogen content of the second active layer 2221 is not changed or substantially changed while the dehydrogenation of the first active layer 2211 is ensured, the high-temperature process times of the second transistor 222 are reduced while the characteristics of the first transistor 221 are ensured, the subthreshold swing of the second transistor is ensured to be small, the turn-off characteristics of the second transistor are ensured to be good, the leakage current of the second transistor is small, the overall working effect of the pixel circuit is improved, and the overall characteristics of the pixel circuit are ensured to be good.

To sum up, the embodiment of the utility model provides an array substrate, through add first via hole in array substrate, first via hole runs through the at least partial inorganic layer of first active layer top, can only carry out the high temperature processing procedure to first active layer through first via hole, so hydrogen ion in the first active layer escapes through first via hole, make hydrogen ion concentration in the first active layer be less than the hydrogen ion concentration in the second active layer, guarantee first transistor functional well on the one hand, on the other hand reduces the high temperature processing procedure number of times of second transistor, it is less to guarantee the subthreshold swing of second transistor, it is good to guarantee that the second transistor shuts off the characteristic, the second transistor leakage current is little, promote pixel circuit's whole work effect, it is good to guarantee pixel circuit overall characteristic.

On the basis of the above embodiment, the first transistor 221 may be a driving transistor, and the second transistor 222 may be a switching transistor. In general, in one pixel circuit, a transistor whose gate is connected to a scanning signal or a light emission control signal is a switching transistor, a transistor other than the switching transistor in the pixel circuit is a driving transistor, the driving transistor is provided in series on a transmission path of a first power supply signal (PVDD signal), a data signal is written to the gate of the driving transistor, and a gate potential of the driving transistor changes in accordance with the writing of the data signal. The high-temperature process is only carried out on the first active layer in the driving transistor through the first through hole, so that hydrogen ions in the first active layer escape through the first through hole, the concentration of the hydrogen ions in the first active layer is smaller than that of the hydrogen ions in the second active layer, the driving transistor is guaranteed to be good in performance on one hand, the high-temperature process times of the switching transistor are reduced on the other hand, the subthreshold swing of the switching transistor is guaranteed to be small, the switching transistor is guaranteed to be good in turn-off characteristic, the leakage current of the switching transistor is small, the overall working effect of the pixel circuit is improved, and the overall characteristic of the pixel circuit is guaranteed to be good.

In addition to the above embodiments, the first via hole penetrates at least the second type inorganic layer, the first via hole may penetrate only the second type inorganic layer, or the first via hole may penetrate both the second type inorganic layer and the first type inorganic layer, which will be separately described below.

With continuing reference to fig. 4, fig. 4 illustrates an example where the first via 25 penetrates the second inorganic layer 24. As shown in fig. 4, the first via 25 penetrates through the second type inorganic layer 24, so that the first active layer 2211 does not need to be etched to the surface of the first active layer 2211 in the process of preparing the first via 25, and the first active layer 2211 can be free from etching, thereby ensuring that the integrity of the first active layer 2211 is good. Moreover, even if the first via 25 is not etched to the first active layer 2211, hydrogen ions in the first active layer 2211 can also escape through the first via 25, thereby ensuring that the hydrogen ions normally escape on the basis of ensuring that the first active layer 2211 is not etched, and ensuring that the first transistor 221 has good characteristics.

Fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present invention, and fig. 5 illustrates an example in which the first via 25 simultaneously penetrates through the second inorganic layer 24 and the first inorganic layer 23. As shown in fig. 5, the first via 25 penetrates through the second inorganic layer 24 and the first inorganic layer 23 at the same time, and the first via 25 is etched to the surface of the first active layer 2211, so that hydrogen ions in the first active layer 2211 can escape through the first via 25 without hindrance, a hydrogen ion escape channel is smooth, a hydrogen ion escape effect is good, and the first transistor 221 has good characteristics.

With continued reference to fig. 4 and 5, the first transistor 221 further includes a first source 2213 and a first drain 2214, the second transistor 222 further includes a second source 2222 and a second drain 2223, the first source 2213 and the first drain 2214 are electrically connected to the first active layer 2211 through the first source-drain via 27 (the second via 27), respectively, and the second source 2222 and the second drain 2223 are electrically connected to the second source 2221 through the second source-drain via 28 (the third via 28), respectively. With reference to fig. 4 and fig. 5, no matter whether the first via 25 only penetrates through the second type inorganic layer 24 or whether the first via 25 simultaneously penetrates through the second type inorganic layer 24 and the first type inorganic layer 23, in a direction perpendicular to the substrate base 21, the depth of the first via 25 is smaller than that of the first source/drain via 27 and the second source/drain via 28, that is, one end of the first via 25, which is far away from the substrate base 21, is closer to the substrate base 21 and the first active layer 2211 than one end of the first source/drain via 27 and the second source/drain via 28, which is far away from the substrate base 21.

Fig. 6 is a schematic structural diagram of another array substrate provided in an embodiment of the present invention, fig. 7 is a schematic structural diagram of another array substrate provided in an embodiment of the present invention, and as shown in fig. 6 and fig. 7, the pixel circuit 22 provided in an embodiment of the present invention may further include a third transistor 223, the third transistor 223 includes a third active layer 2231, the third active layer 2231 includes an oxide semiconductor, that is, is an oxide semiconductor active layer, and the third active layer 2231 is located on a side of the first active layer 2211 away from the substrate 21; the first and second

inorganic layers

23 and 24 are disposed between the film layer where the first active layer 2211 is disposed and the film layer where the third active layer 2231 is disposed.

For example, as shown in fig. 6 and fig. 7, the pixel circuit 22 provided in the embodiment of the present invention may further include a third transistor 223, the third transistor 223 includes a third active layer 2231, and the third active layer 2231 may include an oxide semiconductor, that is, an oxide semiconductor active layer, such as an Indium Gallium Zinc Oxide (IGZO) active layer, where a leakage current in the oxide semiconductor transistor is small, so that it can be ensured that the leakage current is small in the operation process of the pixel circuit 22, and the performance of the pixel circuit 22 is good.

Further, because the oxide semiconductor active layer is sensitive to hydrogen ions, the hydrogen ions can cause the performance of the oxide semiconductor transistor to be degraded, therefore, the embodiment of the present invention provides that the first inorganic layer 23 and the second inorganic layer 24 are located between the film layer where the first active layer 2211 is located and the film layer where the third active layer 2231 is located, and in the actual manufacturing process, the third transistor 223 is manufactured on the side of the second inorganic layer 24 away from the substrate base plate 21 by forming the first via hole 25 penetrating through the second inorganic layer 24 at least, and after the high temperature manufacturing process is performed on the first active layer 2211 through the first via hole 25, the hydrogen ions escaping from the high temperature manufacturing process of the first active layer 2211 do not affect the third active layer 2231, thereby ensuring that the performance of the third transistor 223 is excellent.

Optionally, as shown in fig. 6 and fig. 7, the pixel circuit 22 provided in the embodiment of the present invention may further include a capacitor 224, where the capacitor 224 includes a first capacitor substrate 2241 and a second capacitor substrate 2242 disposed opposite to each other; the first transistor 221 may further include a first gate 2212 located on a side of the first active layer 2211 away from the substrate base 21, the first capacitor base 2241 is disposed on the same layer as the first gate 2212, and the second capacitor base 2242 is located on a side of the first capacitor base 2241 away from the substrate base 21; the array substrate 20 may further include a first insulating layer 31 between the first active layer 2211 and the first gate 2212, a second insulating layer 32 between the first gate 2212 and the second capacitor substrate 2242, and a third insulating layer 33 between the second capacitor substrate 2242 and the third active layer 2231; at least one of the first, second, and third insulating

layers

31, 32, and 33 is a silicon nitride layer, and the first via 25 penetrates the silicon nitride layer.

Illustratively, the pixel circuit 22 may further include a capacitor 224, and the capacitor 224 may serve as a storage element to ensure that the gate potential of the first transistor 221 is stable. Specifically, the capacitor 224 may include a first capacitor base plate 2241 and a second capacitor base plate 2242, wherein the first capacitor base plate 2241 may be disposed on the same layer as the first gate 2212 of the first transistor 221, and the second capacitor base plate 2242 is located on a side of the first gate 2212 away from the substrate base plate 21, where fig. 6 and fig. 7 illustrate that the first gate 2212 is multiplexed as the first capacitor base plate 2241, so that the preparation processes of the first gate 2212 and the first capacitor base plate 2241 are simple while the film layer structure of the array base plate 20 is ensured to be simplified.

On this basis, the array substrate 20 may further include a first insulating layer 31 between the first active layer 2211 and the first gate 2212, a second insulating layer 32 between the first gate 2212 and the second capacitor substrate 2242, a third insulating layer 33 between the second capacitor substrate 2242 and the third active layer 2231, wherein the first insulating layer 31 may be the first-type inorganic layer 23, the second insulating layer 32 and the third insulating layer 33 may be the second-type inorganic layer 24, alternatively, the first insulating layer 31 and the second insulating layer 32 are the first inorganic layer 23, and the third insulating layer 33 is the second inorganic layer 24, which is not limited in the embodiments of the present invention, fig. 6 and 7 illustrate only the first insulating layer 31 as the first inorganic layer 23, and the second insulating layer 32 and the third insulating layer 33 as the second inorganic layer 24. Since the silicon nitride layer has a strong blocking effect on hydrogen ion escape, when at least one of the first insulating layer 31, the second insulating layer 32 and the third insulating layer 33 is a silicon nitride layer, the first via hole 25 penetrates through the silicon nitride layer, so that a smooth hydrogen ion escape channel is ensured, hydrogen ions in the first active layer 2211 can smoothly escape, and the first active layer 2211 is ensured to have excellent performance.

Specifically, as shown in fig. 6, the second insulating layer 32 and/or the third insulating layer 33 in fig. 6 may be a silicon nitride layer, and the first via 25 penetrates through the silicon nitride layer; as shown in fig. 7, at least one of the first insulating layer 31, the second insulating layer 32, or the third insulating layer 33 in fig. 7 may be a silicon nitride layer, and the first via hole 25 penetrates through the silicon nitride layer to ensure a smooth hydrogen ion escape channel and ensure that hydrogen ions in the first active layer 2211 can escape smoothly.

As a possible implementation manner, with continuing reference to fig. 4, 5, 6 and 7, the array substrate 20 provided in the embodiments of the present invention may further include a third inorganic layer 26 located on a side of the second inorganic layer 24 away from the substrate 21, and the third inorganic layer 26 may include multiple third inorganic layers, where the third inorganic layer located on a side of the second inorganic layer 24 covers the second inorganic layer 24 and fills the first via 25.

For example, after the first active layer 2211 is subjected to a high-temperature process through the first via 25, the third inorganic layer near the second inorganic layer 24 may fill the first via 25, so that there is no floating unfilled region in the array substrate 20, and the structure of the array substrate 20 is stable.

As a possible implementation manner, with continuing reference to fig. 6 and 7, the array substrate 20 provided in the embodiment of the present invention may further include a second via 27 and a third via 28, where the second via 27 is the first source/drain via 27, the third via 28 is the second source/drain via 28, and the second via 27 and the third via 28 both penetrate through the first type inorganic layer 23, the second type inorganic layer 24, and the third type inorganic layer 26; the vertical projection of the second via hole 27 on the plane of the substrate base plate 21 at least partially overlaps the vertical projection of the first via hole 25 on the substrate base plate 21, and the vertical projection of the second active layer 2221 on the substrate base plate 21 covers the vertical projection of one end of the third via hole 28 close to the second active layer 2221 on the plane of the substrate base plate 21; the array substrate 20 may further include a fourth via 29, where the fourth via 29 penetrates through the third inorganic layer 26 on the side of the third active layer 2231 away from the substrate 21, and a vertical projection of the third active layer 2231 on the substrate 21 covers a vertical projection of one end of the fourth via 29 close to the third active layer 2231 on the plane of the substrate 21; the first transistor 221 further includes a first source 2213 and a first drain 2214, the second transistor 222 further includes a second source 2222 and a second drain 2223, and the third transistor 223 further includes a third source 2232 and a third drain 2233; the first source 2213, the first drain 2214, the second source 2222, the second drain 2223, the third source 2232 and the third drain 2233 are disposed at the same layer; the first source 2213 and the first drain 2214 are electrically connected to the first active layer 2211 through the second via 27; the second source 2222 and the second drain 2223 are electrically connected to the second active layer 2221 through the third via hole 28; the third source 2232 and the third drain 2233 are electrically connected to the third active layer 2231 through the fourth via 29.

Illustratively, with continued reference to fig. 6 and 7, the first transistor 221 further includes a first source 2213 and a first drain 2214, the second transistor 222 further includes a second source 2222 and a second drain 2223, and the third transistor 223 further includes a third source 2232 and a third drain 2233; the first source 2213, the first drain 2214, the second source 2222, the second drain 2223, the third source 2232 and the third drain 2233 are arranged in the same layer, and the film layer structure of the array substrate 20 is simple. Further, the array substrate 20 provided by the embodiment of the present invention may further include a second via 27, a third via 28 and a fourth via 29, where the second via 27 and the third via 28 all penetrate through the first inorganic layer 23, the second inorganic layer 24 and the third inorganic layer 26, and the third via 29 penetrates through the third inorganic layer 26 above the third active layer 2231, so that the first source electrode 2213 and the first drain electrode 2214 are electrically connected to the first active layer 2211 through the second via 27; the second source 2222 and the second drain 2223 are electrically connected to the second active layer 2221 through the third via hole 28; the third source 2232 and the third drain 2233 are electrically connected to the third active layer 2231 through the fourth via 29, so that a complete connection relationship of the first transistor 221, the second transistor 222, and the third transistor 223 is achieved.

Based on the above implementation, as shown in fig. 6 and fig. 7, since the first transistor 221 and the second transistor 222 both include polysilicon active layers, the first active layer 2211 and the second active layer 2221 may be disposed on the same layer, which ensures a simple film structure of the array substrate 20. Further, the first transistor 221 of the present invention may further include a first gate 2212, and the second transistor 222 may further include a second gate 2224, wherein the first gate 2212 and the second gate 2224 may be disposed on the same layer, so as to ensure a simple film structure of the array substrate 20.

On the basis of the above implementation, fig. 8 is a schematic structural diagram of another array substrate provided in the embodiment of the present invention, as shown in fig. 8, the third transistor 223 may be a double-gate transistor, for example, the third transistor 223 may include a third gate 2234 located on a side of the third active layer 2231 away from the substrate 21 and a fourth gate 2235 located on a side of the third active layer 2231 close to the substrate 21, that is, the third transistor 223 is a double-gate transistor with a top-gate and a bottom-gate structure, which ensures that the third transistor 223 has stable performance. It should be noted that, since the third transistor 223 may be an oxide semiconductor transistor, in general, the oxide semiconductor transistor has a relatively large volume, and the third transistor 223 is a double-gate transistor with stacked top and bottom gates, which is beneficial to reducing the volume of the third transistor and further realizing the miniaturization design of the whole pixel circuit.

In addition to the above-mentioned implementation, the first transistor 221 and the second transistor 222 may also be double-gate transistors (not shown), and since the active layers of the first transistor 221 and the second transistor 222 include silicon, such as polysilicon, the first transistor 221 and the second transistor 222 may be polysilicon transistors, for example. Because the polysilicon transistor has a small volume, when the first transistor 221 and the second transistor 222 are both dual-gate transistors, both gates of the first transistor 221 may be both top-gate structures, for example, both gates are located on the side of the first active layer 2211 away from the substrate 21, and both gates of the second transistor 222 may be both top-gate structures, for example, both gates are located on the side of the second active layer 2221 away from the substrate 21; two grids in the first transistor 221 can be located respectively at the both sides of the rete that first active layer 2211 is located, two grids in the second transistor 222 can be located respectively at the both sides of the rete that second active layer 2221 is located, and two grids in the first transistor 221 and two grids in the second transistor 222 can correspond the same floor setting, guarantee array substrate simple structure when guaranteeing that first transistor performance is good (for example, the leakage current is less), the embodiment of the utility model provides a concrete structure to first transistor 221 and second transistor 222 does not prescribe a limit.

Fig. 9 is a schematic structural diagram of another array substrate according to an embodiment of the present invention, as shown in fig. 9, in a direction perpendicular to the substrate base, one end of the first via 25 close to the substrate base 21 is not overlapped with one end of the second via 27 close to the substrate base 21, so that the arrangement position of the second via 27 is not necessarily limited to the arrangement position of the first via 25, the arrangement position of the second via 27 has high flexibility and low process complexity, and the requirement of diversified design of the second via 27 is met.

Based on the inventive concept of the present invention, a method for manufacturing an array substrate is described below, for manufacturing the array substrate described in the above embodiments, and as shown in fig. 4, fig. 5, fig. 6, fig. 7, and fig. 8, the array substrate 20 includes a pixel circuit 22, the pixel circuit 22 includes a first transistor 221 and a second transistor 222, the first transistor 221 includes a first active layer 2211, the second transistor 222 includes a second active layer 2221, and the first active layer 2211 and the second active layer 2221 both include silicon. Fig. 10 is a schematic flow chart of a method for manufacturing an array substrate according to an embodiment of the present invention, and as shown in fig. 10, the method for manufacturing an array substrate includes:

and S110, providing a substrate base plate.

As shown in fig. 11, the substrate 21 may be a flexible substrate or a rigid substrate, which is not limited in the embodiments of the present invention. When the substrate 21 is a flexible substrate, the substrate 21 may include a flexible layer, such as Polyimide (PI), or may include two layers of Polyimide (PI), which is not limited herein.

And S120, preparing a first active layer and a second active layer on one side of the substrate.

As shown in fig. 12, the first active layer 2211 and the second active layer 2221 each include silicon, for example, each include polycrystalline silicon, which is a polysilicon active layer, for example, a low temperature polysilicon active layer.

S130, preparing a first inorganic layer on one side of the first active layer far away from the substrate base plate.

As shown in fig. 13, the first type inorganic layer 23 covers the first active layer 2211 and the second active layer 2221, and the first type inorganic layer 23 may include one or more inorganic layers, and fig. 13 illustrates only an example in which the first type inorganic layer 23 includes one inorganic layer.

S140, a first heating process is carried out on the first active layer through the first inorganic layer.

As shown in fig. 14, a first heating process is performed on the first active layer 2211 and the second active layer 2221 through the first inorganic layer 23 to activate the first active layer 2211 and the second active layer 2221 to repair defects.

S150, preparing a second inorganic layer on the side, away from the substrate, of the first inorganic layer.

As shown in fig. 15, the second inorganic layer 24 is located on the side of the first inorganic layer 23 away from the base substrate 21, and the second inorganic layer 24 covers the first inorganic layer 23. Further, the second inorganic layer 24 may include one or more inorganic layers, and fig. 15 only illustrates that the second inorganic layer 24 includes two inorganic layers.

Further, as shown in fig. 15, the first gate 2212 of the first transistor 221, the second gate 2224 of the second transistor 222, and the capacitor structure 224 may be simultaneously fabricated while fabricating the second type of inorganic layer, where the capacitor structure 224 includes a first capacitor substrate 2241 and a second capacitor substrate 2242, where the first capacitor substrate 2241 and the first gate 2212 are disposed in the same layer, and fig. 15 illustrates an example where the first gate 2212 is multiplexed as a first capacitor substrate 2341.

S160, preparing a first through hole, wherein the first through hole at least penetrates through the second inorganic layer, and the vertical projection of the first active layer on the plane of the substrate base plate covers the vertical projection of one end, close to the first active layer, of the first through hole on the plane of the substrate base plate.

As shown in fig. 16, the first via 25 is formed above the corresponding area of the first active layer 2211, that is, the vertical projection of the first active layer 2211 on the plane of the substrate base 21 covers the vertical projection of the end of the first via 25 close to the first active layer 2211 on the plane of the substrate base 21. Further, the first via 25 penetrates at least the second type inorganic layer 24, and fig. 16 only illustrates an example in which the first via 25 penetrates the second type inorganic layer 24.

S170, performing a second heating process on the first active layer through the first via hole to make the concentration of hydrogen ions in the first active layer smaller than that in the second active layer.

As shown in fig. 17, when the first active layer 2211 is subjected to the second heating process through the first via hole 25, hydrogen ions in the first active layer 2211 are removed through the first via hole 25, so as to ensure that the concentration of hydrogen ions in the first active layer 2211 is less than that of hydrogen ions in the second active layer 2221, thereby ensuring that the first transistor 221 has good performance, the second transistor 222 has a small sub-threshold swing, and the second transistor 222 has good turn-off characteristics.

In summary, in the above method for manufacturing an array substrate, the first high temperature process is performed on the first active layer and the second active layer to eliminate the defects in the first active layer and the second active layer; and then, at least preparing a first via hole in the second inorganic layer, wherein the first via hole penetrates through at least part of the inorganic layer above the first active layer, performing a second high-temperature process on the first active layer through the first via hole, and hydrogen ions in the first active layer escape through the first via hole, so that the concentration of the hydrogen ions in the first active layer is less than that of the hydrogen ions in the second active layer, thereby ensuring good performance of the first transistor on one hand, reducing the times of the high-temperature process of the second transistor on the other hand, ensuring small subthreshold swing of the second transistor, ensuring good turn-off characteristic of the second transistor, reducing leakage current of the second transistor, improving the overall working effect of the pixel circuit and ensuring good overall characteristic of the pixel circuit.

On the basis of the preparation method, preparing a first via hole, wherein the first via hole at least penetrates through the second inorganic layer, and the method comprises the following steps: and preparing a first via hole, wherein the first via hole penetrates through the second inorganic layer.

Illustratively, as shown in fig. 16, the first via 25 penetrates through the second-type inorganic layer 24, so that during the process of preparing the first via 25, it is not necessary to etch to the surface of the first active layer 2211, and the first active layer 2211 may be free from etching, thereby ensuring that the integrity of the first active layer 2211 is good. Moreover, even if the first via 25 is not etched to the first active layer 2211, hydrogen ions in the first active layer 2211 can also escape through the first via 25, thereby ensuring that the hydrogen ions normally escape on the basis of ensuring that the first active layer 2211 is not etched, and ensuring that the first transistor 221 has good characteristics.

On the basis of the preparation method, preparing a first via hole, wherein the first via hole at least penetrates through the second inorganic layer, and the method comprises the following steps: and preparing a first via hole, wherein the first via hole penetrates through the second inorganic layer and the first inorganic layer.

Illustratively, the first via hole penetrates through the second inorganic layer and the first inorganic layer simultaneously, and the first via hole is etched to the surface of the first active layer, so that hydrogen ions in the first active layer can escape through the first via hole without hindrance, a hydrogen ion escape channel is ensured to be unobstructed, a hydrogen ion escape effect is good, and the first transistor is ensured to have excellent characteristics.

On the basis of the above manufacturing method, the pixel circuit further includes a third transistor, the third transistor includes a third active layer, the third active layer includes an oxide semiconductor, that is, the third active layer is an oxide semiconductor active layer, correspondingly, fig. 18 is a schematic flow chart of another manufacturing method of the array substrate provided in the embodiment of the present invention, and as shown in fig. 18, the manufacturing method of the array substrate includes:

s210, providing a substrate base plate.

As shown with continued reference to fig. 11.

S220, preparing a first active layer and a second active layer on one side of the substrate.

With continued reference to fig. 12.

And S230, preparing a first inorganic layer on one side of the first active layer far away from the substrate base plate.

As shown with continued reference to fig. 13.

S240, a first heating process is carried out on the first active layer through the first inorganic layer.

As shown with continued reference to fig. 14.

And S250, preparing a second inorganic layer on the side, away from the substrate, of the first inorganic layer.

As shown with continued reference to fig. 15.

S260, preparing a first through hole, wherein the first through hole at least penetrates through the second inorganic layer, and the vertical projection of the first active layer on the plane of the substrate base plate covers the vertical projection of one end, close to the first active layer, of the first through hole on the plane of the substrate base plate.

Continuing with fig. 16.

S270, performing a second heating process on the first active layer through the first via hole to make the concentration of hydrogen ions in the first active layer smaller than that in the second active layer.

As shown with continued reference to fig. 17.

And S280, preparing a third active layer on the side, away from the substrate, of the second inorganic layer.

Illustratively, before, during or after the third active layer is prepared, a third inorganic layer is prepared on the side of the second inorganic layer far away from the substrate base plate, the third inorganic layer comprises a plurality of third inorganic layers, and the third inorganic layer on the side close to the second inorganic layer covers the second inorganic layer and fills the first via hole.

The third type of inorganic layer including a plurality of third inorganic layers, and the third active layer is prepared simultaneously with the preparation of the plurality of third inorganic layers will be described as an example.

As shown in fig. 19, a third inorganic layer is prepared on the side of the second type inorganic layer 24 away from the base substrate 21, and the third inorganic layer fills the first via 25. The first via hole 25 is filled with the third inorganic layer close to one side of the second inorganic layer 24, so that no suspension unfilled region exists in the array substrate 20, and the structural stability of the array substrate 20 is ensured.

As shown in fig. 20, a third active layer 2231 is prepared on a side of the layer of the third inorganic layer remote from the base substrate 21. The third active layer 2231 may include an oxide semiconductor, that is, an oxide semiconductor active layer, such as an Indium Gallium Zinc Oxide (IGZO) active layer, and a leakage current in the oxide semiconductor transistor is small, which may ensure that a leakage current in the operation process of the pixel circuit 22 is small, and ensure that the performance of the pixel circuit 22 is good.

S290, preparing a second via hole, a third via hole and a fourth via hole.

As shown in fig. 21, the second via hole 27 and the third via hole 28 each penetrate the first type inorganic layer 23, the second type inorganic layer 24, and the third type inorganic layer 26; the vertical projection of the second via 27 on the plane of the substrate base 21 at least partially overlaps the vertical projection of the first via 25 on the substrate base 21, and the vertical projection of the second active layer 2221 on the substrate base 21 covers the vertical projection of one end of the third via 28 close to the second active layer 2221 on the plane of the substrate base 21. Alternatively, the second via 27 and the third via 28 may be simultaneously prepared using the same mask process.

As shown in fig. 22, the fourth via 29 penetrates through the third inorganic layer 26 on the side of the third active layer 2231 away from the substrate base 21, and a vertical projection of the third active layer 2231 on the substrate base 21 covers a vertical projection of one end of the fourth via 29 close to the third active layer 2231 on the plane of the substrate base 21.

It should be noted that, in the preparation method, the preparation sequence of the second via, the third via and the fourth via is not limited, and the fourth via may be prepared after the second via and the third via are prepared, or the second via and the third via may be prepared after the fourth via is prepared.

S300, preparing a first source electrode and a first drain electrode of the first transistor, a second source electrode and a second drain electrode of the second transistor and a third source electrode and a third drain electrode of the third transistor on the side, away from the substrate base plate, of the third inorganic layer.

As shown in fig. 23, the first source 2213 and the first drain 2213 are electrically connected to the first active layer 2211 through the second via 27; the second source 2222 and the second drain 2223 are electrically connected to the second active layer 2221 through the third via hole 28; the third source 2232 and the third drain 2233 are electrically connected to the third active layer 2231 through the fourth via 29, so that a complete connection relationship of the first transistor 221, the second transistor 222, and the third transistor 223 is achieved.

On the basis of the above manufacturing method, the manufacturing of the first active layer and the second active layer on the substrate base plate side may include:

by adopting the same mask process, the first active layer 2211 and the second active layer 2221 are prepared on one side of the substrate base plate 21, and the first active layer 2211 and the second active layer 2221 are arranged at the same layer, so that the preparation processes of the first active layer 2211 and the second active layer 2221 are simple.

Further, the preparation method can also comprise the following steps:

and preparing a first grid on one side of the first active layer far away from the substrate base plate and a second grid on one side of the second active layer far away from the substrate base plate by adopting the same mask process, wherein the first grid and the second grid are arranged on the same layer.

With reference to fig. 15, the first gate 2212 and the second gate 2224 are prepared by using the same mask process, and the first gate 2212 and the second gate 2224 can be disposed at the same layer, so as to ensure a simple film structure of the array substrate 20.

Based on the same utility model discloses think, the embodiment of the utility model provides a display panel is still provided, including any above-mentioned embodiment array substrate, consequently this display panel also has the technological effect that array substrate that above-mentioned embodiment provided had, and the same part can refer to the explanation to array substrate in the above and understand, does not repeated hereafter.

Exemplarily, the display panel 40 may be an Organic Light Emitting Diode (OLED) display panel, as shown in fig. 24, and the OLED display panel 40 includes an array substrate 20 and an OLED 30. Further, the display panel may also be other types of display panels known to those skilled in the art, such as a micro light emitting diode display panel, which is not limited by the embodiment of the present invention.

Based on same utility model design, the embodiment of the utility model provides a still provides a display device, and this display device includes any kind of display panel that above-mentioned embodiment provided. Illustratively, referring to fig. 25, the display device 50 includes a display panel 40. Therefore, the display device also has the advantages of the display panel and the array substrate in the above embodiments, and the same points can be understood by referring to the above explanation of the display panel and the array substrate, which is not repeated herein.

The embodiment of the present invention provides a display device 50, which can be a mobile phone as shown in fig. 25, and also can be any electronic product with a display function, including but not limited to the following categories: TV set, notebook computer, desktop display, panel computer, digital camera, intelligent bracelet, intelligent glasses, vehicle-mounted display, industrial control equipment, medical display screen, touch interaction terminal etc. the embodiment of the utility model provides a do not do special restriction to this.

It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.

Claims

1. An array substrate, comprising:

a substrate base plate;

a pixel circuit on one side of the substrate, the pixel circuit including a first transistor including a first active layer and a second transistor including a second active layer, the first and second active layers each including silicon;

2. The array substrate of claim 1, wherein the concentration of hydrogen ions in the first active layer is less than the concentration of hydrogen ions in the second active layer.

3. The array substrate of claim 1, wherein the first transistor further comprises a first source and a first drain, the first source and the first drain being electrically connected to the first active layer through a second via, respectively;

in the direction perpendicular to the substrate base plate, one end of the first via hole far away from the substrate base plate is closer to the substrate base plate than one end of the second via hole far away from the substrate base plate.

4. The array substrate of claim 1, wherein the first transistor is a driving transistor and the second transistor is a switching transistor.

5. The array substrate of claim 1, wherein the first via hole penetrates through the second type of inorganic layer.

6. The array substrate of claim 1, wherein the first via hole penetrates through the first inorganic layer and the second inorganic layer.

7. The array substrate of claim 1, wherein the pixel circuit further comprises a third transistor comprising a third active layer comprising an oxide semiconductor, and wherein the third active layer is located on a side of the first active layer away from the substrate;

the first type of inorganic layer and the second type of inorganic layer are located between the film layer where the first active layer is located and the film layer where the third active layer is located.

8. The array substrate of claim 7, wherein the pixel circuit further comprises a capacitor, and the capacitor comprises a first capacitor substrate and a second capacitor substrate which are oppositely arranged;

the first transistor further comprises a first grid electrode positioned on one side of the first active layer, which is far away from the substrate base plate, the first capacitor base plate and the first grid electrode are arranged on the same layer, and the second capacitor base plate is positioned on one side of the first capacitor base plate, which is far away from the substrate base plate;

the array substrate further comprises a first insulating layer positioned between the first active layer and the first grid electrode, a second insulating layer positioned between the first grid electrode and the second capacitor substrate, and a third insulating layer positioned between the second capacitor substrate and the third active layer;

at least one of the first insulating layer, the second insulating layer and the third insulating layer is a silicon nitride layer, and the first via hole penetrates through the silicon nitride layer.

9. The array substrate of claim 7, further comprising a third inorganic layer on a side of the second inorganic layer away from the substrate, wherein the third inorganic layer comprises a plurality of third inorganic layers, and wherein the third inorganic layer on a side of the second inorganic layer covers the second inorganic layer and fills the first via.

10. The array substrate of claim 9, further comprising a second via and a third via, each of the second via and the third via penetrating through the first inorganic layer type, the second inorganic layer type, and the third inorganic layer type; the vertical projection of the second via hole on the plane of the substrate base plate at least partially overlaps with the vertical projection of the first via hole on the substrate base plate, and the vertical projection of the second active layer on the substrate base plate covers the vertical projection of one end of the third via hole close to the second active layer on the plane of the substrate base plate;

the array substrate further comprises a fourth through hole, the fourth through hole penetrates through the third inorganic layer on the side, away from the substrate, of the third active layer, and the vertical projection of the third active layer on the substrate covers the vertical projection of one end, close to the third active layer, of the fourth through hole on the plane of the substrate;

the first transistor further comprises a first source and a first drain, the second transistor further comprises a second source and a second drain, and the third transistor further comprises a third source and a third drain; the first source electrode, the first drain electrode, the second source electrode, the second drain electrode, the third source electrode and the third drain electrode are arranged on the same layer;

the first source electrode and the first drain electrode are electrically connected with the first active layer through the second via hole; the second source electrode and the second drain electrode are electrically connected with the second active layer through the third via hole; the third source electrode and the third drain electrode are electrically connected to the third active layer through the fourth via hole.

11. The array substrate of claim 10, wherein the first transistor further comprises a first gate on one side of the first active layer;

the second transistor further comprises a second grid electrode positioned on one side of the second active layer far away from the substrate base plate;

the second active layer and the first active layer are arranged on the same layer, and the second grid electrode and the first grid electrode are arranged on the same layer.

12. The array substrate of claim 3, wherein an end of the first via near the substrate base plate does not overlap an end of the second via near the substrate base plate in a direction perpendicular to the substrate base plate.

13. A display panel comprising the array substrate according to any one of claims 1 to 12.

14. A display device characterized by comprising the display panel according to claim 13.