CN213877587U

CN213877587U - Memory cell and memory

Info

Publication number: CN213877587U
Application number: CN202023187287.3U
Authority: CN
Inventors: 杨晓蕾; 韩谷昌; 哀立波; 张恺烨; 刘波
Original assignee: Hikstor Technology Co Ltd
Current assignee: Hikstor Technology Co Ltd
Priority date: 2020-12-25
Filing date: 2020-12-25
Publication date: 2021-08-03
Anticipated expiration: 2030-12-25

Abstract

The application provides a memory cell and a memory. The memory cell includes: a first storage area including at least one first storage subunit; and the second storage area comprises at least one second storage subunit, and the characteristic size of the second storage subunit is larger than that of the first storage subunit. In the storage unit, two storage areas are provided, each storage area at least comprises one storage subunit, the first storage subunit with a small size can improve the storage density, fast read-write storage is realized, the energy barrier of the second storage subunit with a large size is high, the data storage time of the storage is long, the reflow soldering data retention capacity of the storage unit is good, and the storage unit well solves the problem that the pre-stored information after reflow soldering cannot be lost while the high erasable times, high density and high read-write speed of the storage unit are guaranteed in the prior art.

Description

Memory cell and memory

Technical Field

The present application relates to the field of memories, and more particularly, to a memory cell and a memory.

Background

STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory) is a potential new Memory as a Memory that changes MTJ (Magnetic Tunnel junction) state by current. The Memory has the advantages of simple circuit design, high read-write speed, infinite erasing and writing and the like, and has the greatest advantage of non-volatility (power-off data is not lost) compared with a traditional Memory such as a Dynamic Random Access Memory (DRAM). As shown in FIG. 1, for an MRAM data state diagram, the magnetic orientation of the free layer can be manipulated by an external field H or a write current I. When the free layer magnetization direction and the pinned layer are parallel or antiparallel, a 0 or 1 output data may correspond, respectively.

As a nonvolatile Memory, one core criterion of MRAM (Random Access Memory) is data retention time, which depends on the barrier height between two states in MTJ. Fig. 2(a) and 2(b) show schematic diagrams of potential barriers corresponding to in-plane magnetization and perpendicular magnetization, respectively.

For the application of the eMRAMs (embedded MRAM), the memory chip is soldered to the PCB through a reflow soldering process, so that the chip needs to ensure that the pre-stored data is not lost in the process.

The reflow soldering corresponds to a high temperature process as shown in fig. 3, and the maximum temperature can reach 260 ℃. This means that for an eMRAM chip, its basic memory cell MTJ needs to ensure that data can be preserved without loss when passing through a high temperature of 260 ℃.

For the MTJ device, the data storage at 260 ℃ is not lost, that is, the reduced energy barrier height of the MTJ device at 260 ℃ needs to satisfy Δ > 41 × ln (N), where N represents an array of N bits.

To ensure that the MTJ device does not lose its data when stored at 260 deg.C, the most effective way to increase its reduced energy barrier height Δ is to increase the anisotropic performance density H_K. But increaseH_KWill cause V_CAt the same time increase, and V_CThe increase will affect the number of erasability.

Another way to raise the height of the energy barrier is to increase the volume V.

However, increasing V increases Ic, increases power consumption, and decreases read/write speed and memory density.

Therefore, there is a need for a memory that ensures high erasable times, high read/write speed, and high density of the memory, and that pre-stored information is not lost after reflow soldering.

The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

SUMMERY OF THE UTILITY MODEL

The main objective of the present application is to provide a storage unit and a memory, so as to solve the problem that the information pre-stored after reflow soldering is not lost while the high erasable times, high read-write speed and high density of the memory cannot be guaranteed in the prior art.

In order to achieve the above object, according to one aspect of the present application, there is provided a memory cell including: a first storage area including at least one first storage subunit; and the second storage area comprises at least one second storage subunit, and the characteristic size of the second storage subunit is larger than that of the first storage subunit.

Further, the first storage subunit and the second storage subunit have the same structure.

Further, the feature sizes of the first storage sub-units are the same, and the feature sizes of the second storage sub-units are the same.

Further, the characteristic size of the first storage subunit is 40nm to 70 nm.

Further, the first storage area further includes a plurality of first switches, the first switches are connected to the first storage subunits in a one-to-one correspondence manner, the second storage area further includes a plurality of second switches, the second switches are connected to the second storage subunits in a one-to-one correspondence manner, and a current of the first switches in a saturation region is smaller than a current of the second switches in the saturation region.

Further, the first switch is a first MOS transistor, and the second switch is a second MOS transistor.

Further, the first storage sub-cell is a first MTJ and the second storage sub-cell is a second MTJ.

Further, the thin film structures of the first MTJ and the second MTJ are the same.

Further, the first MTJ includes a first fixed layer, a first tunnel layer, and a first free layer that are sequentially stacked, and the second MTJ includes a second fixed layer, a second tunnel layer, and a second free layer that are sequentially stacked, a magnetization direction of the first fixed layer is perpendicular to a magnetization direction of the first free layer, and a magnetization direction of the second fixed layer is perpendicular to a magnetization direction of the second free layer.

According to another aspect of the present application, there is provided a memory including any one of the memory cells.

By applying the technical scheme of the application, the storage unit has two storage areas in total, each storage area at least comprises one storage subunit, the first storage subunit with smaller size can improve the storage density and realize the fast read-write storage, the second storage subunit with larger size has higher energy barrier, the data storage time of the storage is ensured to be longer, so that the reflow soldering data retention capacity of the storage unit is better, thus, the memory unit of the application ensures high erasable times, high read-write speed and high density of the memory, the method and the device ensure that the information prestored in the storage unit is not lost after reflow soldering, and better solve the problem that the information prestored after reflow soldering cannot be ensured to be not lost while ensuring high erasable times, high read-write speed and high density of the memory in the prior art.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:

FIG. 1 illustrates an MRAM data state diagram;

FIG. 2(a) shows a schematic diagram of the potential barrier for in-plane magnetization;

FIG. 2(b) shows a schematic diagram of the potential barrier for perpendicular magnetization;

FIG. 3 shows a schematic diagram of a high temperature process corresponding to reflow soldering;

FIG. 4 shows a schematic structural diagram of a memory cell according to an embodiment of the present application;

FIG. 5 shows a schematic of a first MTJ structure;

fig. 6 shows a structural schematic diagram of a second MTJ.

Wherein the figures include the following reference numerals:

10. a first storage area; 20. a second storage area; 11. a first fixed layer; 12. a first tunnel layer; 13. a first free layer; 21. a second fixed layer; 22. a second tunnel layer; 23. a second free layer.

Detailed Description

It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.

As described in the background art, in the prior art, it is not possible to ensure that the pre-stored information is not lost after reflow soldering while ensuring high erasable times, high read-write speed, and high density of the memory.

According to an embodiment of the present application, there is provided a memory cell, as shown in fig. 4, including:

a first memory area 10 comprising at least one first memory subunit;

the second storage area 20 includes at least one second storage subunit, and the characteristic size of the second storage subunit is larger than that of the first storage subunit.

In the storage unit, two storage areas are provided, each storage area at least comprises one storage subunit, the first storage subunit with a smaller size can improve the storage density, and realize fast read-write storage, the second storage subunit with a larger size has a higher energy barrier, and the data storage time of the storage is longer, so that the reflow soldering data retention capacity of the storage unit is better.

It should be noted that the first storage subunit has a small characteristic dimension, a large resistance and a low flip current, and thus ensures that the area of the first storage region is small, high-density and fast read-write storage can be achieved, the second storage subunit has a large characteristic dimension, a small resistance and a large flip current, and ensures that the area of the second storage region is large, the energy barrier of the second storage subunit is high, and the second storage subunit has the advantage of long data storage time, and the second storage region can be used as a storage region for storing pre-stored information in an embedded chip by reflow soldering.

In an embodiment of the present application, the first storage subunit and the second storage subunit have the same structure. In the embodiment, the number of layers, the type of the structural layer and the position relationship of the layers of the two storage subunits are the same, so that the first storage subunit and the second storage subunit are simple to manufacture, and the storage units can be manufactured by workers more conveniently. In addition, the process controllability is high, and the process introduced variable is small, so that the storage unit can be used for large-capacity read-write storage.

In another embodiment of the present application, the feature sizes of the first storage sub-units are the same, and the feature sizes of the second storage sub-units are the same. In this embodiment, because the characteristic dimensions of the plurality of first storage sub-units are the same, the manufacturing process of the storage unit is easier, and the manufacturing of the storage unit is more convenient.

It should be noted that the feature sizes of the first storage sub-units may be different, and the feature sizes of the second storage sub-units may be different.

In yet another embodiment of the present application, the feature size of the first memory sub-unit is 40nm to 70 nm.

Of course, the feature size is not limited to the above feature size, and other feature sizes may be used, and those skilled in the art may select an appropriate feature size according to actual situations.

In yet another embodiment of the present application, the first storage area further includes a plurality of first switches, the first switches are connected to the first storage sub-units in a one-to-one correspondence, the second storage area further includes a plurality of second switches, the second switches are connected to the second storage sub-units in a one-to-one correspondence, and a current of the first switches in a saturation region is smaller than a current of the second switches in a saturation region. In this embodiment, the current of the first switch in the saturation region is small, that is, the area of the first storage region is small, so that the first storage sub-unit can store the current quickly, and the current of the second switch in the saturation region is large, that is, the area of the second storage region is large, so that the energy barrier is further high.

In a specific embodiment of the present application, the first switch is a first MOS transistor, and the second switch is a second MOS transistor. This can further ensure better performance of the memory cell.

In another specific embodiment of the present application, the first memory sub-cell is a first MTJ, and the second memory sub-cell is a second MTJ. In this embodiment, MTJ is used as the memory sub-cell, which further ensures better performance of the memory cell. Of course, the first storage subunit and the second storage subunit may be other electromagnetic elements.

Specifically, for the single domain case, the data retention times of the first MTJ and the second MTJ of the present application are respectively proportional to the square of their characteristic dimensions, and for the multi-domain case, the data retention times of the first MTJ and the second MTJ of the present application are respectively proportional to their characteristic dimensions.

In yet another embodiment of the present application, the thin film structures of the first MTJ and the second MTJ are the same. Therefore, the first MTJ and the second MTJ are simple to manufacture, and the two MTJs are further convenient for workers to manufacture.

In still another embodiment of the present application, as shown in fig. 5 and 6, the first MTJ includes a first fixed layer 11, a first tunnel layer 12, and a first free layer 13, which are sequentially stacked, the second MTJ includes a second fixed layer 21, a second tunnel layer 22, and a second free layer 23, which are sequentially stacked, a magnetization direction of the first fixed layer 11 is perpendicular to a magnetization direction of the first free layer 13, and a magnetization direction of the second fixed layer 21 is perpendicular to a magnetization direction of the second free layer 23. In this embodiment, the storage capacities of the first MTJ and the second MTJ are further ensured to be better, so that the storage capacity of the memory cell is better.

In practical applications, each of the first MTJ and the second MTJ may further include other layers, such as a capping layer, a top electrode, a bottom electrode, and the like, and those skilled in the art may select the structures of the first MTJ and the second MTJ according to practical situations.

Specifically, in one embodiment, the material of the first free layer and the second free layer includes at least one of Co, Fe, Ni, CoB, FeB, NiB, CoFe, NiFe, CoNi, CoFeNi, CoFeB, NiFeB, CoNiB, CoFeNiB, FePt, FePd, CoPt, coppt, CoFePt, feppd, CoPtPd, and CoFePtPd, and the material of the first fixed layer and the second fixed layer includes at least one of Co, Fe, Ni, CoB, FeB, NiB, CoFe, NiFe, CoNi, CoFeB, CoFeNiB, FePt, FePd, CoPd, CoPt, CoPd, CoFePt, CoFePtPd, CoFePt.

According to an embodiment of the present application, there is also provided a memory including any one of the above-described memory cells.

In the memory, because the memory unit is included, the memory unit has two memory areas in total, each memory area at least includes one memory subunit, the first memory subunit with smaller size can improve the memory density and realize the fast read-write memory, the second memory subunit with larger size has higher energy barrier, thus ensuring the longer data storage time of the memory and leading the reflow soldering data retention capability of the memory unit to be better, thus, the memory unit of the application ensures high erasable times, high read-write speed and high density of the memory, the method and the device ensure that the information prestored in the storage unit is not lost after reflow soldering, and better solve the problem that the information prestored after reflow soldering cannot be ensured to be not lost while ensuring high erasable times, high read-write speed and high density of the memory in the prior art.

From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:

1) the utility model provides a storage unit, two total storage areas, each storage area has all included a storage subunit at least, the density of storage can be improved to the less first storage subunit of size, realize quick read-write storage, the energy barrier of the great second storage subunit of size is higher, the data save time of having guaranteed the memory is longer, make the reflow soldering data retention ability of this storage unit better, thus, above-mentioned storage unit of this application is when guaranteeing the high number of times of erasing and writing of memory, high read-write speed, high density, guaranteed that this storage unit does not lose after reflow soldering prestore information, can't guarantee among the prior art the high number of times of erasing and writing of memory, high read-write speed, high density while, guarantee that reflow soldering prestore information does not lose the problem.

2) The memory of the application comprises the memory unit, in the memory unit, the two storage areas are total, each storage area at least comprises one storage subunit, the first storage subunit with smaller size can improve the storage density and realize the fast read-write storage, the second storage subunit with larger size has higher energy barrier, the data storage time of the memory is ensured to be longer, the reflow soldering data retention capability of the storage unit is better, thus, the memory unit of the application ensures high erasable times, high read-write speed and high density of the memory, the method and the device ensure that the information prestored in the storage unit is not lost after reflow soldering, and better solve the problem that the information prestored after reflow soldering cannot be ensured to be not lost while ensuring high erasable times, high read-write speed and high density of the memory in the prior art.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A memory cell, comprising:

a first storage area including at least one first storage subunit;

and the second storage area comprises at least one second storage subunit, and the characteristic size of the second storage subunit is larger than that of the first storage subunit.

2. The memory cell of claim 1, wherein the first memory sub-cell and the second memory sub-cell are identical in structure.

3. The memory cell of claim 1, wherein the first memory sub-cells have the same feature size and the second memory sub-cells have the same feature size.

4. The memory cell of claim 1, wherein the first memory sub-cell has a feature size of 40nm to 70 nm.

5. The memory cell of claim 1, wherein the first memory region further comprises a plurality of first switches, the first switches are connected to the first memory sub-cells in a one-to-one correspondence, the second memory region further comprises a plurality of second switches, the second switches are connected to the second memory sub-cells in a one-to-one correspondence, and a current of the first switches in a saturation region is smaller than a current of the second switches in the saturation region.

6. The memory cell of claim 5, wherein the first switch is a first MOS transistor and the second switch is a second MOS transistor.

7. The memory cell of any of claims 1 to 6, wherein the first memory sub-cell is a first MTJ and the second memory sub-cell is a second MTJ.

8. The memory cell of claim 7, wherein the thin film structures of the first MTJ and the second MTJ are the same.

9. The memory cell of claim 7, wherein the first MTJ comprises a first fixed layer, a first tunnel layer, and a first free layer stacked in this order, wherein the second MTJ comprises a second fixed layer, a second tunnel layer, and a second free layer stacked in this order, wherein a magnetization direction of the first fixed layer is perpendicular to a magnetization direction of the first free layer, and wherein a magnetization direction of the second fixed layer is perpendicular to a magnetization direction of the second free layer.

10. A memory comprising a memory cell according to any one of claims 1 to 9.